컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley

컴퓨터구조론

교수 채수환

교재

Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley

평가방법

중간고사 40%학기말 고사 40%레포트 및 출석 20%계 100%

단 결석 ¼ 이상은 F 학점

What must you do as a junior student

Improve your grade up to at least 3.5/4.5. Cultivate your English ability.Make good relationship with your friends.Think your future seriously.Be an expert in your field.Be flexible.

Chapter 1 Digital Logic Fundamentals

Boolean AlgebraBasic Combinatorial LogicMore Complex Combinatorial ComponentsCombinatorial Circuit DesignBasic Sequential ComponentsMore Complex Sequential ComponentsReal World Example: PLD

1.1 Boolean Algebra

Basic FunctionsAND NANDOR NOR NOTXOR XNOR (or Equivalence)Table 1.3: All possible binary Boolean

functions

1.1 Boolean Algebra( 계속 )

Manipulation of Boolean AlgebraDeMorgan’s LawMintermKarnaugh map(K-map)


DeMorgan’s Law It allows a digital designer to convert an AND

function to an equivalent OR function and vice versa.

(ab)’=a’+b’ (a+b)’=a’b’

Example: (xy’+yz)’=(xy’)’(yz)’=(x’+y)(y’+z’)

=x’y’+x’z’+yy’+ yz’ = x’y’+x’z’+ yz’


MintermEach possible AND set of input values If there are two input values, x and y,

there are four possible minterms: x’y’, x’y, xy’, xy


K-map (Karnaugh-map)A useful device for minimizing logic

Figure 1.1 K-maps


K-mapThe ordering of K-map inputs: Gray

codeA Gray code is a reflected code.

Figure 1.2 Gray code sequence generation


Grouping on K-mapPrime Implicants(PI)Essential Prime Implicants(EPI):

groups which include cells that covered by only one group.

Figure 1.3 (xy’+yz)’

Figure 1.4 More complex function


Don’t careWhen some patterns of input values

will never occur, it is called don’t care condition.

We can treat the don’t care values as either 0 or 1, whichever makes it easier to group the minterms.

Figure 1.5 A 7-segment LED driver

1.2 Basic Combinatorial Logic

Gates: digital components that implement the logic functions. AND OR NOR NOT NAND NOR XNOR

Figure 1.6 Logic Symbols

1.2 Basic Combinatorial Logic(continued)

The gates can be combined to realize more complex functions.There are some realization ways for a given complex functions depending on the conditions.

Figure 1.7 Two realization of the function wx’+x’z’+w’xyz

1.2 Basic Combinatorial Logic(continued)

Buffers: Buffers do not perform any operations on its input.Regular buffer: to boost the current of

input to a higher level Tri-state buffer: it has a data input,

just like the regular buffer, but also an enable input, E.If E is disable state, it produces a high

impedance output.

Figure 1.8 Logic symbols for buffers

Buffers:

Regular buffers(simply buffers): for boosting the current

Tri-state buffers: enable, high-impedance

1.3 More Complex Combinatorial ComponentsMultiplexer(MUX) It chooses one of its data inputs and

passes it through to its output.Select signals are needed for select a

data input

Figure 1.9 (a) Internal configuration of 4-to-1 MUX

Figure 1.9 (b) Schematic representation with an active high enable signals

Figure 1.9 (c) Schematic representation with an active low enable signals

Figure 1.10 A 4-to-1 MUX constructed using 2-to-

1 MUXs

1.3 More Complex Combinatorial Components(continued)

Decoder It accepts a value and decodes it. It has n inputs and 2n outputs,

numbered from 0 to 2n–1.

Figure 1.11 Internal Configuration of a 2-to-4

decoder


Page 19, Figure 1.11 (c) Schematic representation with an active low enable signals


Encoder It is the exact opposite of the

decoder. It receives 2n inputs and outputs an n-

bit value corresponding to the input value.

Figure 1.12 (a) Internal Configuration of

a 4-to-2 encoder


Figure 1.12 (c) Schematic representation with an active low enable signals


Priority encoderThe encoder works if zero or one

inputs are active, but fails.A priority encoder works just like a

regular encoder, with one exception, Whenever more than one input is active, the output is set to corresponding to the highest active input.

Figure 1.13 (a) A 4-to-2 priority encoder

Figure 1.13 (b) and (c) The other 4-to-2 priority encoder and its truth table


Comparator It compares two n-bit binary values to

determine which is greater, or if they are equal.

Figure 1.14 1-bit comparator

Figure 1.15 1-bit comparator with propagated inputs

Figure 1.16 n-bit comparator constructed using 1-bit comparators with propagated inputs


AdderAdders are most commonly used, not

only to perform addition, but also to perform subtraction, multiplication, and division.Half adderFull adderRipple adderCarry lookahead addeer

Figure 1.17 A half adder

Figure 1.18 a full adder

Figure 1.19 4-bit adder constructed using full adders


Full subtracterA full subtracter(Figure 1.20)Two’s complement addition

By doing this, a CPU may use a parallel adder for addition and subtraction.

Figure 1.20 A full subtracter

1.3 More Complex Combinatorial Components( 계속 )

Memory It is a group of circuit used to store

data.Address inputsData linesClasses of memory chips depending on

volatilityROMRAM

Figure 1.21 ROM and RAM

1.4 Combinatorial Circuit Design

BCD to 7-Segment Decoder

Figure 1.22 A 7-Segment LED display

Figure 1.23 (a) K-maps for designing segments

Figure 1.23 (b) Circuits to implement segments b and c

Figure 1A : LEDS (a) active high (b) active low

1.4 Combinatorial Circuit Design(continued)

A sorter

Figure 1.24 (a) A two-input compare-and –swap module

Figure 1.24 (b) four-input data sorter

1.5 Basic Sequential Components

The most fundamental components are latch and flip-flop Latch: level-triggered Flip-Flop: edge-triggered Triggering

Positive Negative

Clock It is used to synchronize the flow of data in

a digital system

Figure 1.25 clock sequence

1.5 Basic Sequential Components(continued)

D latch and D F-F It has one input, D, and a clock input. The value of D becomes output, Q,

after some delay. LD signal: It must be high as the clock

changes from 0 to 1 in order for the data to be loaded into the F-F.

Figure 1.26 (a) Positive-edge triggered D F-F

Figure 1.26 (b) Positive-level triggered D latch

Figure 1.27 Positive level triggered D latch with set and clear

Figure 1.28 SR latch


JK-FF It resolves the problem of undefined

when SR=11

Figure 1.29 J-K F-F

Figure 1.30 T F-F


Flip-flops and latches may be combined in parallel to store data with more than one bit.

Figure 1.31 4-bit D F-F

1.6 More Complex Sequential Components

Counters It stores a binary value and, when

signaled to do so, arithmetically increases or decreases its value.

Ripple counterUp/down counter

Figure 1.32 4-bit Counter

Figure 1.33 4-bit up/down counter

1.6 More Complex Sequential Components

Shift registers it can shift data one bit position to

the right or left. It is particularly useful for certain

hardware multipliers and dividers.

Figure 1.34 4-bit left-shift register

1.7 Real World Example

PLAPALPLDFPGA

Figure 1.35 PLA programmed b=x2’+x1’x0’+x1x0 and c=X2+X1’+X0

Figure 1.36 PAL programmed b=x2’+x1’x0’+x1x0 and c=X2+X1’+X0

Documents

컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley