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电子设计自动化技术( EDA )

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电子设计自动化技术( EDA ). 王 巍. 电子设计自动化技术( EDA). 绪论. 教材或参考书. 1. 李国丽等 编著 《EDA 与数字系统设计 》 机械工业出版社, 2004. 2. 徐志军、徐光辉 编著 《CPLD/FPGA 的开发与应用 》 电子工业出版社, 2002.1. 3. 刘宝琴、张芳兰等编著 《ALTERA 可编程逻辑器件及其应用 》 清华大学出版社, 1995. 4. 侯伯亨、顾新编 《VHDL 硬件描述语言与数字逻辑电路设计 》 电子科技大学出版社, 1995. 电子设计自动化技术( EDA). 绪论. 教材或参考书. - PowerPoint PPT Presentation

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  • EDA

  • EDA) 2. CPLD/FPGA2002.13. ALTERA 19951. EDA20044. VHDL 1995

  • EDA) 5. CPLD 19996. VHDL 20007.Kevin Skahill VHDL 1999

  • MAXPlus II VHDL EDA)

  • EDA)1 . EDAEDAHDLEDA (ASIC) PLD

  • EDA)2 . 30 104/ : : EDA : :30 :

  • EDA)

  • EDA)74/54TTL40004500CMOS

  • EDA)

  • EDA)

  • EDA)1. 2. 3.

  • EDA)System On ChipEDAEDA

  • EDA)EDAEDAHDL

  • EDA)EDA EDAElectrion Design Automation)90CADCAMCATCAE EDAEDAASICSOCEDA

  • EDA)EDA70CADLSIPCBTANGO80CAMCATCAEEDA90EDA

  • EDA)EDAEDAIPIntellectual Property PLDISP

  • EDA)EDA

  • EDA)EDA

  • EDA)EDATOPDOWNVHDL

  • EDA)EDA5. a b c6.FPGACPLD

  • EDA)CMOSPMOSNMOSCMOSBiMOS BiMOSBiCMOSSSIMSILSISmallMediumLargeVLSIVery Large Scale IC:105ULSIUltra Large Scale IC106GSIGigantic Scale IC:ICICICICICASIC

  • EDA)(ASIC)

    RAMROMSSIMSILSI 744000 CPUDSPPLCPROMPLAPALGALCPLDFPGA

  • EDA)1.PROMPLAPALGALEPLDCPLDFPGA

  • EDA)2./ SPLDPROM PLA PALGALCPLDEPLD,PLD FPGA

  • EDA)3.OTP(One Time Programmable) 1. ActelFPGASRAM XilinxFPGAEEPROM3. UEPROM/ EPLD4. EEPROMFLASHGALCPLD

  • EDA)ISPIn System Programmable)EEPROMFLASHICPIn Circuit ReconfigurabilitySRAMEPROMEEPROMSRAM

  • EDA)PAD1999LatticeIn System Programmability Analog Circuits

  • EDA)70PROMPLA70AMDPAL80LatticeGAL80XilinxFPGA;AlteraEPLD80LatticeISP90CPLDEPLD

  • EDA) PLD

  • EDA) EDAEDA

  • EDA) HDL1. VHDLVery High Speed Integrated Circuit Hardware Description Language, 2. Verilog-HDL Verilog Hardware Description Language3. AHDLAltera Hardware Description Language4.SystemC

  • EDA)EDAEDA EDAEDASOCHDL

  • EDA)EDA EDAEDA EDA ASICSOCEDAEDA

  • EDA) EDAESDACEESDAEDA

  • 1-1 EDAEDA 1-2 EDAASICFPGA 1-3 VHDL 1-4 1-5 EDA 1-6 IPEDA 1-7 DSPFPGA

  • EDA)

  • Product Term

  • 01:

    L3

    L2

    G1

    A

    B

    L1

    _992243021.vsd

    B

    A

    D

    EMBED Visio.Drawing.4

    C

    L=A+B+C+ D DDDD

    _992243021.vsd

    _992248400.vsd

  • PLD

    A

    B

    EMBED Visio.Drawing.4

    EMBED Visio.Drawing.4

    Z

    Y

    _992246132.vsd

    _992246194.vsd

    _992246203.vsd

    _992243021.vsd

  • 2.4.1 PROMPROM2.2 PROMPLAPALGAL

  • 2.4.2 PLA2.2 PROMPLAPALGALPROM

  • 2.4.3 PAL I/O 2.2 PROMPLAPALGAL

  • PAL An Bn Cn Cn+1 Sn

  • AnBnCnAnBnAnCnBnCn

    EMBED Visio.Drawing.4

    EMBED Visio.Drawing.4

    ()

    Cn+1

    Sn

    An

    Bn

    Cn

    _992246203.vsd

  • PAL(1) PAL(2) TTLCCMOS;(3) PAL(4) (5) (6)

  • 1 PAL

    H

    (Active-High Output)

    PAL10H8

    L

    (Active-Low Output)

    PAL16L8

    P

    (Programmable Output Polarity)

    PAL16P8

    C

    (Complementary Output)

    PAL16C1

    X

    (Exclusive-OR Gate)

    PAL20(10

    R

    (Registered Output)

    PAL16R8

    RP

    (Registered with Programmable Proarity)

    PAL16RP8

    RA

    (Registered Asynchronous)

    PAL16RA8

  • 188/88 1CLK 1

  • OLMC111DSYN

  • OLMC1. 2. /3. 4. 5.

  • GAL

  • PROMPLAPALGAL

  • CPLD PLDCPLDComplex Programmable Logic Device PLDPCBPLDCPLD22V10PLD.

  • CPLDCPLD1. 2. I/O;3.

  • CPLD

  • CPLDAlteraMAX7000SI/O(Logic Array Block)(MacroCell)

  • MAX7128SCPLDAlteraMAX7000S

  • CPLD

  • CPLDCPLD22V10PLD1. Product-Term Array2. Product-Term Distribution3. Programmable Register)

  • MAX7000

  • (1)

    /

    VinGNDVref

    D1D4

    Sign

    ENB

    A

    H

    Q1

    Q8

    ENB

    AD

    Q1Q4

    ENB

    MA

    MB

    MC

    1

    11

    10

    01

    00

    R

    J

    Q

    Q

    K

    D

    L

    S

    R

    11

    10

    01

    00

    R

    11

    10

    01

    00

    R

    J

    Q

    Q

    K

    D

    L

    S

    R

    J

    Q

    Q

    K

    D

    L

    S

    R

    11

    10

    01

    00

    R

    J

    Q

    Q

    K

    D

    L

    S

    R

    1

    J

    OLMC

    S

    J

    OLMC

    S

    J

    OLMC

    S

    OLMC

    OLMC

    1

    OLMC

    OLMC

    OLMC

    1

    2

    I

    I

    0

    7

    19

    I/O/Q

    CLK

    0 3

    4 7

    8

    12

    11

    15

    16

    19

    20

    23

    24

    27

    28

    31

    1

    I/CLK

    I

    3

    I

    I

    8

    15

    18

    I/O/Q

    OE

    4

    I

    I

    16

    23

    17

    I/O/Q

    5

    I

    I/OE

    24

    31

    16

    I/O/Q

    6

    I/O/Q

    I/O/Q

    32

    39

    15

    I/O/Q

    7

    I/O/Q

    40

    47

    14

    8

    48

    55

    13

    9

    56

    63

    12

    11

    Vcc

    SG1

    SL0

    7

    SL1

    7

    SG0

    SL0

    6

    19

    I/O

    7

    Vcc

    SG1

    1

    SL0

    6

    SL1

    6

    SG1

    SL0

    6

    18

    I/O

    6

    CLK/I

    0

    2

    I

    1

    3

    I

    2

    0

    7

    8

    15

    0 3

    4 7

    8

    12

    16

    20

    24

    28

    11

    15

    19

    23

    27

    31

  • CPLD

  • CPLD

  • CPLD

  • CPLD

  • CPLDI/OCPLD100

  • I/OTTLCMOS1.20.5um,5V0.35um,3.3V0.25um,internal 2.5V,I/O3.3V0.18um,internal 1.8V,I/O2.5V and 3.3V

    CPLD

  • EPM7128SI/O

  • FPGAFPGA1. CLB2. /IOB3. PICIOBCLBPIC

  • FPGA

  • FPGA

  • FPGA FPGAFPGA1. 2.

  • FPGAFPGA FPGA SRAMM2MSRAMSRAMSRAMSRAM

  • 0000010100000101 A B C D 16x1RAM

    LUT

    1

    2

    3

    4

  • N2NSRAM

  • FPGAFPGA MM2MSRAM SRAM

  • FPGAFPGA FPGA55 AnBnCnSnCn+1

  • AnBnCnSnCn+10000000110010100110110010101011100111111

  • FPGAFPGA

  • FPGAFPGA FPGA

  • FPGA21sabf=sa+/sbFPGAACTEL1. s=1 f=sa;2. a=1 f=s+b;3. a=/b f=sb;

  • FPGAFPGA

  • FPGAFPGA 8F=/(S3+S4)(/S2W+S1X)+(S3+S4)(/S2Y+S2Z)

  • CPLDFPGA

  • FPGACPLDFPGASRAMSRAMFPGAEPROMSRAMCPLDEEPROMEEPROM

  • FPGACPLDFPGACLBCPLD

  • FPGACPLDFPGACPLDFPGACLBCPLDCPLDFPGA

  • FPGACPLDFPGACPLDFPGACPLDCPLDCPLD

  • PLDEPM7 128 S L C 8410EPM7EPM7000128128S5VAE3.3VB2.5VLPLCCQPQFPCCommercial070IIndustry4085MMilitary551258410

  • VCCGNDVCCVCCINTVCCIOJTAGFPGAEEPROM

  • 2083.3VI/O2.5V250MHz49921049152 bitRAM

  • 1. 0.35um CMOS4002. PLDAIn-System Programming CPLDE2PROMPCBFPGASRAM

  • 3.3.3V2.5V1.8VCPU4.5.6.RAMROMFIFODSPCPU

  • FLEX FLEX10K 1. FLEX10K CMOS SRAM

  • Altera PLD 25 32 FLEX10K FLEX10KA FLEX10KV FLEX10KE

  • FLEX10K FLEX10K PROM

  • AlteraEPC1 EPC2 EPC16EPC1441PROM RAMBitBlasterByteBlasterMV ICR, In Circuit Reconfigurability 320 ms FLEX10KMAX+PLUS

  • 2. FLEX10K (1) FLEX10KPLD (SOPC) (2) 1~25 40960RAMEAB2048

  • (3) FLEX10KA5.0 V FLEX10KB3.3 V5.0 V 0.5 mA PCI JTAG 2.5 V 3.3 V 5.0 V 100%

  • (4) Fast Track

  • (5) I/O Open drain option FLEX10KA FLEX10KE FLEX10KS (6) 84600 PLCC TQFP PQFP RQFP PGA BGA FLEX10K 2.2FLEX10K

  • FLEX10K

  • FLEX10KFLEX 10K...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOC...IOCIOCEABEAB(EAB)(LE)(Fast Track) (LAB)

  • (1) LELE(LC)

  • (1) LE(Logic Element)LABLE, LE0.2 ns

  • FLEX10Kn

  • (1) LE

  • (2) LABLEFLEX10K LAB

  • (3) (FastTrack) = ( Altera LUT FPGA )

  • AlteraPLD

  • FLEX10K

  • (4) I/OIO

  • 5FPGAEABEABRAMRAM;RAMROMRAMFIFOStack; DSP25685124;

  • FLEX10KEAB

  • EAB

    EAB EAB 2048EAB

  • EAB

  • EAB

  • ACEX1K ACEX1KLUTEAB LUT DSP EABRAM ROM RAMFIFO ACEX1K

  • CMOS SRAM ACEX1K 2.5 VACEX1K DSL

  • ACEX1K EAB EAB4096 LAB LABLE LELUT LE LAB LAB96 ACEX1K

  • ACEX1K

  • ACEX1K20002.5 VSRAMPLDFPGA FLEX10KEFLEX10K EAB PLL LEEAB ACEX1KEP1K30 EP1K50 EP1K100FLEX10KEEPF10K30E EPF10K50E EPF10K100E EAB4 kb

  • Altera

  • Altera

  • FPGA/CPLDJTAG

  • JTAGBST Boundary Scan TestIEEE1149.1JTAGISPDSP

  • JTAGIO

    TDI

    (Test Data Input)

    TCK

    TDO

    (Test Data Output)

    TCK

    TMS

    (Test Mode Select)

    TAPTMSTCK

    TCK

    (Test Clock Input)

    BST

    TRST

    (Test Reset Input)

    (IEEE)

  • JTAG

  • JTAG BST

  • JTAG BSTFLEX

  • CPLDFPGA10

    1

    2

    3

    4

    5

    6

    7

    8

    9

    10

    PS

    DCK

    GND

    CONF_DONE

    VCC

    nCONFIG

    -

    nSTATUS

    -

    DATA0

    GND

    JATG

    TCK

    GND

    TDO

    VCC

    TMS

    -

    -

    -

    TDI

    GND

  • CPLDISPCPLDTCKTDOTMSTDICPLDJTAGCPLD

  • CPLDISPCPLDISP

  • PCFPGAFPGA SRAMconfigure ICRin-circuit ReconfigurabilityCPLDISPFPGA12PSPassive Serial3PPSPassive Parallel Synchronous4PPA Passive Parallel Asynchronous5PSA Passive Serial Asynchronous6JTAGFPGAMSEL0MSEL1MESL1=0MESL0=0PSMESL1=1MESL0=0PPS

  • FPGA

  • FLEXACEXAPEX FPGAFLEXACEXAPEXFPGA FPGA Passive Serial Configuration 10/PCFPGA

  • PLDwww.altera.comPLDwww.xilinx.comFPGAPLDwww.latticesemi.comISPwww.actel.com

  • ALTERAFPGA FLEX10K10A10KEEPF10K30E APEX20K20KE EP20K200E ACEX1K EP1K30EP1K100 STRATIXEP1 EP1S30EP1S120CPLD MAX7000/S/A/BEPM7128S MAX9000/AFPGA XC3000 XC4000 XC5000 Virtex SPARTANXCS10XCS20XCS30CPLD XC9500XC95108XC95256XILINX

  • LATTICEVANTISAMDispLSI1K2K3K5K8K ispLSI1016 ispLSI2032ispLSI1032EispLSI3256A MACH ispPAC PLDACTEL ACT1/2/340MXATMELATF1500AS40MXCYPRESSQUIKLOGIC CPLD

  • ALTERA FPGA FLEX10K10A10KEEPF10K30E APEX20K20KE EP20K200E ACEX1K EP1K30EP1K100 STRATIXEP1 EP1S30EP1S120 CYCLONEEP1C20

    EXCALIBUR

    CPLD MAX7000/S/A/BEPM7128S MAX9000/A MAX3000

  • PLD 2.8.1 PLD XILINXFPGA XC9500/4000 CoolrunnerXPLA3 SpartanVertex Foundition Xilinx Altera PLD/FPGA60%AlteraXilinx AlteraXilinxPLD

  • Lattice Vantis LatticeISP ISPPLD AlteraXilinx AlteraXilinx PLD PLDLatticeFPGA 1999 VantisAMD ispLSI2000/5000/8000 MACH1/2 MACH4/5 ispDesignEXPERT

  • ActelPLD PLD / AlteraXilinx Cypress PLD/FPGACypress QuicklogicPLD/FPGA

  • LucentIP PLD/FPGALucent ATMEL PLD/FPGAATMEL PLD ATMELAlteraXilinx Clear Logic PLD/FPGA

  • WSI PSD PLD PSD8xx PSD9xx PLD EPROM Flash 20008WSIST

  • Xilinx Xilinx1984 FPGA 1999XilinxPhilipsPLD Xilinx PLD CPLDXC9500 CoolrunnerXPLA3 FPGAVertex Spartan XC4000 XC3000XC5200

  • Xilinx Foundation Series Foundation SeriesPC XilinxFPGACPLD Foundation Series Foundation SeriesFoundation Project ManagerXilinx

  • Foundation SeriesSynopsysFPGA ExpressSynopsys FPGA ExpressFoundation SeriesVHDLVerilog HDL JTAGCPLDFPGA

  • Alliance Series Xilinx Xilinx Alliance EDAEDA AllianceFPGACPLD EDA

  • WebpackXilinx Foundation Xilinx ISEXilinx Xilinx (1) XC9500 FlashPLD XC9536 XC9572 XC95144 2.11XC9500

  • XC9500

  • (2) CoolRunnerPhilipsPLD 1999Xilinx XCR3256XL XCR3320 XCR3384 XCR3960 2.12CoolRunner (3) XC4000XC4000E5 V XC4000XL/XLA3.3 V XC4000XV2.5V 648464CLB

  • CoolRunner

  • (4) SPARTAN SRAMFPGA SPARTANSPARTAN (5) Virtex SRAMFPGA Virtex XCV812E XCV405E Vertex-SRAMFPGA Vertex

  • Virtex

  • Xilinx Virtex Virtex FPGAFPGA Virtex FPGAFPGAVirtex Virtex VirtexSelect I/O

  • Virtex FPGADLL Virtex SelectRAM+RAM RAM SDRAM ZBT SRAMDDR Virtex FPGA

  • Virtex FPGA XilinxVirtex-E FPGA 320Virtex-EASIC Virtex-E FPGA0.18 m 21

  • Virtex-E FPGA 832 KBRAM 8DLL 20 LVDS Bus LVDSLVPECL Virtex-E100 Gb/sI/O

  • VirtexVirtex-EFPGA IP Virtex PCIDSP Virtex-XilinxPlatform FPGA EMI Virtex-XC2V40 XC2V1000 XC2V6000

  • Lattice Vantis LatticeISP ispDesignEXPERT ispEXPERT SystemispEXPERT ispEXPERT SystemVHDL VerilogABEL Lattice

  • 1. ispLSI ispLSIEEPROMPLD LatticeispLSI ispLSI1000/E ispLSI2000/E/V/VE ispLSI3000 ispLSI5000V ispLSI6000ispLSI8000 MACHVantisMACH4 MACH4A MACH5 MACH5A

  • ispLSI1 00025 000 3.5 ns 180 MHz DSP ISP ISP ISP

  • LatticeispLSIPLD FPGA

  • ispLSI ISPISP ISP PLD LatticeispEXPERT

  • JED

  • ispLSI 1 JEDSDI 2 E2CMOS 3 SDO

  • 2. ispPAC In System Programmability Programmable Analog CircuitsispLSI

  • (1) (2) (3)

  • (1) (2) 100% (3) ispPAC ispPACPAC Designer

  • 3. ispGAL/PAL LatticePLD(GAL PAL) PLD PLD22V10 22LV10 CPU

  • ispGDS GDSGeneric Digtal Switch ispGDS I/O GDS ispGDS ispGDS ispGDS14 ispGDS18 ispGDS22 5 V 7.5 ns I/O12 1822

  • ispGDX GDXGeneric Digtal Crosspoint ispGDS / MUX ispGDX CPU /PCB ispGDX ispGDX80 ispGDX120 ispGDX160 80 120 160 ispGDXispGDX Development System .GDX JEDEC PCBGDX

    CpldCpld