درس مدارهای منطقی دانشگاه قمhttp://lc-qom.blogfa.com/

((Multiplexerمولتی پلکسر و

(Demultiplexerِد� مولتی پلکسر )

تهیه شده توسط حسین امیرخانیمبتنی بر اسالیدهای درس مدارهای منطقی دانشگاه امیرکبیر

http://ceit.aut.ac.ir/~szamani/index_files/logic.htm

2

Multiplexer• معنی لغوی

تسهیم کردن چند خبر را روی یک خط

فرستادن• مشخصات

2n data inputs, n select inputs, 1 output

Used to connect 2n points to a single point

control signal pattern form binary index of input connected to output

2:1 mux

I 0

I 1

A

Z

I 0

A

I 1 I 2 I 3

B

Z 4:1 mux

I 0

A

I 1 I 2 I 3

B

Z 8:1

mux

C

I 4 I 5 I 6

I 7

A 0 1

Z I 0 I 1

3

Multiplexer

…

…

4

Boolean FunctionsZ = A' I0 + A I1

Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7

2:1 mux

I 0

I 1

A

Z

I 0

A

I 1 I 2 I 3

B

Z 4:1 mux

I 0

A

I 1 I 2 I 3

B

Z 8:1

mux

C

I 4 I 5 I 6

I 7 In general, Z = S mk Ik

in minterm shorthand form

2n -1

k=0

A I0 A

I0

I1 00 01 11 10

0

1

0

0

1

1

0

1

0

1

5

Circuit Diagram

• 4-to-1 MUXA

B

I0

I1

I2

I3

A B Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

6

Cascading MUXes (ترکیب مولتی پلکسرها)

Design a MUX (8:1) by smaller MUXes

Z

A C B

I 0 I 1 I 2 I 3

I 4 I 5 I 6 I 7

4:1 mux

0 1 2 3 S 1 S 0

4:1 mux

0 1 2 3 S 1 S 0

2:1 mux

S

0

1

پرارزش

7

Another Implementation

0

1 S

0

1 S

0

1 S

0

1 S

0

1

S1

2

3 S0

C

A B

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

C

C

C

Z

پرارزش

8

Larger Data Lines

What if we want to select m-bit data/words?− Combine MUX blocks in parallel with

common select and enable signals

9

4-bit data

• Example: Selection between

2 sets of 4-bit inputs

2:1 mux

I 0

I 1

A

Z

2:1 mux

I 0

I 1

A

Z

2:1 mux

I 0

I 1

A

Z

2:1 mux

I 0

I 1

Z

x0

x1

x2

x3

y0

y1

y2

y3

z0

z1

z2

z3

A

?

10

Application

Multiple input sources:

A+C orA+D orB+C orB+D

MUX MUX

X Y

Sum

A B C D

Sa Sb

design Mux by decoder

11

12

MUX by 3-State Buffers

Three-state logic in place of AND-OR

Output of gates can be connected

I0

I1

I2

I3

S1

S0

(b)

Y

13

General Logic by MUX

• Example:F = A' B' C' + A' B C' + A B C' + A B C

= A' B' (C') + A' B (C') + A B' (0) + A B (1)

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

C’

C’

0

1

1 0 1 0 0 0 1 1

8:1 MUX

0 1 2 3 4 5 6 7 S2 S1 S0

A B C

F

A 0 0 1 1

B 0 1 0 1

F C’ C’ 0 1

S1 S0

A B

4:1 MUX

0 1 2 3

C

C01

F

14

General Logic by MUX

Any Boolean function of n variables can be implemented using a 2n-to-1 multiplexer.

Any Boolean function of n variables can be implemented using a 2n-1-to-1 multiplexer with only not gates.

15

Using Smaller MUX

How about implementing a 4-variable function by a 4-to-1 MUX− Anything else is needed?

16

General Logic

• By decoder: Multiple outputs:

− A single decoder,− One more OR for each output

• By MUX: Multiple outputs:

− One more MUX for each output,− No need for OR

• Use MUX for few outputs,• Use decoder for many outputs.

مثال81سال

82سال

مثال

83سال •

80سال •

18

مثال

84سال •

19

20

Standard MSI MUXes

• 74x151 8:1 MUX

21

Standard MSI MUXes

• 74x157 2:1 4-bit MUX

Demultiplexer

DEMUX

23

DEMUX

24

Decoder vs. Demux

ABC ABC ABC ABC ABC ABC

ABC ABC

3:8 dec

O0 O1

O2

A

B

C

Enb

S2

S1

S0

O3

O4

O5

O6

O7

E A B C O0 O1 O2 O3 O4 O5 O6 O7

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0

1 0 1 0 0 0 1 0 0 0 0 0

1 0 1 1 0 0 0 1 0 0 0 0

1 1 0 0 0 0 0 0 1 0 0 0

1 1 0 1 0 0 0 0 0 1 0 0

1 1 1 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 0 0 0 0 0 1

25

Decoder vs. Demux

3:8 dec

0 1

2 3 4 5 6 7

A B C

Enb

ABC ABC ABC ABC ABC ABC

ABC ABC S 2 S 1 S 0

ABC ABC ABC ABC ABC ABC

ABC ABC

3:8 dec

O0 O1

O2

A

B

C

Enb

S2

S1

S0

O3

O4

O5

O6

O7

سؤاالت آزمون کارشناسی ارشد

26

سال سؤال

1379 11

1381 63

1383 65

1384 62

1386 66

1389 67

1390 67

1391 62