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بنام خدا
ريز پردازنده ها
Microprocessors
Reference Booksمنابع:
Title: The Z80 Microprocessor , Hardware , Software , programming & interfacing
Author: Barry B. Brey Translator: Hossein Nia
Publisher: Astane Ghodse Razavi ( Beh Nashr )
Reference Books منابع:
Z80 Family DATABOOK
Publisher: ZILOG Corp. Copyright 2004
Introductionمقدمه: Microprocessor / (uP) / (MPU)
A uP is a CPU on a single chip. Components of CPU
• ALU, instruction decoder, registers, bus control circuit, etc.
Micro-computer (u-Computer) small computer uP + peripheral I/O + memory specifically for
data acquisition and control applications
Microcontroller (uC) u-Computer on a single chip of silicon
uP vs. uC ريزپردازنده و :ريزكنترلر
A uP Only is a single-chip CPU Bus is available RAM capacity ROM is smaller than RAM (usually) number of I/O ports is selectable
A uC Contains a CPU and RAM,ROM ,Peripherals, I/O ports in a
single IC Internal hardware is fixed Communicate by port ROM is larger than RAM (usually) Small power consumption Single chip, small board Implementation is easy Low cost
uP vs. uC – cont. ريزپردازنده:و ريزكنترلر
Applications:
uCs are suitable to control of I/O devices in designs requiring a minimum component
uPs are suitable to processing information in computer systems
uP vs. uC – cont. ريزپردازنده و :ريزكنترلر uC is easy to use and design.
Only single chip can be a complete system
interfacing to other devices, • for example, motors, displays,
sensors, and communicate with PC. In contrast, similar system that builds from uP would require a lot of additional units,
such as RAM, UART, I/O , TIMER and etc.
uC is a Reusable Hardware ريزكنترلر قابل برنامه ريزي :مجدد است Logic circuit provides limited function for
one single design. In order to change
circuit’s functionality, we need to redesign the
circuits.
uC can reprogram and change functionality of every port, input to output or digital to analog on the fly.
uCs Many uCs are existing right now.
8051, 68HC11, MSP430, ARM series, and etc.
We may widely divide it with how it is designed
RISC/CISC architecture. What is the main difference between RISC/CISC? Does it make any difference to our
application?
The Microprocessor (MPU) The uP is the ‘ brain of the microcomputer ’ Is a single chip which is capable of
processing data controlling all of the components
which make up the microcomputer system
µP used to sequence executions of instructions that is in memory
uP Fetch , Decode , and Execute the instruction
The internal architecture of the microprocessor is complex.
The Microprocessor (MPU)
microprocessor (MPU) typically contains
Registers: Temporary storage locations for
program instruction or data.
The Arithmetic Logic unit (ALU): This part of
the MPU performs both arithmetic and logical
operations
Timing and Control Circuits: that keep all of the
other parts of system (Regs, ALU, memory &
I/O) working together in the right time
sequence
Microcomputers :ريزكامپيوترها All Microcomputers consist of (at least) :
1. Microprocessor Unit (MPU) 2. Program Memory (ROM) 3. Data Memory (RAM) 4. Input / Output ports 5. Bus System (and Software)
MPU is the brain of microcomputer
Parts of a Computer
CPU
control
ALU
Memory I/O
Instruct.
data
data
bus
System Architecture
CPU Memory
Bus
I/O ports
I/O devices
Microcomputers :ريزكامپيوترها
The Input/Output (I/O) System :ورودي/خروجي I/O is the link between the MPU and the
outside world.
An input port is a circuit through which an external device can send signals (data?) to the MPU.
An output port is a circuit that allows the MPU to send signals (data?) to external devices.
I/O ports connect both digital and analogue devices by DAC and ADC
Bus گذرگاهها (مسيرهاي :عمومي) A Bus is a common communications pathway used
to carry information between the various elements of a computer system
The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another
The individual subsystems of the digital computer are connected through an interconnecting BUS system
Bus گذرگاهها (مسيرهاي :عمومي)
There are three main bus groups ADDRESS BUS DATA BUS CONTROL BUS
Data Bus گذرگاه داده:
The Data Bus carries the data which is transferred throughout the system. ( bi-directional)
Examples of data transfers Program instructions being read from memory
into MPU. Data being sent from MPU to I/O port Data being read from I/O port going to MPU Results from MPU sent to Memory
These are called read and write operations
Address Bus گذرگاه :آدرس An address is a binary number that
identifies a specific memory storage location or I/O port involved in a data transfer
The Address Bus is used to transmit the address of the location to the memory or the I/O port.
The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.
Control Bus گذرگاه :كنترل The Control Bus: is another group of signals
whose functions are to provide synchronization ( timing control ) between the MPU and the other system components.
Control signals are unidirectional, and are mainly outputs from the MPU.
Example Control signals RD: read signal asserted to read data into MPU WR: write signal asserted to write data from
MPU
Main memory حافظه :اصلي The duties of the memory are :
To store programs To provide data to the MPU on request To accept result from the MPU for storage
Main memory Types ROM : read only memory. Contains program
(Firmware). does not lose its contents when power is removed (Non-volatile)
RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values
Read-Only Memory حافظه فقط :خواندني
uP can read instructions from ROM quickly
Cannot write new data to the ROM ROM remembers the data, even
after power cycled Typically, when the power is turned
on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap )
Available ROMs : ROM انواع Masked ROM or just ROM PROM or programmable ROM (once only) EPROM (erasable via ultraviolet light) Flash (can be erased and re-written about
10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading)
EEPROM (electrically erasable read-only memory, also known as EEROM—both reading and writing are very slow but can program millions of times…useless for storing a program but good for say configuration information.
.
.
ROMA0
A1
A2
Am
D0
Dn
D1
D2
OECE
n+1 bitData
12 mCapacity :
m+1 bitAddress
OE : Output Enable connect to RD of uP
)(CSCE : Chip Enableto Address decoder
)1(2 1 nm
ROMPROM
EEPROM
.Timing Diagram for a Typical ROM
CE
A0-Am
D0-Dn
OE falls to data valid
Addr. valid to data valid
OE
.
27XX EPROM
U1
2716
87654321
232219
1820
21
910111314151617
A0A1A2A3A4A5A6A7A8A9A10
CEOE
VPP
O0O1O2O3O4O5O6O7
16 kbit2 kbyte
U2
2732
87654321
23221921
1820
910111314151617
A0A1A2A3A4A5A6A7A8A9A10A11
CEOE/VPP
O0O1O2O3O4O5O6O7
32 kbit4 kbyte
U3
2764
109876543
25242123
2
1112131516171819
2227
1
20
A0A1A2A3A4A5A6A7A8A9A10A11A12
O0O1O2O3O4O5O6O7
OEPGM
VPP
CE
64 kbit8 kbyte
PGM and VPP are used to programming
27XXX EPROMU4
27128
109876543
25242123
226
1
1112131516171819
20
2227
A0A1A2A3A4A5A6A7A8A9A10A11A12A13
VPP
D0D1D2D3D4D5D6D7
CE
OEPGM
U5
27256
109876543
25242123
22627
2022
1
1112131516171819
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14
CEOE
VPP
D0D1D2D3D4D5D6D7
U6
27512
109876543
25242123
226
2022
27
28
1
1112131516171819
A0A1A2A3A4A5A6A7A8A9A10A11A12A13
CEOE/VPP
A14
VCC
A15
O0O1O2O3O4O5O6O7
U7
27010
121110
98765
27262325
42829
32
1314151718192021
2431
1
22
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16
D0D1D2D3D4D5D6D7
OEPGM
VPP
CE
128 kbit16 kbyte
256 kbit32 kbyte
512 kbit64 kbyte
1024 kbit128 kbyte
28256
109876543
25242123
226
1
1112131516171819
28
20
2227
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14
D0D1D2D3D4D5D6D7
VCC
CE
OEWE
256 kbit32 kbyte
2864
20
22
28
109876543
252421
27
1112131516171819
232
1
CE
OE
VCC
A0A1A2A3A4A5A6A7A8A9A10
WE
I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
A11A12
RDY/BUSY
64 kbit8 kbyte
28010
121110
98765
27262325
42829
32
1314151718192021
32
22
2431
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16
D0D1D2D3D4D5D6D7
VCC
CE
OEWE
1026 kbit128 kbyte
28040
121110
98765
27262325
42829
32
1314151718192021
32
301
22
2431
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16
D0D1D2D3D4D5D6D7
VCC
A17A18
CE
OEWE
4096 kbit512 kbyte
2816
18
20
24
87654321
232219
21
910111314151617
CE
OE
VCC
A0A1A2A3A4A5A6A7A8A9A10
WE
I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
16 kbit2 kbyte
28XX E2PROM
RAM (Random Access Memory) :حافظه خواندني/نوشتني
The uP can read the data from RAM quickly, The uP can write new data quickly to RAM RAM forgets its data if power is turned off Two type of is available :
Static RAM(SRAM): ff base, fast, expensive, low cap / vol, applied for cache , no refresh.
Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.
RAM(Static) A0
A1
A2
Am
D0
Dn
D1
D2
RDWR
n+1 bitData
12 mCapacity :
m+1 bitAddress
CS: Chip Select to Address decoder
)1(2 1 nm
RAM
CS
RD: Read signal connect to MemRD of uP
WR: Write signal connect to MemWR of uP
Data bus isBidirectional
Session 2
Microprocessors History Data width 8086 vs 8088 8086 pin description Z80 Pin description
Microprocessors Microprocessors come in all kinds of varieties
from the very simple to the very complex Depend on data bus and register and ALU width
uP could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit We will discuss two sample of it
Z80 as an 8-bit uP and 8086/88 as an 16-bit uP
All uPs have the address bus the data bus RD, WR, CLK , RST, INT, . . .
Historyتاريخچه:
Company
4 bit 8 bit 16 bit 32 bit 64 bit
Intel40044040
800880808085
8088/68018680286
8038680486
80860Pentium
Zilog Z80Z8000Z8001Z8002
Motorola680068026809
680066800868010
680206803068040
Internal and External Bus
Internal bus is a pathway for data transfer between registers and ALU in the uPs
External bus is available externally to connect to RAM, ROM and I/O
Int. and Ext. Bus width may be different For example
In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit
In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit
8086 vs 8088
U?
8086MIN
MN33
READY22
CLK19
RESET21
INTR18
HLDA30
HOLD31
NMI17
TEST23
AD016
AD115
AD214
AD313
AD412
AD511
AD610
AD79
AD88
AD97
AD106
AD115
AD124
AD133
AD142
AD1539
A16/S338
A17/S437
A18/S536
A19/S635
BHE/S734
DEN26
DT/R27
M/IO28
RD32
WR29
ALE25
INTA24
U?
8088MIN
MN33
READY22
CLK19
RESET21
INTR18
HLDA30
HOLD31
NMI17
TEST23
AD016
AD115
AD214
AD313
AD412
AD511
AD610
AD79
A88
A97
A106
A115
A124
A133
A142
A1539
A16/S338
A17/S437
A18/S536
A19/S635
SSO34
DEN26
DT/R27
IO/M28
RD32
WR29
ALE25
INTA24
16_bit Data Bus
20_bit Address
8_bit Data Bus
20_bit Address
80888086
Only external bus of 8088 is 8-bit
8086 Pin Assignment نام :پايه ها
8086 Pin Description تشريح Vcc (pin 40) : Power :پايه ها
Gnd (pin 1 and 20) : Ground
AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode
READY (input , Active High) : take uP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately
terminate its present activity.
TEST’ (input , Active Low) : Connect this to HIGH
HOLD (input , Active High) : Connect this to LOW
HLDA (output , Active High) : Hold Ack
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non- maskable interrupt
8086 Pin DescriptionDEN’ (output) : Data Enable. It is LOW when processor
wants to receive data or processor is giving out data
(to74245)
DT/R’ (output) : Data Transmit/Receive. When High, data from uP to memory
When Low, data is from memory to uP (to74245 dir)
IO/M’ (output) : If High uP access I/O Device. If Low uP access memory
RD’ (output) : When Low, uP is performing a read operation
WR’ (output) : When Low, uP is performing a write operation
ALE (output) : Address Latch Enable , Active High Provided by uP to latch address When HIGH, uP is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines
Z80 CPU Pin Assignment :Z80 پايه هاي
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
14
15
12
8
7
9
10
13
27
19
20
21
22
28
18
23
6
24
16
17
26
25
11
29
M1 -
MREQ -IORQ -
RD -WR -
RFSH -
HALT -
WAIT -
INT -NMI -
RESET -
BUSRQ -BUSAK -
+ 5VGND
Z - 80 CPU
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15
D0D1D2D3D4D5D6D7
Address Bus
Data Bus
SystemControl Lines
CPUControl Lines
BusControl Lines
Z80 Pin Description A15-A0 : Address bus (output, active high, 3-state). Used for accessing the memory and I/O portsDuring the refresh cycle the I is put on this bus.
D7-D0 : Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts.
RD:Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O
WR:Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.
Z80 Pin Description
MREQMemory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1
IORQInput/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1
M1Machine Cycle One (output, active Low).Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle
RFSHRefresh (output, active Low).Together with MREQ indicates refresh cycle.Lower 7-bits address is refresh address to DRAM
Z80 Pin DescriptionINT
Interrupt Request (input, active Low).Interrupt Request is generated by I/O devices. Checked at the end of the current instruction If flip-flop (IFF) is enabled.
NMINon- Maskable Interrupt(Input, negative edge-triggered). Higher priority than INT. Recognized at the end of the current InstructionIndependent of the status of IFFForces the CPU to restart at location 0066H.
Z80 Pin DescriptionBUSREQ
Bus Request (input, active Low).higher priority than NMI recognized at the end of the current machine cycle.forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp.
BUSACKBus Acknowledge (output, active,Low)indicates to the requesting device that address, data, and control signalsMREQ, IORQ, RD, and WR have entered their high-impedance states.
Z80 Pin Description
RESETReset (input, active Low). RESET initializes the CPU as follows:Resets the IFFClears the PC and registers I and RSets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactivestate. must be active for a minimum of three full clock cycles before the reset operation is complete.
Z80 Z80 بلوك دياگرامCPU
CONTROLSECTION
± k
CONTROL BUS
SEQUENCER
CONTROLLER
INTERNAL ADDRESS BUS (16 BIT)
INTERNAL DATA BUS (8 BIT)
16
INTERNAL CONTROL BUS
DECODER
REGISTER
INSTRUCTIONRI
± k
ALU
TMPA
A'
F
F'
ACT
ADDRESS BUSBUFFER
DATA BUS
BUFFER
BUFFER
13
8
IX
IY
SP
PC
W' Z'
B' C'
D'
H' L'
E'
B
W
D
H
Z
C
E
L
MUXMUX
Z80 Programming Model
Register Set مجموعه ثبات ها: A : Accumulator Register
F : Flag register Two sets of six general-purpose registers
may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ D’ E’ H’ L’)
or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’)
The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via: EXX (BC)<->(BC') , (DE)<-
>(DE') , (HL)<->(HL') EX AF, AF ’ (AF)<->(AF') what is this instruction useful for?
Register Set(cont) 4 16-bit registers hold memory address (pointers)
index registers (IX) and (IY) are 16-bit memory pointers
16 bit stack pointer (SP) Program counter (PC)
Program counter (PC) PC points to the next opcode to be fetched
from ROM when the µP places an address on the address
bus to fetch the byte from memory, it then increments the program counter by one to the next location
Special purpose registers I : Interrupt vector register. R : memory Refresh register
Flag Register ثبات پرچم :ها
S Sign Flag (1:negativ)*Z Zero Flag (1:Zero)H Half Carry Flag (1: Carry from Bit 3 to Bit 4)**P Parity Flag (1: Even)V Overflow Flag (1:Overflow)*N Operation Flag (1:previous Operation wassubtraction)**C Carry Flag (1: Carry from Bit n-1 to Bit n,
with n length of operand)
*: 2-complement number representation**:used in DAA-operation for BCD-arithmetic
7 6 5 4 3 2 1 0
XS Z H X P N CV
DAA - Decimal Adjust Accumulator
before DAA after DAA
Op N C Bits 4-7 H Bits 0-3 A=A+.. C
ADDADC
0 0 0-9 0 0-9 00 0
0 0 0-8 0 A-F 06 00 0 0-9 1 0-3 06 0
0 0 A-F 0 0-9 60 1
0 0 9-F 0 A-F 66 1
0 0 A-F 1 0-3 66 1
0 1 0-2 0 0-9 60 1
0 1 0-2 0 A-F 66 1
0 1 0-3 1 0-3 66 1
SUBSBCNEG
1 0 0-9 0 0-9 00 01 0 0-8 1 6-F FA 0
1 1 7-F 0 0-9 A0 1
1 1 6-F 1 6-F 9A 1
Adjusts the content of the Accumulator A for BCD addition and subtractionoperations such as ADD, ADC, SUB, SBC, and NEG according to the table:
Instruction cycles, machine cyclesand “T-states”
Instruction cycle is the time taken to complete the execution of an instruction
Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc.
T-state = 1/f (f:Z80 Clock Frequency) f= 4MHZ T-state=0.25 uS
Basic CPU Timing Example
Opcode Fetch Bus Timings (M1 Cycle)
The R register
Is increased at every first machine cycle (M1).
Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same
Bit 7 can be changed using the LD R,A instruction.
LD A,R and LD R,A access the R register after it is increased
R is often used in programs for a random value, which is good but of course not truly random.
the block instructions decrease the PC with two, so the instructions are re-executed.
Memory read/write cycle
Adding One Wait State to an M1 Cycle
Adding One Wait State to Any Memory Cycle
IO read/write cycle
During I/O operations a single wait state is automatically inserted
Bus Request/Acknowledge Cycle
Interrupt Request/Acknowledge Cycle
Two wait states are automatically added to this cycle
Non - Maskable Interrupt Request Operation
M1 Refresh Cycle
Takes 4T to 6Ts Z80 includes built in circuitry for refreshing
DRAM This simplifies the external interfacing
hardware DRAM consists of MOS transistors, which
store Information as capacitive charges; each cell needs to be periodically refreshed
During T3 and T4 (when Z80 is performing internal ops), the low order address is used to supply a 7-bit address for refresh
Wait Signal
the Z80 samples the wait signal during T2 if low then Z80 adds wait
states to extend the machine cycle
used to interface memories with slow response time
Slow memory is low cost
There are two types of interrupts: non mask-able (NMI)
Could not be masked Jump to 0066H of memory
mask-able(INT) Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2
وقفه ها: Interrupts
Interrupt Modes حالت هاي :وقفه Mode 0:
An 8 bit opcode is Fetched from Data BUS and executed
The source interrupt device must put 8 bit opcode at data bus
8 bit opcode usually is RST p instructions Mode 1:
A jump is made to address 0038h No value is required at data bus
Mode 2: A jump is made to address (register I × 256 +
value from interrupting device that puts at bus) I is high 8 bit of interrupt vector Value is low 8 bit of interrupt vector
Z80 CPU Instruction Description
158 different instruction types Including all 78 of the 8080A CPU. Instruction groups
Load and Exchange Block Transfer and Search Arithmetic and Logical Rotate and Shift Bit Manipulation (Set, Reset, Test) Jump, Call, and Return Input/Output Basic CPU Control
Addressing Modes
Immediate Immediate Extended Modified Page Zero Addressing (rst p) Relative Addressing
Jump Relative (2 byte) • One Byte Op Code• 8-Bit Two’s Complement Displacement (A+2)
Extended Addressing Absolute jump
• One byte opcode• 2 byte address
Indexed Addressing (Index Register + Displacement) (IX+d) 2 byte opcode 1 byte displacement
Addressing Modes (cont.)
Register Addressing LD C,B
Implied Addressing Op Code implies other operand(s) ADD E
Register Indirect Addressing 16-bit CPU register pair as pointer (such as HL) ADD (HL)
Bit Addressing set, reset, and test instructions. SET 3,A RES 7,B
Minimal Configuration of a Z80 Microcomputer
MemoryClock Power
InputZ - 80 CPU
Supply
Output(I/O)
(ROM, RAM)Generator
Address Bus
Data Bus
Control Bus
Out
In
Z80 Memory Connection
CPU 16 bit address bus 64 k memory (max) CPU 8 bit data bus 8 bit data width Generally should be connected
Data to Data Address to Address WR to WR RD to RD MREQ to CS
Memory connection (cont.)
WR
RD
RD WR
RAM64 kb
CSZ80 CPU
D7~D0D7~D0
A15~A0A15~A0
MREQ
If only one RAM chip Full size (64 kb capacity)
Memory connection (cont.)
WR
RD
RD WR
RAM32 kb
CSZ80 CPU
D7~D0D7~D0
A14~A0A14~A0
MREQA15
If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFh
Memory connection (cont.)
There is two 32 kb RAM Problem: Bus Conflict. The two
memory chips will provide data at the same time when microprocessor performs a memory read.
Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
Memory connection (cont.)
WR
RD
RD WR
RAM32 kb
CSZ80 CPU
D7~D0D7~D0
A14~A0A14~A0
MREQ
RAM32 kb
D7~D0
A14~A0
RD WR CS
A15
There is two 32 kb RAM A15 applied to select one RAM chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1)
Memory connection (cont.)
WR
RD
OE
ROM32 kb
CSZ80 CPU
D7~D0D7~D0
A14~A0A14~A0
MREQ
RAM32 kb
D7~D0
A14~A0
RD WR CS
A15
32 kb ROM and 32 kb RAM ROM doesn’t have wr signal
Memory connection (cont.)
Z80 CPU
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
RAM16 kb
D7~D0
A13~A0
RD WR CS
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0S1
There is 4 memory chipA14 and A15 applied to chip selection
Address Bit Map
A15 to A0
(HEX)
AA AA
11 11
54 32
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000h
3FFFh
00 00
00 11
0000
1111
0000
1111
0000
1111ROM
4000h
7FFFh
01 00
01 11
0000
1111
0000
1111
0000
1111RAM
1
8000h
BFFFh
10 00
10 11
0000
1111
0000
1111
0000
1111RAM2
C000h
FFFFh
11 00
11 11
0000
1111
0000
1111
0000
1111RAM3
Selects chipSelects location within chips
Memory Map Represents the memory type
Address area of each memory chip
Empty area
0000h
3FFFh
ROM16k
4000h
7FFFh
RAM1
16k
8000h
BFFFh
RAM2
16k
C000h
FFFFh
RAM3
16k
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
RAM16 kb
D7~D0
A13~A0
RD WR CS
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0
S1
Memory Map Empty Area cann’t write and read
Read op. returns FFh value ( usualy )
Write op. cann’t store any value on it
0000h
3FFFh
ROM
4000h
7FFFh
Empty
8000h
BFFFh
RAM2
C000h
FFFFh
RAM3
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0
S1
Memory Map Empty Area cann’t write and read
Read op. returns FFh value (usualy)
Write op. cann’t store any value on it
0000h
3FFFh
ROM
4000h
7FFFh
Empty
8000h
BFFFh
RAM
C000h
FFFFh
Empty
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0
S1
Full and Partial Decoding Full (exhaust) Decoding
All of the address lines are connected to any memory/device to perform selection
Absolute address : any memory location has one address
Partial Decoding When some of the address lines are
connected the memory/device to perform selection
Using this type of decoding results into roll-over addresses (fold back or shading).
roll-over address : any memory location has more than one address
Partial Decoding A15~A12 has no connection Then doesn’t play any role in addressing What is the Memory and Address Bit
map?
WR
RD
RD WR
RAM4 kb
CS
Z80 CPU
D7~D0D7~D0
A11~A0A11~A0
MREQ
XA15~A12
Partial Decoding
A15 to A0
(HEX)
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
X000h
XFFFh
xxxx
xxxx
0000
1111
0000
1111
0000
1111RAM WR
RD
RD WR
RAM4 kb
CS
Z80 CPU
D7~D0D7~D0
A11~A0A11~A0
MREQ
XA15~A12
0000h
0FFFhRAM
1000h
1FFFhRAM’
2000h
2FFFhRAM’
3000h
3FFFhRAM’
F000h
FFFFhRAM’
Every memory location has more than one address For example first RAM location has addresses:
0000h1000h2000h3000h ……………. …………….
F000h
Roll-over Address
Partial Decoding A12 only connected to RAM A13 has no connection What is the memory map?
WR
RD
OE
ROM4 kb
CS
Z80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
Partial Decoding
8 roll-over address for ROM 4 roll-over address for RAM
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0xxx
0xxx
0000
1111
0000
1111
0000
1111ROM
X0x0
X0x1
0000
1111
0000
1111
0000
1111RAM
WR
RD
OE
ROM4 kb
CSZ80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
Partial Decoding
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0xxx
0xxx
0000
1111
0000
1111
0000
1111
4k
ROM
X0x0
X0x1
0000
1111
0000
1111
0000
1111
8k
RAM
0000h
1FFFh
RAM’
0000h
0FFFhROM
1000h
1FFFhROM’
2000h
3FFFh
RAM’
2000h
2FFFhROM’
3000h
3FFFhROM’
4000h
5FFFh
4000h
4FFFhROM’
5000h
5FFFhROM’
6000h
7FFFh
6000h
6FFFhROM’
7000h
7FFFhROM’
8000h
9FFFh
RAM
F000h
FFFFh
A000h
BFFFh
RAM’
C000h
DFFFh
E000h
FFFFh
WR
RD
OE
ROM4 kb
CSZ80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
Conflict
Partial Decoding
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0xxx
0xxx
0000
1111
0000
1111
0000
1111
4k
ROM
X1x0
X1x1
0000
1111
0000
1111
0000
1111
8k
RAM
0000h
1FFFh
0000h
0FFFhROM
1000h
1FFFhROM’
2000h
3FFFh
2000h
2FFFhROM’
3000h
3FFFhROM’
4000h
5FFFh
RAM’
4000h
4FFFhROM’
5000h
5FFFhROM’
6000h
7FFFh
RAM’
6000h
6FFFhROM’
7000h
7FFFhROM’
8000h
9FFFh
F000h
FFFFh
A000h
BFFFh
C000h
DFFFh
RAM
E000h
FFFFh
RAM’
WR
RD
OE
ROM4 kb
CSZ80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
Conflict
Full (exhaustive) decoding
MREQ
WR
RD
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
RD
6116RWM2k8
CS
D7~D0A10~A0
WR
D7~D0
A12~A0
A10~A0
A13
A12
A11
A15
A14
RD
7421
0000h-07FFh
0800h-0FFFh
1000h-17FFh
1800h-1FFFh
2000h-27FFh
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000
0001
0000
1111
0000
1111
0000
1111ROM
0010
0010
0000
0111
0000
1111
0000
1111RAM
Partial decoding
MREQ
WR
RD
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
RD
6116RWM2k8
CS
D7~D0A10~A0
WR
D7~D0
A12~A0
A10~A0
A15
A14
A13
RD
0000h-1FFFh
2000h-3FFFh
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000
0001
0000
1111
0000
1111
0000
1111ROM
001x
001x
x000
x111
0000
1111
0000
1111RAM
GND
VCC
1 Bit Memory With Separated I/O
RDWR /
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
D0D1D7
D7-D0
A11-A0A11-A0A11-A0
CS
What is the memory (addr. bit) map
WR
RD
D0
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
D1D7D7-D0
A11-A0A11-A0A11-A0
RD
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
0000h-1FFFh
2000h-3FFFh
MREQ
A15
A14
A13
GND
VCC
WR
Adding RAM & ROM
Minimum Z80 Computer System
Z80-µP-Family (Typical Environment)
+5V
Z80 CPU+5V IEI IEI
IEI
IEOINT -
IEO
INT -
INT - RDY
W/RDYB -INT -
INT -
RxCA -TxCA -
RxCB -TxCB -
ZC/TO2ZC/TO1
CTC SIO
PIO DMA
System Buses (Address, Data, Control)
Z80 Input Output
Z80 at most could have 256 input port and 256 output 8 bit port address is placed on A7–A0 pin to select the I/O device OUT (n), A
n is 8 bit port address Content of A is data
OUT (C), r Content of C is a port address r is a data register
IN A, (n) n is 8 bit port address Data is transferred to A
IN r (C) Content of Reg C is a port address Input data is transferred to r (data reg)
Remember IO read/write cycle
Z80 and simple output port
Z80CPU
A14
A0:
D7D6
WR
IORQ
A15
D5D4D3D2D1D0
A7A6A5A4A3A2A1A0IOWR
74LS373
Q0Q1Q2Q3Q4Q5Q6Q7
D0D1D2D3D4D5D6D7
OELE
OUT (03), A
Z80 and simple input port
Z80CPU
A14
A0:
D7D6
RD
IORQ
A15
D5D4D3D2D1D0
A7A6A5A4A3A2A1A0IORD
74LS244
A0A1A2A3A4A5A6A7
Y0Y1Y2Y3Y4Y5Y6Y7
G1 G2
5V
IN A, (02)
8088 and simple output port
A15
8088Minimum
Mode
A18
A0:
D7D6
IORIOW
A19
D5D4D3D2D1D0
A14
A13
A12
A11
A10
A9A8A7A6A5A4A3A2A1A0IOW
74LS373
Q0Q1Q2Q3Q4Q5Q6Q7
D0D1D2D3D4D5D6D7
OELE
8088 and simple input port
A15
8088Minimum
Mode
A18
A0:
D7D6
IORIOW
A19
D5D4D3D2D1D0
A14
A13
A12
A11
A10
A9A8A7A6A5A4A3A2A1A0IOW
What is this?
74LS244
A0A1A2A3A4A5A6A7
Y0Y1Y2Y3Y4Y5Y6Y7
G1 G2
5V
Simplified Drawing of 8088 Minimum Mode
D7 - D0 Q7 - Q0
OELE 74LS373
D7 - D0 Q7 - Q0
OELE 74LS3738088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DENDT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OELE 74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
A7 - A0 B7 - B0
EDIR 74LS245
MEMR
MEMW
IOR
IOW
A7-A0
A15-A8
A19-A16
D7-D0
Minimum Mode
220 bytes or 1MB memory
1 MBMemory
D7 - D0
A19 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A19 - A0
MEMR
MEMW
CS
What are the memory locations of a 1MB (220 bytes) Memory?A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Example: 34FD0 0011 0100 11111 1101 0000
Minimum Mode
512 kB memory
512 kBMemory
D7 - D0
A18 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A18 - A0
MEMR
MEMW
CS
A19What do we do with A19?
1) Don’t connect it2) Connect to cs
What is the difference?
512 kB Memory Map Don’t connect it
A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it.
A19=0 is the same as A19=1 for Memory
Connect to cs If A19=0 Memory
chip act normal function
00000h
7FFFFh
512k
Mem
80000h
FFFFFh
512k
Mem’
00000h
7FFFFh
512k
Mem
80000h
FFFFFh Empty
2 512 kB memory
512 kBRAM1
D7 - D0
A18 - A0
RDWR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A18 - A0
MEMR
MEMW
CS
A19
MEMR
MEMW
512 kBRAM2
D7 - D0
A18 - A0
RDWR
MEMR
MEMW
CS
2 512 kB memory
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000
0111
0000
1111
0000
1111
0000
1111
0000
1111 ROM
1000
1111
0000
1111
0000
1111
0000
1111
0000
1111 RAM
00000h
7FFFFh
512k
RAM1
80000h
FFFFFh
512k
RAM2
What are the memory locations of two consecutive 512KB (219 bytes) Memory?
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
Memory chip#__ is mapped to:
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210 Memory
Chip
RAM#1
RAM#2
RAM#3
RAM#4
Interfacing several 8K Memory Chips to the 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#?
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Memory chip#__ is mapped to:
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210 Memory
Chip
RAM#1
RAM#2
RAM#126
RAM#127
RAM#128
What is the Memory and Address Bit map?
MREQ
WR
RD
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
RD
6116RWM2k8
CS
D7~D0A10~A0
WR
D7~D0
A12~A0
A10~A0
A14
A13
A12
A15
RD
7408
VCC
74244
21GGINPUT
