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Smart Trip Logic for Smart Grids to Block DistanceRelay Maloperation - Implementation and ValidationVenkatesh C, Student Member, IEEE

Department of Electrical EngineeringIndian Institute of Technology Madras

Chennai - 600036Email: ee10d036@ee.iitm.ac.in

K Shanti Swarup, Senior Member, IEEEDepartment of Electrical EngineeringIndian Institute of Technology Madras

Chennai - 600036Email:ksswarup@iitm.ac.in

Vishnu Prasath S

Email:vishnuprasaths@yahoo.com

Abstract Zone 1 reach setting of a distance relay depend uponmany factors, such as, dc offset in current signals, loading effect,fault resistance in the presence of in-feed from remote end andalso capacitive voltage transformer (CVT) transients. All thesefactors are taken care of except for CVT transients, which isdealt either by reducing zone 1 reach or by providing a xed timedelay in todays intelligent electronic devices (IED). This paperproposes a new and simple logic to prevent numerical distancerelay mal-operation by zone 1 element due to CVT transientswithout sacricing zone 1 reach. This is achieved by providingadaptive time delay by actually monitoring the CVT transientsin time domain. The proposed logic is validated in real time byincorporating the proposed logic along with positive sequencepolarized distance relay model in eld programmable gate array(FPGA).

I. INTRODUCTION

Today, power grids are undergoing some major changes inthe quest to transform themselves into smarter power grids. In-order to meet these needs, IEDs are equipped with differentfunctionalities to make trip decision in a intelligent fashion

to prevent mal-operation which may lead to cascaded trippingand nally blackout. IED mal-operation may be due to differ-ent reasons like hidden failures, overreaching, under-reaching,power swings, load encroachment and due to the presenceof series capacitors. Distance relay may also mal-operate dueto fault resistance in the presence of remote end in-feed [1],[2]. In addition to this, zone 1 element may overreach due toCVT transients [3], [4], [5] especially during high source toline reach impedance ratio (SIR) [6], [7]. This is due to thepresence of energy storage elements (inductor and capacitorin active type CVT or saturable inductor and resistor in caseof passive type CVT) in ferro-resonance suppression circuit(FSC) which fails to replicate the primary system informationin secondary instantaneously.

It is six decades before, this problem i.e. distance relay mal-operation due to CVT transients is suspected [8]. The problemgot aggravated when electromechanical relays are replacedwith digital relays with high speed tripping features i.e. es-pecially when half-cycle algorithms are used for fundamentalfrequency voltage and current phasor estimation. Even-thoughthe problem seems to be very old, it is still important in todaysscenario, as it is one of the main governing factors to decidethe zone 1 reach setting apart from other overreaching factors.

Different solutions are proposed by relay manufacturers tohandle the overreaching by providing nite impulse responselters [9] in current path to overcome overreaching due todc offset in current waveform, adaptive tilting angle [10] toprevent overreaching due to fault resistance in the presence of remote end in-feed. The emphasis will be still more, especially

when the voltage signal to IED is fed from active type CVTwhich is prone to CVT transients due the presence of energystorage elements in FSC.

The paper is organized as follows, Section II discusses theliterature review, followed by Section III with the proposedlogic. Section IV discusses the test system modeling andsimulation results. Hardware implementation and validationresults are shown in Section V and section VI with conclusion.

I I . L ITERATURE R EVIEW

IED receives the system primary information via instrumenttransformers i.e. CVT and current transformer (CT). Faultinformation delivered by CVT and CT are corrupted by

unwanted information like dc offset [1]. These CVT and CTsignals cause distance elements to overreach i.e. mal-operate,since distance relay estimates positive sequence impedanceby extracting the fundamental frequency current and voltagephasors. Different techniques like mimic ltering [9], doubledifferentiator [7] are available to lter out the unwantedlow frequency information. Even-though the above mentionednite impulse response lters can effectively remove expo-nentially decaying dc offset in current or voltage signals, itfails, when unwanted information is quite close to the desiredinformation i.e. fundamental frequency which is the case withCVT transients.

Relay manufacturers handle this issue by providing eitherspecial lters or counters to overcome this overreach problemdue to CVT transient. Current solution available in differentIED to handle this issue is listed in Table. I.

As it can be seen from Table. I that the current solutionis either to pull back the reach setting or to provide a xedtime delay. Moreover the existing techniques rely on frequencydomain information to detect CVT transients. This paperproposes a new and simple logic to handle this problemwithout sacricing zone 1 reach by directly monitoring thetransients in time domain itself. The proposed smart trip (ST)

IEEE ISGT Asia 2013 1569807391

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TABLE I: Techniques used in IEDs to handle issue due toCVT transient

Manufacturer Technique

Relay A xed time delay if high SIR is detected

Relay B adaptive algorithm to reduce zone 1 reach

Relay Cuse of double zone 1 where, inner zone 1 reachis dynamic without delay whereas outer zone 1

has xed reach (100%) with time delay

Relay D

patented technique to block trip signalbased on frequency domain informationfor a xed time delay (assuming CVT transientsdies out within this time delay) if high SIR is detected

Relay E special lters are introduced in voltage pathif high SIR is detected in addition to adaptive counter

logic, blocks the trip signal if it detects that the CVT signal isnot t (SNF) to be used for trip decision. The added featureis that, the blocking time is adaptive as it depends on theextracted unwanted signal information.

III . S MART TRIP LOGIC

This section discusses the functioning of proposed smarttrip (ST) logic which is shown in Fig. 1. The proposed logicdecides whether to forward the trip command to the circuitbreaker or not. The main advantage of this proposed logicis, the decision is based on the information available in timedomain. In order to perform this task, one cycle moving

Ph. ElementRY Z 1Y BZ 1BR Z 1

G. ElementR Z 1Y Z 1B Z 1

Trip SC T

V r (t) Filter V lth V rf (t) V uthV rf

V y (t) Filter V lth V yf (t) V uthV yf

V b(t) Filter V lth V bf (t) V uthV bf

Signal Not Fit SNF

Smart Trip ST

Block TripSIR> 5

Proposed

BT

Latching Relay

Fig. 1: Proposed smart trip logic

where,R Z 1 , Y Z 1 , B Z 1 Ground elementsRY Z 1 , Y B Z 1 , BR Z 1 Phase elementsSC Security counterV rf , V yf , V bf Filter outputV r (t ), V y (t ), V b(t) Voltage samplesSNF Signal not tBT Block tripT TripST Smart tripV lt Lower thresholdV ut Upper threshold

average lter (MAF), as shown in equation (1) is used toextract the unwanted information from the voltage sampleswhich are obtained after prepossessing using anti-aliasing lter(AAF).

y[n ] = 1N

N 1

k =0

x [n k] (1)

where,

N number of samples per power cyclen sample numberx input voltage sampley lter output

The extracted time domain information is compared withboth lower ( V lth ) and upper ( V uth ) bounds to assert SNF, sincethe output of MAF ( V rf , V yf , V bf ) will be almost zero duringnormal operating condition or when CVT transients dies outcompletely. Ideally the lter output should be zero when CVTtransients dies out completely, but it will not be zero due

to errors quantization errors and due to the presence of arcresistance. A threshold setting of 1V is used to monitor CVTtransients and no user setting is required. SNF gets asserted if any phase voltage violates the threshold condition indicatingthat the signal is not t for trip decision, thereby blockingthe trip signal asserted by zone 1 ground ( R Z 1 , Y Z 1 , B Z 1 ) orphase ( RY Z 1 , Y B Z 1 , BR Z 1 ) elements if estimated SIR [11]is above 5.

IV. T EST SYSTEM MODELING AND SIMULATION

In order to test the performance of ST logic, system shownin Fig. 2 is implemented in Alternative Transient Program(ATP). The 200km transmission line ( Z L ) [12] shown in

Protected by Zone 1 instantaneous Protected by Zone 2 with time delay typically (200ms)

CT CVT Zone 2

Zone 1

Source A Source B

Bus A Bus B

Zone 1

Zone 2 CT CVT

Z a Z L CB CB Z b

IED A

IED B

Fig. 2: Single line diagram of 400kV test system

where,Z a , Z b Source impedanceZ L line impedanceCB Circuit breakerIED Intelligent Electronic Device

Fig. 2 is modeled as frequency dependent line model [13]with CVT model [14], [15], CT model [16], primary arcmodel along with elongation effect [17] and bus bar model.

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Source impedance ( Z a , Z b) is modeled as distributed param-eter model. Distance relay ( IED A ) is modeled as positivesequence polarized mho characteristic [2] as shown in Fig. 3.

AAF

Samplingunit, sampling

frequency600Hz

Double differ-entiatior lter

SmartTrip LogicFull cycle

discreteFourier

transform

AAF

Samplingunit, sampling

frequency600Hz

Double differ-entiatior lter

Full cyclediscreteFourier

transform

positivesequencepolarizedmho char-acteristic

with securitycount 2 fortrip decision

vr,y,b CVT

ir,y,b from CT

T ST

Fig. 3: Model of numerical distance relay with ST logic

In-order to satisfy Nyquist sampling theorem [18], theextracted fault information is ltered by anti-aliasing low passlter before sampling, which is done at a rate of 600Hz. Thesignals are then preprocessed before it is fed to the discreteFourier transform, which transforms the time domain informa-tion to frequency domain information in the form of phasors.The extracted information i.e fundamental frequency voltageand current phasors are then fed to the positive sequencepolarized mho characteristic distance relay and nally theavailable information i.e. the current, voltage and polarizingphasors is fed to the ground and phase elements for tripdecision.

In-order to verify the performance of ST logic, reach settingof zone 1 elements for both ground and phase elements arekept at 50% of line reach i.e. 100km of line length and singleline to ground fault is applied at time instant T f at Bus B.Since the fault is outside zone 1 reach setting i.e. 100%, itis expected that zone 1 element i.e. either ground element orphase element should not assert trip signal for faults outsideits protected zone.

Fig. 4 shows the fault information available to the numericaldistance relay, lter outputs and trip signals for SI R = 30and s = 30 , where s is the loading angle of sending endgenerator i.e. at Bus A. In high SIR condition, the relayoverreaches and asserts the trip signal (T) due to the presenceof CVT transients immediately after fault as shown in Fig. 4.Fig. 4 also indicates that, due to CVT transients the estimatedimpedance trajectory moves into zone 1 characteristic therebyasserting the trip signal (T) and then moves out after CVTtransients dies out thereby de-asserting the trip signal(T). How-ever the ST logic which supervises the trip signal blocks thissignal as SNF is asserted, thereby preventing maloperation.The presence of proposed ST logic will not provide hindranceto trip for in-zone faults as ST logic forwards the trip signalonce the CVT transients die out.

100

50

0

50

100

C V T s e c o n

d a r y v o

l t a g e

( V )

vr vy vb

0.15

0

0.15Voltage and current signals after

low pass ltering and sampling

C T s e c o n

d a r y c u r r e n t ( A )

ir iy ib

0

10

20

v o

l t a g e

( V )

V lth V uth V rf V yf V bf

20

30

40

S I R

SIR actual SIR estimated

0

1 T r i p

T

0 0.1 0.2 0.3 0.4 0.5 1

0T f

time (s)

T r i p

ST

Fig. 4: Voltage, current and logic signals for a single line toground fault at Bus B

V. H ARDWARE IMPLEMENTATION

In order to validate the simulation results in real time theproposed logic is realized in hardware using FPGA. FPGAcontains predened resources i.e. logic blocks which can berecongured as desired by the user for any given application.The interconnects between different logic blocks is achievedusing programmable interconnect and the external world com-munication is achieved via input output blocks. The mainadvantage in FPGA when compared to digital signal processoris the ability to construct parallel structures for processing

and it can be recongured even after eld implementation.Xilinx spartan 3A DSP 3SD1800A-FG676 [19] FPGA isused to implement, test and validate the proposed logic bysynthesizing and implementing in FPGA using Xilinx ISE-webpack.

Sending end voltage and current information is fed to theFPGA where positive sequence polarized mho characteristicdistance relay along with the proposed logic is implementedusing hardware description language (HDL) verilog. Table. IIshows the list of modules and their function which are created

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using HDL verilog.

TABLE II: Distance relay modules

Module Name Function

Discrete Fourier transform to estimate phasorsSequence transformation to estimate sequence parametersPolarizing quantity to estimate polarizing phasorGround element to estimate positive sequence impedancePhase element to estimate positive sequence impedanceProposed ST logic to prevent mal-operation

These modules processes the information in a parallelfashion rather than pipelining each processes which is theusual case in digital signal processors. In addition to this all theelements i.e. three ground elements and three phase elementsestimate positive sequence impedance simultaneously.

Fig. 5 shows the register transfer level view of the distancerelay incorporating the proposed logic which is obtained aftersynthesizing the verilog code.

Fig. 5: Register transfer level view of numerical distance relayalong with the proposed logic

This shows the complexity in hardware level since entirealgorithm has to be handled in bit level. The synthesized

code is rst validated using Xilinx simulation tool beforeimplementation at each module level. During implementationstage again each level is tested and validated using ChipScopePro which helps to tap the signals inside FPGA.

Fig. 6a and Fig. 6b shows the nal placed and routed viewin FPGA and the device utilization details are shown in Table.III. FPGA placed view in Fig. 6a gives the indication of thelogic blocks utilized to implement the entire relay and Fig. 6bshows the nal interconnection between logic blocks obtainedusing programmable interconnects.

(a) placed view (b) routed view

Fig. 6: FPGA placed and routed view

TABLE III: Device utilization summary

Logic uti lization Used Avai lable Uti liza tion

Number of slice ip ops 14263 33280 42%Number of 4 input LUT 11910 33280 35%Number of occupied slices 9586 16640 57%Number of DSP48As 83 84 98%

The implementation of proposed logic is also simple, asMAF lter can be visualized as constant coefcient niteimpulse response lter. Table IV shows the hardware con-sumption details for implementing the proposed logic in XilinxFPGA. This shows that the proposed logic can be easilyincorporated in existing relays without any major hardwaremodication.

TABLE IV: Device utilization summary

Logic utilization UtilizationRelay Relay+ ST logic

Number of slice ip ops 39% 42%Number of 4 input 32% 35%Number of occupied slices 53% 57%Number of DSP48As 98% 98%

Fig. 7 shows the graphical view of area occupied for theproposed logic (blue patches) which will be augmenting theexisting numerical distance relay algorithm (black patches).

Fig. 8 shows the actual hardware setup with test resultsvalidated using Xilinx FPGA. Three signal information are

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Fig. 8: Experimental setup showing the test results

Fig. 7: FPGA placed view highlighting the slices consumedfor the proposed logic

tapped from FPGA for oscilloscope display via input outputports. In oscilloscope display, channel 1 shows the time atwhich fault is applied i.e. 0.2 second for a total simulationtime of 0.5 seconds. Channel 2 shows the relay mal-operationwhich occurs 30ms after fault inception and channel 3 showsthe SNF signal which monitors the CVT transients in real timethereby blocking distance relay mal-operation. Oscilloscopeinformation in Fig. 8 also indicates that SNF gets asserted afterfault immediately after transient detection which is not the casein existing techniques as it consumes one power cycle time

i.e. 20ms for 50Hz to transform the information to frequencydomain. Fig. 8 also shows that the blocking time is adaptiveas it entirely depends upon the CVT transient informationavailable in time domain.

VI . CONCLUSION

This paper proposes a new and simple logic to adaptivelyblock numerical distance relay mal-operation during high SIRcondition without reducing zone 1 reach or by giving xedtime delay. With the use of existing techniques the reach wouldbe reduced to a safe level which is estimated to be 5% for theconsidered CVT and SIR, but the proposed logic prevents mal-operation even at 50% reach setting with adaptive time delay.The proposed logic is also validated in real time using XilinxFPGA.

A PPENDIX

Estimated values of transmission line parameters,

TABLE V: Line Data

line parameters Resistance (pu) Reactance (pu)positive sequence 1.46 10 3 3.70 10 2

negative sequence 1.46 10 3 3.70 10 2

zero sequence 3.39 10 2 1.15 10 1

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