1 - burnon.com · 2018. 10. 31. · The STM32W108 baseband controls TX_ACTIVE and drives it high (VDD_PADS) when in Tx mode. Select alternate output function with GPIO_PCCFGH[7:4]

- 1 -

版权声明

本文档所包含的所有信息均为浙江瑞瀛物联科技有限公司（以下简称“瑞瀛”或“本公司”）版权所有。

未经本公司书面许可，不得向本公司雇员、代理商、合作方或授权许可方以外的任何第三方泄露本文档内

容，不得以任何形式擅自复制或传播本文档。若使用者违反本版权保护的约定，本公司有权追究使用者由

此产生的法律责任。

版本更新

V1.0.0

V1.0.2

2011/06/04

2012/09/26

初稿

电源电路参考设计修改

V1.0.3

V1.0.4

2014/10/14

2018/01/08

默认芯片改为 EM357，相关参数对应修改

增加焊接炉温点，模块包装规格

- 2 -

目录

1. 产品介绍 ............................................................................................................................................................ - 4 -

1.1 产品简介 .................................................................................................................................................. - 4 -

1.2 产品应用 .................................................................................................................................................. - 4 -

1.3 主要特性 .................................................................................................................................................. - 5 -

1.4 产品优势 .................................................................................................................................................. - 5 -

1.5 名称缩写和简写 ....................................................................................................................................... - 6 -

1.6 相关文档 .................................................................................................................................................. - 7 -

2. 产品概述 ............................................................................................................................................................ - 8 -

2.1 概述 .......................................................................................................................................................... - 8 -

3. 技术规格 ............................................................................................................................................................ - 9 -

3.1. 电气特性 ................................................................................................................................................. - 9 -

3.2. 物理/环境特性 ..................................................................................................................................... - 11 -

3.3. 引脚配置 ............................................................................................................................................... - 11 -

3.4. 模块功率模式配置 ............................................................................................................................... - 20 -

3.5 天线规格 ................................................................................................................................................ - 22 -

3.6. 模块电路参考设计 ............................................................................................................................... - 26 -

3.7. 模块调试与编程接口连接 ................................................................................................................... - 27 -

3.8. 射频性能测试结果 ............................................................................................................................... - 27 -

3.9. 模块包装规格 ....................................................................................................................................... - 29 -

3.9.1. 模块焊接温度 ................................................................................................................................... - 30 -

- 3 -

4. 订购信息 .......................................................................................................................................................... - 30 -

5. 联系我们 .......................................................................................................................................................... - 31 -

- 4 -

1. 产品介绍

1.1 产品简介

REX3U 是外形小巧、高灵敏度的低功率 ZigBee 模块。基于瑞瀛创新型 RexBee

硬件平台，该模块符合 IEEE 802.15.4 规范和 ZigBeePRO 通信协议，已广泛应用于

无线传感、控制及数据采集等领域。使用该模块为用户的开发省去大量的时间和精力，

从而为产品推向市场节约了时间和开发成本。

1.2 产品应用

瑞瀛 RexBee 模块符合 IEEE802.15.4 规范和 ZigBeePRO 协议，支持自我修复、自我组织的网状网络，

优化了网络流量并降低了功耗。该模块支持两种应用配置：

透明传输：用户可根据我司的 AT 指令程序，进行程序开发

客户定制：我司可根据客户的具体应用，为客户提供可靠、安全的应用程序

模块的应用包括但不限于：

楼宇自动化和监控

照明控制

无线烟感和瓦斯探测器

结构完整性监控

HVAC 监测和控制

库存管理

环境监测

安防

工业监控

机械设备状态和性能监测

植物系统监测 (如温度、压强、水流量、湿度等)

自动抄表

- 5 -

1.3 主要特性

尺寸：18.00*15.00*2.60mm

输出功率高达 8dBm

高接收灵敏度：最高-99 dBm

出色的链路预算：107dB

可靠通信范围广: 300m (可视距离)

极低的功耗

休眠模式：

- 6 -

1.5 名称缩写和简写

ADC Analog-to -Digital Converter

API Application Programming Interface

DC Direct Current

DTR Data Terminal Ready

DIP Dual In-line package

EEPROM Electrically Erasable Programmable Read-Only Memory

ESD Electrostatic Discharge

GPIO General Purpose Input/Output

HAL Hardware Abstraction Layer

HVAC Heating, Ventilating and Air Conditioning

HW Hardware

TWI Inter-Integrated Circuit

IEEE Institute of Electrical and Electronics Engineers

IRQ Interrupt Request

ISM Industrial, Scientific and Medical radio band

JTAG Digital interface for debugging of embedded device, also known as

IEEE 1149.1 standard interface

MAC Medium Access Control layer

MCU Microcontroller Unit. In this document it also means the processor,

which is the core of ZigBee module

NWK Network layer

OEM Original Equipment Manufacturer

OTA Over-The-Air upgrade

PCB Printed Circuit Board

PER Package Error Ratio

PHY Physical layer

RAM Random Access Memory

RF Radio Frequency

RTS/CTS Request to Send/ Clear to Send

RX Receiver

SMA Surface Mount Assembly

SPI Serial Peripheral Interface

SW Software

TX Transmitter

UART Universal Asynchronous Receiver/Transmitter

USART Universal Synchronous/Asynchronous Receiver/Transmitter

- 7 -

USB Universal Serial Bus

ZDK ZigBee Development Kit

ZigBeePRO Wireless networking standards targeted at low-power applications

802.15.4 The IEEE 802.15.4-2003 standard applicable to low-rate wireless PAN

1.6 相关文档

[1] IEEE Std 802.15.4-2003 IEEE Standard for Information technology - Part 15.4 Wireless Medium

Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area

Networks (LR-WPANs)

[2] ZigBee Specification. ZigBee Document 053474r17, October 19, 2007

- 8 -

2. 产品概述

2.1 概述

REX3U 是一款外形小巧、高灵敏度的低功率 ZigBee 模块，符合 IEEE 802.15.4 规范和 ZigBeePRO 标

准。基于瑞瀛创新型 RexBee 硬件平台，拥有极其出色的射频性能、极低的功耗，非常易于用户集成。

图 2-1. 产品框图

REX3D 模块符合 FCC、IC 和 CE 规范，能应用于多种不同环境中的设备，符合 RoHS 规范。

同时，本公司还提供一整套完整的开发和评估套件，用户可根据自身需求选择不同版本套件进行测试

及开发。

2.4GHz

Radio

O-QPSK

Modem

IEEE802.15.4

MAC

Accelerator

Encryption

Accelerator

Power

Management

Data

RAM

12kB

Program

Flash

192kB

ARM CORTEX-M3®

CPU with NVIC and

MPU

SPI

TWI

Timers

UART

GPIO

registers

Cortex M3 Core

Antenna

Matching

Network

XTAL (Crystal Frequency 24MHz)

Balun

- 9 -

3. 技术规格

3.1. 电气特性

3.1.1. 电气特性

表 3-1. 绝对最大额定参数

参数最小值最大值

模块供电电压范围（VCC） 2.1V 3.6V

引脚工作电压范围（ADC 引脚除外） -0.3V VDD_PADS+0.3

ADC 引脚工作电压范围 -0.3V 2.0V

芯片所有 I/O 最大驱动电流数据

40 mA

芯片最大接收射频信号强度

+10 dBm

注意: 超过绝对最大额定参数可能对模块造成毁害。在任何情况下，用户都不可违反上表所列的绝对最大额

定参数。若有违反，可能对模块造成不可挽回的危害。

3.1.2. 测试条件

表 3-2. 测试条件 ( 除非另行约定 ), VCC = 3.3V, 温度 = 25°C

参数范围单位

供电电压, VCC 2.1 to 3.6 V

接收电流 29 mA

发射电流（@3dBm） 36 mA

发射电流（@8dBm） 45 mA

休眠电流

- 10 -

3.1.3. 射频特性

表 3-3. RF 射频特性

参数测试条件范围单位

工作频段 2400~2483.5 MHz

频段数量 16

信道编号 0B~1A Hex

信道间隔 5 MHz

发射功率 -32 to +8 dBm

接收灵敏度丢包率≤1% -99 dBm

最大传输速率 250 kbps

额定输入/输出阻抗 For unbalanced output 50 Ω

3.1.4. 处理器特性

表 3-4.处理器特性


片上 Flash 存储空间 192K bytes

片上 RAM 存储空间 12K bytes

工作频率 24 MHz

3.1.5. 模块接口特性

表 3-5.模块接口特性


UART 最大波特率 230400 bps

模拟通道的分辨率/转换时间半双工模式 12/4096 Bits/µs

模拟输入阻抗 >1 MΩ

模拟参考电压（VREF） 1.2 V

模拟输入电压 0 - VREF V

I2C 总线最大时钟频率 400 KHz

GPIO 输出电压(逻辑 0) -8/ 4 mA 0 ~ 0.18*VCC V

GPIO 输出电压(逻辑 1) -8/ 4 mA 0.82*VCC ~ VCC V

实时时钟频率 32.768 KHz

- 11 -

3.2. 物理/环境特性

表 3-6. 物理/环境特性

参数值备注

物理尺寸 18.0*15.0*2.6mm

重量 1.1g

工作温度 -40°C to +85°C

工作相对湿度

- 12 -

图 3-9. 引脚配置

- 13 -

表 3-10. 引脚说明

模块引

脚编号

QFN48 封

装引脚编号

引脚信号方向引脚说明

1 GND - Ground

2 11

PC5 I/O Digital I/O;

TX_ACTI

VE O

Logic-level control for external Rx/Tx switch. The STM32W108

baseband controls TX_ACTIVE and drives it high (VDD_PADS)

when in Tx mode. Select alternate output function with

GPIO_PCCFGH[7:4]

3 13

PC6 I/O Digital I/O;

OSC32B I/O 32.768 kHz crystal oscillator Select analog function with

GPIO_PCCFGH[11:8]

nTX_ACT

IVE O

Inverted TX_ACTIVE signal (see PC5) Select alternate output

function with GPIO_PCCFGH[11:8]

4 14

PC7 I/O Digital I/O

OSC32A I/O 32.768 kHz crystal oscillator. Select analog function with

GPIO_PCCFGH[15:12]

OSC32_E

XT I Digital 32 kHz clock input source

5 18

PA7

I/O

High

curr

ent

Digital I/O. Disable REG_EN with GPIO_DBGCFG[4]

TIM1_CH

4

O

Timer 1 Channel 4 output Enable timer output with TIM1_CCER

Select alternate output function with GPIO_PACFGH[15:12]

Disable REG_EN with GPIO_DBGCFG[4]

I Timer 1 Channel 4 input. (Cannot be remapped.)

REG_EN O External regulator open drain output. (Enabled after reset.)

6 19

PB3 I/O Digital I/O

TIM2_CH

3

O

Timer 2 channel 3 output Enable remap with TIM2_OR[6]

Enable timer output in TIM2_CCER Select alternate output

function with GPIO_PBCFGL[15:12]

I Timer 2 channel 3 input. Enable remap with TIM2_OR[6].

- 14 -

模块引

脚编号

QFN48 封

装引脚编号


UART_C

TS I

UART CTS handshake of Serial Controller 1 Enable with

SC1_UARTCFG[5] Select UART with SC1_MODE

SC1SCLK

O

SPI master clock of Serial Controller 1 Either disable timer

output in TIM2_CCER or disable remap with TIM2_OR[6]

Enable master with SC1_SPICFG[4] Select SPI with

SC1_MODE Select alternate output function with

GPIO_PBCFGL[15:12]

I SPI slave clock of Serial Controller 1 Enable slave with

SC1_SPICFG[4] Select SPI with SC1_MODE

7 20

PB4 I/O Digital I/O

TIM2_CH

4

O



function with GPIO_PBCFGH[3:0]


UART_R

TS O

UART RTS handshake of Serial Controller 1 Either disable timer

output in TIM2_CCER or disable remap with TIM2_OR[7]

Enable with SC1_UARTCFG[5] Select UART with SC1_MODE

Select alternate output function with GPIO_PBCFGH[3:0]

SC1nSSE

L I

SPI slave select of Serial Controller 1 Enable slave with


8 21

PA0 I/O Digital I/O

TIM2_CH

1

O

Timer 2 channel 1 output Disable remap with TIM2_OR[4]


function with GPIO_PACFGL[3:0]

I Timer 2 channel 1 input. Disable remap with TIM2_OR[4].

SC2MOSI

O

SPI master data out of Serial Controller 2 Either disable timer

output in TIM2_CCER or enable remap with TIM2_OR[4]



GPIO_PACFGL[3:0]

I SPI slave data in of Serial Controller 2 Enable slave with


9 22

PA1 I/O Digital I/O

TIM2_CH

3

O





- 15 -

模块引

脚编号

QFN48 封

装引脚编号


SC2SDA I/O

TWI data of Serial Controller 2 Either disable timer output in

TIM2_CCER or enable remap with TIM2_OR[6] Select TWI with

SC2_MODE Select alternate open-drain output function with

GPIO_PACFGL[7:4]

SC2MISO

O

SPI slave data out of Serial Controller 2 Either disable timer


Enable slave with SC2_SPICFG[4] Select SPI with SC2_MODE

Select alternate output function with GPIO_PACFGL[7:4]

I SPI master data in of Serial Controller 2 Enable slave with


10 24

PA2 I/O Digital I/O

TIM2_CH

4

O





SC2SCL I/O

TWI clock of Serial Controller 2 Either disable timer output in

TIM2_CCER or enable remap with TIM2_OR[7] Select TWI with

SC2_MODE Select alternate open-drain output function with

GPIO_PACFGL[11:8]

SC2SCLK

O

SPI master clock of Serial Controller 2 Either disable timer




GPIO_PACFGL[11:8]

I SPI slave clock of Serial Controller 2 Enable slave with


11 25

PA3 I/O Digital I/O

SC2nSSE

L I

SPI slave select of Serial Controller 2 Enable slave with


TRACEC

LK O

Synchronous CPU trace clock Either disable timer output in

TIM2_CCER or enable remap with TIM2_OR[5] Enable trace

interface in ARM core Select alternate output function with

GPIO_PACFGL[15:12]

TIM2_CH

2

O





12 26 PA4 I/O Digital I/O

- 16 -

模块引

脚编号

QFN48 封

装引脚编号


ADC4 Anal

og ADC Input 4. Select analog function with GPIO_PACFGH[3:0].

PTI_EN O

Frame signal of Packet Trace Interface (PTI). Disable trace

interface in ARM core. Select alternate output function with

GPIO_PACFGH[3:0].

TRACED

ATA2 O

Synchronous CPU trace data bit 2. Select 4-wire synchronous

trace interface in ARM core. Enable trace interface in ARM core.

Select alternate output function with GPIO_PACFGH[3:0].

13 27

PA5 I/O Digital I/O

ADC5 Anal

og ADC Input 5. Select analog function with GPIO_PACFGH[7:4].

PTI_DAT

A O

Data signal of Packet Trace Interface (PTI). Disable trace

interface in ARM core. Select alternate output function with

GPIO_PACFGH[7:4].

nBOOTM

ODE I

Embedded serial bootloader activation out of reset. Signal is

active during and immediately after a reset on NRST.

TRACED

ATA3 O

Synchronous CPU trace data bit 3. Select 4-wire synchronous

trace interface in ARM core. Enable trace interface in ARM core.


14 29

PA6

I/O

High

curr

ent

Digital I/O

TIM1_CH

3

O Timer 1 channel 3 output Enable timer output in TIM1_CCER


I Timer 1 channel 3 input (Cannot be remapped.)

15 12 nRESET I Active low chip reset (internal pull-up)

16 30

PB1 I/O Digital I/O

SC1MISO O

SPI slave data out of Serial Controller 1 Either disable timer

output in TIM2_CCER or disable remap with TIM2_OR[4] Select

SPI with SC1_MODE Select slave with SC1_SPICR Select

alternate output function with GPIO_PBCFGL[7:4]

SC1MOSI O

SPI master data out of Serial Controller 1 Either disable timer


SPI with SC1_MODE Select master with SC1_SPICR Select

alternate output function with GPIO_PBCFGL[7:4]

SC1SDA I/O TWI data of Serial Controller 1 Either disable timer output in

TIM2_CCER, or disable remap with TIM2_OR[4] Select TWI

- 17 -

模块引

脚编号

QFN48 封

装引脚编号


with SC1_MODE Select alternate open-drain output function

with GPIO_PBCFGL[7:4]

SC1TXD O

UART transmit data of Serial Controller 1 Either disable timer


UART with SC1_MODE Select alternate output function with

GPIO_PBCFGL[7:4]

TIM2_CH

1

O





17 31

PB2 I/O Digital I/O

SC1MISO I SPI master data in of Serial Controller 1 Select SPI with

SC1_MODE Select master with SC1_SPICR

SC1MOSI I SPI slave data in of Serial Controller 1 Select SPI with

SC1_MODE Select slave with SC1_SPICR

SC1SCL I/O

TWI clock of Serial Controller 1 Either disable timer output in

TIM2_CCER, or disable remap with TIM2_OR[5] Select TWI

with SC1_MODE Select alternate open-drain output function

with GPIO_PBCFGL[11:8]

SC1RXD I UART receive data of Serial Controller 1 Select UART with

SC1_MODE

TIM2_CH

2

O



function with GPIO_PBCFGL[11:8]


18 32

SWCLK I/O Serial Wire clock input/output with debugger Selected when in

Serial Wire mode (see JTMS description, Pin 35)

JTCK I

JTAG clock input from debugger Selected when in JTAG mode

(default mode, see JTMS description, Pin 35) Internal pull-down

is enabled

19 35

PC4 I/O Digital I/O Enable with GPIO_DBGCFG[5]

JTMS I

JTAG mode select from debugger Selected when in JTAG mode

(default mode) JTAG mode is enabled after power-up or by

forcing NRST low Select Serial Wire mode using the

ARM-defined protocol through a debugger Internal pull-up is

enabled

SWDIO I/O Serial Wire bidirectional data to/from debugger Enable Serial

- 18 -

模块引

脚编号

QFN48 封

装引脚编号


Wire mode (see JTMS description) Select Serial Wire mode

using the ARM-defined protocol through a debugger Internal

pull-up is enabled

20

36

PB0 I/O Digital I/O

VREF Anal

og O

ADC reference output. Enable analog function with

GPIO_PBCFGL[3:0].

VREF Anal

og I

ADC reference input. Enable analog function with

GPIO_PBCFGL[3:0]. Enable reference output with an ST

system function.

IRQA I External interrupt source A.

TRACEC

LK O

Synchronous CPU trace clock. Enable trace interface in ARM

core. Select alternate output function with GPIO_PBCFGL[3:0].

TIM1CLK I Timer 1 external clock input.

TIM2MSK I Timer 2 external clock mask input.

21 34

PC3 I/O Digital I/O Either Enable with GPIO_DBGCFG[5], or enable

Serial Wire mode (see JTMS description)

JTDI I

JTAG data in from debugger Selected when in JTAG mode

(default mode, see JTMS description, Pin 35) Internal pull-up is

enabled

22 33

PC2 I/O Digital I/O Enable with GPIO_DBGCFG[5]

JTDO O JTAG data out to debugger Selected when in JTAG mode (default

mode, see JTMS description, Pin 35)

SWO O

Serial Wire Output asynchronous trace output to debugger Select

asynchronous trace interface in ARM core Enable trace interface in

ARM core Select alternate output function with

GPIO_PCCFGL[11:8] Enable Serial Wire mode (see JTMS

description, Pin 35) Internal pull-up is enabled

23 38

PC1 I/O Digital I/O

ADC3 Anal

og ADC Input 3 Enable analog function with GPIO_PCCFGL[7:4]

SWO O

Serial Wire Output asynchronous trace output to debugger Select

asynchronous trace interface in ARM core Enable trace interface in

ARM core Select alternate output function with GPIO_PCCFGL[7:4]

TRACEDA

TA0 O

Synchronous CPU trace data bit 0 Select 1-, 2- or 4-wire synchronous

trace interface in ARM core Enable trace interface in ARM core Select

alternate output function with GPIO_PCCFGL[7:4]

- 19 -

模块引

脚编号

QFN48 封

装引脚编号


24 40

PC0

I/O

High

curre

nt

Digital I/O Either enable with GPIO_DBGCFG[5], or enable Serial Wire

mode (see JTMS description, Pin 35) and disable TRACEDATA1

JRST I

JTAG reset input from debugger Selected when in JTAG mode (default

mode, see JTMS description) and TRACEDATA1 is disabled Internal

pull-up is enabled

IRQD (1) I Default external interrupt source D

TRACEDA

TA1 O

Synchronous CPU trace data bit 1 Select 2- or 4-wire synchronous

trace interface in ARM core Enable trace interface in ARM core Select

alternate output function with GPIO_PCCFGL[3:0]

25 43

PB5 I/O Digital I/O

ADC0 Anal

og ADC Input 0 Enable analog function with GPIO_PBCFGH[7:4]

TIM2CLK I Timer 2 external clock input

TIM1MSK I Timer 2 external clock mask input

26 42

PB6

I/O

High

curre

nt

Digital I/O

ADC1 Anal


IRQB I External interrupt source B

TIM1_CH1 O

Timer 1 channel 1 output Enable timer output in TIM1_CCER Select

alternate output function with GPIO_PBCFGH[11:8]

I Timer 1 channel 1 input (Cannot be remapped)

27 41

PB7

I/O

High

curre

nt

Digital I/O

ADC2 Anal


IRQC (1) I Default external interrupt source C

TIM1_CH2 O

Timer 1 channel 2 output Enable timer output in TIM1_CCER Select

alternate output function with GPIO_PBCFGH[15:12]

I Timer 1 channel 2 input (Cannot be remapped)

28 GND - Ground

29 3.3V I DC3.3V supply

30

- 20 -

3.4. 模块功率模式配置

本文档用于协助用户通过串口（UART）对本公司生产的不同型号的无线通信模块的功率模式进行配置。

用户可以使用通用的串口调试软件与无线模块连接，通过 AT 指令对模块完成配置。在默认情况下，COO

和 HHU 设备的 UART 通信波特率是 115200，8 个数据位，1 停止位，无校验位，记为 115200-8-N-1；

ROUTER 设备的 UART 配置为 9600-8-N-1。可以通过发送 AT+VER 指令来验证与模块的 UART 连接是否

正常。完整的 AT 指令描述可以参考本公司相关文档 (www.rexense.cn)。

获得当前模块的配置信息

在使用 UART 调试时，可以通过 AT+GETINFO 指令来获得模块的配置信息。

从返回信息可以获得无线通信模块的基本配置信息。与无线通信模块功率配置相关的信息包括：

Pwr=+08：指示无线通信芯片的发射功率为+8dBm；

- 21 -

PMode=0000：指示无线通信模块的功率模式采用的是标准模式。

重要说明：

1. 无线通信芯片的发射功率是指，在无线通信模块中的无线通信芯片，其基本的发射功率。

对于 REX3U 无线通信模块而言，无线通信芯片的发射功率就是无线通信模块的发射功率。因此，

为了获得较为理想的通信效果，建议将无线通信芯片的发射功率设置为+8dBm；

芯片的发射功率可以使用 AT+SETPWR 指令配置。

2. 无线通信模块的功率模式是指，无线通信模块是否采用了外部功放模式。

对于 REX3U 无线通信模块而言，无外部功放，需要工作于标准模式，使用如下的 AT 指令：

AT+SETPWRMODE=0000

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3.5 天线规格

REX3U 有 2 种天线可供用户选择，如下图所示。这 2 种天线是通过硬件跳线选择的，因此用户购买模

块时，请与销售人员确定模块选用的天线类型。天线选择跳线说明如下图所示：

图 3-11.跳线示意图

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使用简易天线：

使用外接天线：

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3.5.1 简易天线

图 3-12. 简易天线

3.5.2 U.FL 连接头

图 3-13. U.FL 连接头

备注：当使用 U.FL 连接头时，需要同时使用天线连接线和 SMA 天线，如下图:

图 3-14.天线连接线

天线连接线 (AN11): 连接线长度(11cm)，插入损耗(1dBi)

U.FL 连接头

简易天线

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图 3-15. SMA 天线

SMA 天线 (AN2400): 增益(2dBi)

图 3-16. 模块整体图片

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3.6. 模块电路参考设计

3.6.1. 系统电路为 3.3V 时

3.6.2. 系统电路为 5.0V 时

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3.7. 模块调试与编程接口连接

图 3-16. SWD 连接方式

3.8. 射频性能测试结果

图 3-17. 接收灵敏度

图 3-25. 载波信号测试

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图 3-18. 调制信号测试

- 29 -

3.9. 模块包装规格

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3.9.1. 模块焊接温度

模块焊接最高炉温区间 237-245℃，时间

- 31 -

5. 联系我们

浙江瑞瀛物联科技有限公司地址：杭州市滨江区江陵路 88 号万轮科技园 10 幢北座 10 楼

电话：0571-28081053

传真：0571-87987620

Email: [email protected]

网址：www.rexense.cn
mailto:[email protected]://www.rexense.cn/

Documents

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