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1
Why Low Power Testing?
台大電子所 李建模
2
Test is HOT! Power consumption in test mode higher than normal operation
2 X higher [Zorian 93] ISCAS Benchmark circuit simulation [Li 04]
CUT Normal (mW) Scan mW( X higher than normal)
s526 89.5231.2
(1.58X)
s1494 220.0438.0
(1.99X)
s5378 979.91,831.7(1.87X)
s9234 1,303.33,026.8(2.32X)
s38417 5,452.711,618.3
(2.13X)
average 1,210.32,092.7(1.73X)
3
Why Test Power is High?
ATPG patterns try to detect as many faults as possible High toggle activities when testing
ATPG patterns less correlated than functional patterns [Wang 97]
Many circuit nodes are only toggling when scan chains shift
Some DFT circuit only activated in test mode
4
Why Low Power Testing?
Avoid power problems (e.g. IR drop) in test mode Ensure correct operation in test mode
Protect CUT from overheating in test mode No expensive package for testing
Enable parallel testing of multiple cores in SOC Save test time
Avoid reliability problems Overheating can shorten CUT lifetime
5
Intel CPU Power (Normal Operation)
Source: Borkar, De Intel
Pow
er
(Watt
s)
Of
Inte
l P
art
s
4004
80088080
8085
8086
286
386
486
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
P6
Pentium®
History and projection
6
Types of Power Dissipation
Classified by Circuit Operation Classified by Circuit Type Classified by Time
7
Classified by Circuit Operation Static power dissipation (circuit activity independent)
Leakage power Dynamic power dissipation (circuit activity dependent)
Short circuit power Switch power
8
Classified by Circuit Operation (2)
Source: Synopsys Power Compiler
9
Short Circuit Power
Short Circuit Power Caused by momentary short circuit current
When NMOS PMOS both on Occurs only when circuit switching Can be estimated by the equation
Ei = energy consumed per transition of gate i. usually provided by the ASIC vendor
TRi = toggle rate of output of gate i. TRi is usually obtained by simulation
)( iigateallforiSC TREP
10
Short Circuit Power
Transient short circuit current, ISC
11
Switching Power
Switching Power is Caused by charging and discharging load capacitance
Wire capacitance, parasitic capacitance Occurs only when circuit is switching Can be estimated by the equation
Cload i = total load capacitance connected to net i. extracted from layout or estimated by synthesis tool
TRi = toggle rate of output of gate i. TRi is usually obtained by simulation
)(.2
2
iinetallfor
iloadDD
SW TRCV
P
12
Leakage Power Leakage power is
Caused by static leakage current Such as source to drain, gate tunneling currents
Independent of circuit activities Dependent on technology
Such as transistor Vt , VDD
Not a big concern …. yet Maybe problems in future generations
Can be estimated by Ileak VDD
13
Leakage Power Projection
Source: Borkar, De Intel
Pow
er
(Watt
s)
Of
Inte
l P
art
s
40048008
80808085
8086286
386486
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
P6
0
.4
.8
1.2
1.6
2
2000 2002 2004 2006 2008
VD
D a
nd
VT
Pentium®
8KW
1.7KW
400W
88W 12W
0%
10%
20%
30%
40%
50%
2000 2002 2004 2006 2008
Dra
in L
eakag
e P
ow
er
14
Leakage Significant When Burn In
Leakage power dominates burn in power
Source [Intel 02], [Miller 01]
15
Classified by Circuit Types
Logic power Power dissipation in combinational logic
Sequential power Power dissipation in the sequential elements
Such as scan chain, or latches Clock power
Power dissipation in clock tree
Other types of circuits (not covered in this lecture) Memory power
SRAM, DRAM Analog, Mixed Signal Power
16
Breakdown of Power Dissipation
ISCAS Benchmark Circuit (s9234)
0
200
400
600
800
1000
1200
1400
1600
BIST DFT Non-Scan
Pow
er (
uW)
SC.COMB.
SC.SEQ.
SW.
CLK CLK CLK
Source [Li 04]
SC = Short Ckt SW = Switching
17
Average power Peak power
Classified by time
Time (Clock cycle)
Power waveforms: Dividing a scan chain into two sub-chains [Lee 04]
18
My opinion
Low power testing not really needed now But will be needed in future Especially for burn in
Area needs more research Peak power reduction still needs more research Static power is difficult to control