TABLE OF CONTENTS1. 8086 (definition + specification).....................03 2. Comparison b/w 8085 & 808605 3. Architecture of 808606 4. Registers of 8086..09 5. Advantages of Segmented memory16 6. Addressing modes of 808617 7. Pin Diagram24 8. Instructions of 8086.28 9. Conclusion.36

DEFINITION & SPECIFICATIONMicroprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions. Most Micro Processor are single- chip devices. The 8086 (also called iAPX86) is a 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978. 16-bit processor, 16-bit data bus, 16-bit general purpose registers, 20-bit address bus-which can address 1 MB of memory, 1st member of 80x86 family, concept of segmented memory, new instruction set supported by all upcoming processors of the family 80x86.

Key Features:Released by Intel in 1978 Produced from 1978 to 1990s A 16-bit microprocessor chip. Max. CPU clock rate : 5 MHz to 10 MHz Instruction set: x86-16 Package: 40 pin DIP Intel 8086 Microprocessor The 8086 gave rise to the x86 architecture of Intel's future processors. Common manufacturer(s): Intel, AMD, NEC, Fujitsu, Harris (Intersil), OKI, Siemens AG, Texas Instruments, Mitsubishi.

COMPARISON B/W 8085 & 80868085 Created in 1977 8-bit processor 8-bit data bus 8-bit general purpose registers 16-bit address bus It can access 64k of memory Simplest Architecture Clock speed is 3Mhz Less operational instructions No. of Flags=5

8086 Created in 1978 16-bit processor 16-bit data bus 16-bit general purpose register 20-bit address bus It can access 1 MB of memory Complex Architecture Clock speed is 5Mhz More operational instructions No. of Flags=9

ARCHITECTURE OF 8086

BIU ( BUS INTERFACE UNIT) Transfer of Data & Address on buses Sends Addresses Fetch Instruction Read Data Write Data Includes 4 Segment Register BIU has an array of 6 Registers called Queue.

EU (EXECUTION UNIT) Read instructions from Queue, Decode & Execute. 16-bit Arithmetic unit, 16-bit flag Register, four General purpose Register, four 16-bit offset Register. Pipelining (The process of fetching the next instruction while the current instruction is executing).

REGISTERS OF 8086

GENERAL PURPOSE REGISTERS

1. AX (Accumulator) 2. BX (Base Register) 3. CX (Counter Register) 4. DX (Data Register)

FLAG REGISTERO D I T S Z AC P CY

FLAG REGISTER1.

2. 3. 4. 5. 6. 7. 8. 9.

CY (Carry Flag) P (Parity Flag) AC (Auxiliary Carry Flag) Z (Zero Flag) S (Sign flag) OF (Overflow Flag) DF (Direction Flag) IF (Interrupt Flag) TF (Trap Flag)

SEGMENT REGISTER

1.Code Segment (CS) 2.Data Segment (DS) 3.Stack Segment (SS) 4.Extra Segment (ES)

OFFSET REGISTER

1.Instruction Pointer (IP) 2.Stack Pointer (SP) 3.Source Index (SI) 4.Destination Index (DI) 5.Base Pointer (BP)

ADVANTAGES OF SEGMENTED MEMORY To Form 20-bit memory Address Program can work on different set of Data Program can be loaded or executed anywhere in the memory In multitasking environment, different programs may run simultaneously on different terminal using the common processor and memory, by reloading the contents of various segment Registers for each program.

ADDRESSING MODES OF 80861. Register Addressing Mode 2. Immediate Addressing Mode 3. Direct Addressing Mode 4. Indirect Addressing Mode (Register Indirect, Indexed, Based, Based & Indexed, Based & Indexed with Displacement) 5. String Addressing Mode 6. Port Addressing Mode

REGISTER ADDRESSING

Operands are microprocessor Registers

MOV AX, BX

IMMEDIATE ADDRESSINGThe Data remains in the part of the instruction

MOV BX, 2052H

DIRECT ADDRESSINGThe memory Offset address is directly available in the instruction.

MOV CL, [2000H]

INDIRECT ADDRESSINGMemory Offset address is specified in some Microprocessor Register, Various Combinations are possible.

(A)Register Indirect (B)Indexed Indirect (C)Based Indirect (D)Based & Indexed

MOV DX, [SI] MOV DL, [SI+12] MOV DL, [BP-25] MOV [BP+SI], DH

(E)Based & Indexed with Displacement MOV DL, [BP+SI+23a4H]

STRING ADDRESSING Special Instructions are available to handle Strings The m/m address of the source Data is specified by DS:SI The m/m address of the destination data By ES:DI

I. MOVSB II. LODSB III.STOSB

PORT ADDRESSINGTo read Data from an input port

IN AL, 42HTo write Data to an output port OUT 25H, AL

PIN DIAGRAM OF 8086

PINS COMMON FOR MAXIMUM & MINIMUM MODEAD15-AD0 2. A19/S6, A18/S5, A17/S4, A16/S3 3. BHE (BAR)/S7 4.RD (BAR) 5. READY 6. INTR (Interrupt Request) 7. NMI (Non Maskable Interrupt) 8. TEST (BAR) 9. RESET 10. CLK (Clock Input) 11. Vcc 12. GND 13. MN/ MX(BAR)1.

PINS FOR MINIMUM MODE ONLY1. M/IO (BAR) 2. INTA(BAR) 3. ALE 4. DT/R (BAR) 5. DEN (BAR) 6. HOLD 7. HLDA

PINS FOR MAXIMUM MODE ONLY1. S0(BAR) 2. S1(BAR) 3. S2(BAR) 4. LOCK (BAR) 5. QS1 6. QS0 7. RQ(BAR)/GT1(BAR) 8. RQ(BAR)/GT0(BAR)

INSTRUCTIONS OF 80861. Data copy Instructions 2. Arithmetic Instructions 3. Logical Instructions 4. Arithmetic Adjust Instructions 5. String Instructions 6. Branch Instructions 7. Machine Control Instructions 8. Instructions Related to Stack

DATA COPY INSTRUCTIONS1. MOV operand1, operand2 2. XCHG operand1, operand2 3. LAHF 4. SAHF 5. IN accumulator, port 6. OUT port, accumulator 7. LEA operand, memory variable 8. LDS operand 1, operand2 9. LES operand1, operand2

ARITHMETIC INSTRUCTIONS1. ADD operand1, operand2 2. ADC operand1, operand2 3. SUB operand1, operand2 4. SBB operand1, operand2 5. INC operand 6. DEC operand 7. NEG operand 8. CMP operand1, operand2 9. MUL operand 10. IMUL operand 11. DIV operand 12. IDIV operand

LOGICAL INSTRUCTIONS1. AND operand1, operand2 2. OR operand1, operand2 3. XOR operand1, operand2 4. TEST operand1, operand2 5. NOT operand 6. SAL/SHL operand, count 7. SAR operand, count 8. SHR operand, count 9. RCL operand, count 10. RCR operand, count 11. ROL operand, count 12. ROR operand, count

ARITHMETIC ADJUST INSTRUCTIONS1. DAA (Decimal Adjust Accumulator after addition) 2. DAS (Decimal Adjust Accumulator after Subtraction) 3. AAA (ASCII Adjust Accumulator after Addition) 4. AAS (ASCII Adjust Accumulator after Subtraction) 5. AAM (ASCII Adjust Accumulator after Multiplication) 6. AAD (ASCII Adjust Accumulator after Division) 7. CBW ( Converts byte data into word data by extending the sign bit in AL into AH) 8. CWD ( Converts word data into double word data by extending the sign bit in AX into DX)

STRING INSTRUCTIONS1. STOSB 2. STOSW 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. STOS offset LODSB LODSW LODS offset MOVSB MOVSW MOV offset1, offset2 SCASB SCASW SCAS offset CMPSB CMPSW CMPS offset

BRANCH INSTRUCTIONS1. Jump Instructions ( Near jump, Far jump, unconditional jump, Conditional jump 2. Loop Instructions (LOOP label) 3. Call and Return Instructions (LOOPNE/LOOPNZ short target) 4. Software Interrupt Instructions ( INT n)

MACHINE CONTROL INSTRUCTIONS1. STC (Set carry flag) 2. CLC (Clear Carry Flag) 3. HLT (Halt the program execution) 4. NOP (No Operation) 5. WAIT (Check the Test Signal) 6. LOCK (Prefix before any instruction) 7. CLC (Clear carry Flag) 8. STD (Set Direction Flag) 9. CLD (Clear Direction Flag) 10.STI (Set Interrupt Flag)

INSTRUCTIONS RELATED TO STACK

1.PUSH operand 2.POP operand 3.PUSHF 4.POPF