8515 Service Ma8515 service manuanual (1)

SERVICE MANUAL FORSERVICE MANUAL FOR

85158515

BY: Guangna ZhangTechnical Maintenance Department/GTK MTC

Oct.2007/R02

85158515 N/B MaintenanceN/B Maintenance

1

Contents

1. Hardware Engineering Specification …………………………………………………………………….1.1 Introduction ………………………………………………………………………………………………………………

1.2 System Hardware Parts ………………………………………………………………………..…………………….….

1.3 Other Functions ………………………………………………………………………………………..………………...

1.4 Peripheral Components …………………………………………………………………………………………………

1.5 Power Management ………………………………………………………………...……………………………………

2. System View and Disassembly …………………………………………………………………………....2.1 System View ………………………………………………………………………………………………………………

2.2 Tools Introduction …………………………………………………………………………………………………..……

2.3 System Disassembly ………………………………………………………………………………………………………

3. Definition & Location of Connectors/Switches ………………………………………………………….3.1 Mother Board ………………………………………………………………………………………………….................

4. Definition & Location of Major Components …………………………………………………………...4.1 Mother Board …………………………………………………………………………………………………................

5. Pin Description of Major Component …….……………………………………………………………..5.1 Intel Merom Processor CPU ………………………………………………………………….…………………………

5.2 VIA VN896 North Bridge ………………………………………………………………………..………………………

5.3 VIA VT8237A South Bridge …………………………………………………………………………………………….

3

3

5

39

45

50

54

72

47

74

53

72

50

76

81

74

76

85

MiTac Secret

Confidentia

l Docum

ent


2

6. System Block Diagram …………………………………………………………………………………….

7. Trouble Shooting ………………………………………………………………………………………….7.1 No Power …………………………………………………………………………………………………………….……

7.2 No Display ………………………………………………………………………………………………………………..

7.3 Graphics Controller Test Error LCD No Display ……………………………………………....………….………….

7.4 External Monitor No Display ……………………………………………………………………………………………

7.5 Memory Test Error ……………………………………………………………………………………………..………..

7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error ………………………………………………………………….…...

7.7 Hard Disk Drive Test Error …………………………………………………………………………………………….

7.8 ODD Drive Test Error …………………………………………………………………………………………….……..

7.9 USB Port Test Error …………………………………………………………………………………………………..…

7.10 Audio Test Error ………………………………………………………………………………………………………..

7.11 LAN Test Error …………………………………………………………………………………………….………..….

7.12 Mini Express (Wireless) Socket Test Error …………………………………………….………………….………….

7.13 Express Card Socket Test Error ………………………………………………………………….……………...…….

8. Reference Material …………………………………………………………………………………………

Contents

104

112

119

115

117

93

108

110

122

124

101

94

96

128

126

106

MiTac Secret

Confidentia

l Docum

ent


3

1. Hardware Engineer Specification

1.1 Introduction

The 8515 motherboard implements CORE 2 DUO processor for mobile, 667 MT/s (667 MHz) and 800 MT/s (800 MHz) FSB support. 478-pin Micro-FCPGA packages.

8515 platform implements VN896CE/VT8237A core logic. The VN896CE integrates VIA’s most advanced system controller with high-performance UniChrome Pro 3D/2D graphics and video controller, LCD panel and TV-Out interfaces. The VN896 provides superior performance between the CPU, PCIe, DRAM, V-link and internal AGP 8x graphics controller with pipelined, burst and concurrent operation.

The VN896CE supports 800/667 MHz FSB Intel Pentium M/Merom super-scalar processors. The VN896CE implements a deep In-Order Queue and supports Intel Hyper-Threading Technology to maximize system performance for multithreaded software applications. The VN896 supports 64-bit memory data bus access and up to 2 double-sided DDR2 667 / 533 for 4 GB maximum physical memory. The VN896CE includes a PCI Express 1.0a compliant PCI Express controller, which supports up to two high bandwidth PCIe ports. A 16-Lane port, with up to 4 GB/sec bi-directional data transfer rate, is implemented to support high-end PCI Express compliant graphics controller, and another 1-Lane port designed for PCIe peripheral devices. The VN896CE North Bridge interfaces to the South Bridge through a high speed (up to 533 MB/sec) 8x 66 MHz Data Transfer interconnect bus called V-link interface.

MiTac Secret

Confidentia

l Docum

ent


4

The VT8237A integrates extensive peripheral controllers for modern, state-of-the-art PC systems:

Dual-channel serial ATA/RAID controllerDual-channel enhanced IDE controllerIEEE 802.3 compliant 10/100 Mbps Ethernet MAC with MII interface to external PHY receiverUniversal serial bus controller with eight USB 2.0 portsFull System Management Bus (SMBus) interfaceKeyboard controller with PS/2 mouse supportReal time clock with 256 bytes extended CMOSPower management unit compliant with ACPI and legacy APM requirementsPlug and play functions with steerable PCI interrupts

User expendable peripheral interface built on 8515 system are 4 USB ports. 8515 system provides a New card/Express card and Mini PCI-E card. User interface includes internal keyboard, touch pad. Realtek ALC268 High Definition (Azalia) Audio Codec based multimedia interface includes built-in stereo speaker, Microphone-in and headphone-out audio jacks. There are two communication VIA VT6103L Ethernet PHY to support RJ-45 LAN jack and Modem module to support Modem RJ11 jack.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Vista and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering IDE, plug and play, Advanced Configuration Power Interface (ACPI) with application restart, software-controlled power shutdown.

Following chapters will have more detail description for each individual sub-systems and functions.

MiTac Secret

Confidentia

l Docum

ent


5

1.2 System Hardware Parts

CPU Mobile Merom Celeron/Pentium M CPUThermal spec 35 W TDP

Core Logic VIA VN896CE + 8237A chipsetSystem BIOS Phoenix BIOS

512 KB flash EPROMInclude system BIOSPlug & play capabilityACPI

Memory 0 MB DDRII 533 SDRAM memory on board2 memory SO-DIMM slots for memory expansion1.25-inch height memory module supported200 pins DDRII 533 SDRAM SO-DIMM memory moduleSupport 2048 MB

HDD Support 2.5" 60 GB/80 GB/100 GB/120 GB HDD (9.5 mm) 5400/7200 rpm, PATA, SATA I/F

ODD Combo/DVD-Dual, super multi (12.7 mm)Display 15.4" WXGA, resolution: 1280x800Clock Generator ICS 953009 and DDRⅡ buffer ICS 9P956, LVDS ICS MK1707VGA Control Internal VIA VN896CELVDS Transmitter VIA VT1637LAN VIA VT6103LExpress Card Power switch TPS2231Audio System Built-in sound system

Azalia I/F (HD Audio codec, ALC268)Built-in stereo speakerSound volume control by S/W2 CH

MiTac Secret

Confidentia

l Docum

ent


6

Continue to previous page

Modem 6 Kbps (V.92) fax modem (MDC (Azalia I/F)) and 10/100 (Reserved for 1000)Base-TX LAN

Wireless LAN Wireless LAN Intel (Mini PCI-E Interface IEEE802.11 b, g)Keyboard Controller (CIR) WINBOND W83L951DUSB USB2.0 x4 (Individual)

MiTac Secret

Confidentia

l Docum

ent


7

1.2.1 CPU Mobile Intel Merom CPU Processor

1.2.1.1 Mobile Intel Merom CPU Processor

• CORE 2 DUO processor for mobile

• 667 MT/s (667 MHz) and 800 MT/s (800 MHz) FSB support

• On-die, 2-MB second level cache with advanced transfer cache architecture shared between the two cores

• Advance gunning transceiver logic (AGTL +) bus driver technology

• Enhanced Intel speed step technology to enable real-time dynamic switching between multiple voltage and frequency points

• Source synchronous double-pumped (2×) address

• Source synchronous quad-pumped (4×) data

• Other key feature are:

Processor support

Support for DBI (Data Bus Invor ersion)

Support for MSI (Message signaled interrupt)

MiTac Secret

Confidentia

l Docum

ent


8

32-bit interface to address up to 4 GB of memory

A12 deep In-Order Queue to pipeline FSB commands

AGTL+ bus driver with integrated AGLT termination resist

478-pin Micro-FCPGA and 49-ball Micro-FCBGA packages

VCCA 1.5 V

VCCP 1.05 V

Merom based Intel Pentium M Processor Feature

• On-die 1 MB second level cache with advance transfer cache architecture shared between the two cores

• 478-pin Micro-FCPGA packages

• VCCA 1.5 V

• VCCP 1.05 V

MiTac Secret

Confidentia

l Docum

ent


9

1.2.2 Clock Generator

1.2.2.1 ICS 953009 System Frequency Synthesizer

• VIA VN896CE systems using Intel Merom processors

Recommended Application

• 2 – 0.7 V current-mode differential CPU pairs

• 1 – 0.7 V current-mode differential CPU/PCI-Express selectable pair

• 7 – PCI, 33 MHz

• 2 – REF, 14.318 MHz

• 3 – 3 V66, 66.66 MHz

• 1 – 48 MHz

• 1 – 24/48 MHz

• 5 – PCI-Express 0.7 V current mode differential pairs

Output Features

MiTac Secret

Confidentia

l Docum

ent


10

• Programmable output frequency

• Programmable asynchronous 3 V66&PCI frequency

• Programmable asynchronous PCI-Express frequency

• Programmable output divider ratios

• Programmable output skew

• Programmable spread percentage for EMI control

• Watchdog timer technology to reset system if system malfunctions

• Programmable watch dog safe frequency

• Support I2C index read/write and block read/write operations

• Uses external 14.318 MHz reference input, external crystal load caps are required for frequency tuning

Features/Benefits

MiTac Secret

Confidentia

l Docum

ent


11

1.2.2.2 DDR II Buffer ICS 9P956 System Frequency Synthesizer

Low skew, fanout buffer

I2C for functional and output control

Single bank 1-6 differential clock distribution

1 pair of differential feedback pins for input to output synchronization

Supports up to 2 DDR DIMMs

667 MHz DDR II output frequency support

Switching characteristics

• Output – Output skew: <100 ps

• Output rise and fall time for DDR outputs: 650 ps – 950 ps

• Duty cycle: 47% - 53%

MiTac Secret

Confidentia

l Docum

ent


12

1.2.2.3 VIA VN896CE North Bridge

Defines highly integrated solutions for value notebook PC designs

• High performance UMA north bridge: Integrated VIA C7 and Intel Pentium M north bridge with 800 / 667/ 533 / 400 MHz FSB support. PCI express bus controller and UniChrome Pro 3D / 2D graphics & video controllers in a single chip

• Advanced 64-bit SDRAM controller supporting DDR2 667/533 and DDR 400/333/266/200 SDRAM

• Combines with VIA VT8237A/VT8237R plus for 10/100 LAN, ATA133 IDE, LPC, USB 2.0, serial ATA and high definition audio (VT8237A)

• 37.5x37.5 mm HSBGA package (Ball grid array with heat spreader) with 952 balls and 1.00 mm ball pitch

CPU interface

• Supports 800/667/533/400 MHz FSB VIA C7 and Intel Pentium M processors

• Supports Intel hyper-threading technology

• Supports DBI (Dynamic Bus Inversion)

• Supports trust configuration cycle

• Deep In-order Command Queue (IOQ)

• Integrated CPU-to-DRAM write buffers and CPU-to-DRAM read prefetch buffers

MiTac Secret

Confidentia

l Docum

ent


13

Memory interface

• Built-in phase lock loop circuitry for optimal skew control within and between clocking regions

• Supports DDR2 mode

• Supports DDR2 667/533 memory

• Supports mixed 64/128/256/512/1024/2048x8/16 DDR2 SDRAMs

• Supports 2 unbuffered double-sided DIMMs and up to 4 GB of physical memory

• Supports CL 2/3/4/5 for DDR2 667/533

• Programmable I/O drive capability for memory address, data and control signals

• DRAM interface pseudo-synchronous with host CPU for optimal memory performance

• Concurrent CPU, PCIe, internal graphics controller and V-link access for minimum memory access latency

• Rank interleave and up to16-bank page interleave (i.e., 16 pages open simultaneously) based on LRU to effectively reduce memory access latency

• Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank)

• CPU read-around-write capability for non-stalled operation

MiTac Secret

Confidentia

l Docum

ent


14

• Speculative DRAM read before snoop result to reduce PCI master memory read latency

• Supports Burst Read and Write operations with burst length of 4 or 8

• Optional dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0)

• Supports self-refresh and CAS-before-RAS DRAM refresh with staggered RAS timing

Advanced High Bandwidth PCI Express Interface

• Supports PCI express 1.0a

• Supports up to two PCI express ports

1st port: A 16-Lane port for high end graphics interface. Configurable lane width, 16/8/4/2/1, through hand-shaking for transfer rate up to 4 GB/sec bi-directional

Supports two upstream virtual channels

2nd port: A 1-Lane port for peripheral devices

• Supports interconnect power management

• Supports polarity reversal

• Supports trust configuration cycle

• Supports hot plug

MiTac Secret

Confidentia

l Docum

ent


15

• Loop-back testing mode for easy debugging mode for PCI express

High bandwidth 533 MB/sec 8-bit V-link host controller

• Supports 66 MHz, 4x and 8x transfer modes, V-link interface with 533 MB/sec total bandwidth

• Half duplex transfers with separate command/strobe for 4x 8-bit mode and full duplex for 8x 4-bit mode

• Request/data split-transaction

• Transaction assurance for V-link host-to-client access eliminates V-link host-client retry cycles

• Intelligent V-link transaction protocol to minimize data wait-state and throttle transfer latency to avoid dataoverflow

• Highly efficient V-link arbitration with minimum overhead

Integrated graphics with 2D/3D/video controllers

• Optimized Unified Memory Architecture (UMA)

• Supports 16/32/64 MB frame buffers size

• Graphics engine clocks up to 333 MHz decoupled from memory clock

• Internal AGP 8x performance

MiTac Secret

Confidentia

l Docum

ent


16

• Two 128-bit internal data paths between north bridge and graphics core for frame buffer and texture/commandaccess

2D acceleration features

• 128-bit 2D graphics engine

• Supports ROP3, 256 operations

• Supports 8 bpp, 15/16 bpp and 32 bpp color depth modes

• BitBLT (Bit Block Transfer) functions including alpha BLTs

• Color expansion, source color key and destination color key

• Bresenham line drawing/style line function

• Transparency mode

3D acceleration features

• 3D graphics processor

- 128-bit 3D graphics engine

- Dual pixel rendering pipes

- Dual texture units

MiTac Secret

Confidentia

l Docum

ent


17

- Floating-point setup engine

- Internal full 32-bit ARGB format for high rendering quality

- 8 K texture cache

- Linear address

• Capability

- Supports ROP2

- Supports various texture formats, including: 16/32 bbp ARGB, 8 bbp palletized (ARGB), YUV 422/420 and compressed texture (DXTC)

- Texture sizes up to 2048x2048

- High quality texture filter for Nearest, Linear, bi-linear, tri-linear and anisotropic modes

- Flat and gouraud shading

- Vertex fog and fog table

- Z-Bias, LOD-Bias, polygon offset, edge anti-aliasing and alpha blending

- Bump mapping and cubic mapping

- Hardware back-face culling

MiTac Secret

Confidentia

l Docum

ent


18

- Specular Lighting

- 16/32-bit Z test and 24+8 Z+ stencil test support

• Performance

- Two textures per pass

- Triangle rate up to 4.5 million polygons per second

- Pixel rate up to 400 million pixels per second for 2 textures each

- Texel bilinear fill rate up to 266 million texels per second

- High quality dithering

Extensive display support for external video output

• A dedicated CRT interface

• Supports three 12-bit digital video ports

- Multiplexed DVP0 and DVP1 for LVDS transmitter

- Dedicated DVP2 for TV encoder

• CRT display

MiTac Secret

Confidentia

l Docum

ent


19

- CRT display interface with 24-bit true-color RAMDAC up to 300 MHz pixel rate with gamma correctioncapability

- Supports CRT resolutions up to 2048x1536 at 75 Hz

• 12-bit DDR/18-bit/24-bit LVDS transmitter interface for LCD panel

- 12-bit DDR and clock rate up to 165 MHz

- Built-in digital phase adjuster to fine tune signal timing between clock and data bus

Advanced system power management support

• ACPI 2.0 and PCI bus power management 1.1 compliant

• Supports suspend-to-DRAM (STR) and DRAM self refresh

• Supports dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0)

• Supports SMI, SMM and STPCLK mechanisms

• Supports enhanced Intel Speedstep technology

• Low-leakage I/O pads

Advanced graphics power management support

MiTac Secret

Confidentia

l Docum

ent


20

• Built-in reference voltage generator and monitor sense circuits

• Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-down

• External I/O signal controlling enabling graphics accelerator into standby/suspend-off state

• Auto clock gating for each engine to achieve power saving

• I2C serial bus and DDC monitor communications for CRT plug-and-play configuration

1.2.2.4 VIA VT8237A South Bridge

High bandwidth 1 GB/sec ultra V-link controller

• Supports 16-bit, 66 MHz, 4x and 8x transfer modes, Ultra V-link interface with 1 GB/sec maximum bandwidth

• Full duplex, with separate 8-bit Up and Down data path and command/strobe, in 8x mode

• Half duplex, with 16-bit data bus, in 4x mode

• Request/data split transaction

• Transaction assurance for V-link host to client access eliminates V-link host-client retry cycles

• Intelligent V-link transaction protocol to minimize data wait-state, throttle transfer latency to avoid data overflow

• Highly efficient V-link arbitration with minimum overhead

MiTac Secret

Confidentia

l Docum

ent


21

Dual channel serial ATA/RAID controller

• Complies with serial ATA specification revision 1.0

• Dual Channel master mode PCI

• On-chip two-channel Serial ATA (S-ATA) PHY for support of up to two S-ATA devices directly

• S-ATA devices can be configured in multiple RAID configurations – supports RAID Level 0, RAID Level 1 and JBOD

• S-ATA drive transfer rate is capable of up to 150 MB/s per channel (serial speed of 1.5 Gbit/s)

• External crystal input for serial ATA port operation

• Supports defer spin up and port multiplier

High definition (HD) audio controller

• High definition audio controller with 192 KHz sample rate, 24-bit per sample and up to 8 channels

• Microsoft UAA (Universal Audio Architecture) driver support

• Up to four independent playback streams and audio codecs

• Multiple recording channels for array microphone

• Supports jack sensing/retasking

MiTac Secret

Confidentia

l Docum

ent


22

Universal serial bus controller

• Eight USB 2.0 ports with integrated PHY

• One USB 2.0 root hub and four USB 1.1 root hubs

• USB 2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compliant

• USB 1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible

• Integrated physical layer transceivers with optional over-current detection status on USB inputs

• Eighteen level (doublewords) data FIFO with full scatter and gather capability

• Legacy keyboard and PS/2 mouse support

• One USB 2.0 debug port

Fast Ethernet controller

• High performance PCI master interface with scatter/gather and bursting capability

• Standard MII interface to external PHYceiver

• 1/10/100 MHz full and half duplex operation

• Independent 2 K byte FIFOs for receive and transmit

MiTac Secret

Confidentia

l Docum

ent


23

• Flexible dynamically loadable EEPROM algorithm

• Physical, broadcast, and multicast address filtering using hashing function

• Magic packet and wake-on-address filtering

• Software controllable power down

Ultra DMA-133/100/66/33 bus master EIDE controller

• Dual channel hard disk controller supporting up to four enhanced IDE devices

• Data transfer rate up to 133 MB/sec to cover PIO mode 4, multi-word DMA mode 2 and UltraDMA-133 interface

• Dual DMA engines for concurrent dual channel operation

• Full scatter gather capability

• Supports ATAPI compliant devices including DVD devices

• Supports PCI native and ATA compatibility modes

• Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant

• Complete software driver support

MiTac Secret

Confidentia

l Docum

ent


24

System management bus interface

• Compliant with System Management Bus (SMBus) revision 2.0

• I2C devices compatible

• Supports SMBus Address Resolution Protocol (ARP) by using host commands through software

• Supports slave interface for external SMBus masters to control resume events

• Supports alert on LAN II through a SMBus-interfaced register

Sophisticated mobile power management

• ACPI 2.0 and APM v1.2 Compliant

• Supports On Now power management

• Supports Intel enhanced SpeedstepTM with dedicated pins

• Supports PCI Express WAKE suspend resume event

• Supports CPU clock throttling and clock stop during ACPI C0 / C1 / C2 / C3 states

• Supports PCI clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control

• Supports multiple system suspend types: power-on suspends (POS) with flexible CPU/PCI bus reset options,suspend to DRAM (STR), and suspend to disk (soft-off), all with hardware automatic wake-up

MiTac Secret

Confidentia

l Docum

ent


25

• Multiple suspend power plane controls and suspend status indicators

• Integrates an idle timer, a peripheral timer and a general purpose timer, plus a 24/32-bit ACPI compliant timer

• Supports normal, doze, sleep, suspend and conserve modes

• Global and local device power control

• Supports system event monitoring with two event classes

• Primary and secondary interrupt differentiation for individual channels

• Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for system wake-up

• 32 general purpose input ports and 32 output ports

• Multiple internal and external SMI sources for flexible power management models

• Enhanced integrated Real Time Clock (RTC) with date alarm, month alarm, and century field

• Thermal alarm on external temperature sensing circuit

• I/O pad leakage control

Plug and play functions

MiTac Secret

Confidentia

l Docum

ent


26

• Steerable PCI interrupts

• Steerable interrupts for integrated peripheral controllers

• Microsoft Windows XPTM, Windows NTTM, Windows 2000TM, Windows 98TM and plug and play BIOS compliant

Integrated legacy functions

• Integrated keyboard controller with PS2 mouse support

• Integrated DS12885-style real time clock with extended 256 bytes CMOS RAM and day/month alarm for ACPI

• Integrated DMA, timer, and interrupt controller

• Serial IRQ for docking and non-docking applications

• Fast reset and gate A20 operation

MiTac Secret

Confidentia

l Docum

ent


27

1.2.3 VT1637 LVDS Transmitter

Supports single/dual LVDS transmitter function

Compatible with TIA/EIA-644 LVDS standard

Supports LVDS 18-bit Output

Supports dual channel UXGA panel display

Supports 2D dither for 18-bit Panel

Supports DVO input mode with 25 to 165 MHz input clock

Programmable input clock and strobe select

Narrow bus reduces cable size and cost

PLL requires no external components

2.5 V core power for low power consumption

48-pin LQFP package (7x7x1.4 mm)

Available for lead-free package

MiTac Secret

Confidentia

l Docum

ent


28

1.2.4 TI TPS2231 Single-Slot PC Card Power Interface Switch

Meets the express card™ standard (Express card 34 or express card 54)

Available in a 32-pin power PAD™ HTSSOP (Dual)

Compliant with the express card™ compliance checklists

– 40°C to 85°C ambient operating temperature range

Available in a 20-pin TSSOP, a 20-pin QFN, or 24-pin power PAD™ HTSSOP (Single)

Fully Satisfies the express card™ implementation guidelines

Supports systems with wake function

TTL-logic compatible inputs

Short circuit and thermal protection

1.2.5 Realtek ALC268 High Definition Audio System

Single-chip multi-bit sigma-delta converters with high S/N ratio

1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192 KHz sample rate

MiTac Secret

Confidentia

l Docum

ent


29

2 stereo ADCs support 16/20-bit PCM format with 44.1/48/96 KHz sample rate

Applicable for 2-channel 192 KHz DVD-audio solutions

Line-out, HP-out, Line 1, Line 2, MIC1, and MIC2 are stereo input and output re-tasking

MONO line level output to subwoofer speaker for 2.1 channel applications

High-quality differential CD analog input

External PCBEEP input is applicable, and internal BEEP generator is integrated

Power-off CD mode supported (Only in ALC268 & ALC268-LF)

Power management and enhanced power saving features

Power support: digital: 3.3 V; analog: 3.8 V/5.0 V

Selectable 2.5 V/3.75 V VREFOUT

Two jack detection pins (Each designed to detect 4 jacks)

Supports 44.1/48/96/192 KHz S/PDIF output

Supports 44.1/48/96 KHz S/PDIF input

48-pin LQFP packages (lead (Pb)-free packages also available)

MiTac Secret

Confidentia

l Docum

ent


30

Supports external volume knob control

External PCBEEP Pass-Through when link is in RESET state (Not supported in the ALC268(D)-VE andALC268(D)-VE-LF)

–64 dB ~ +30 dB with 1 dB mixer gain resolution for finer volume control

Impedance sensing capability for each re-tasking jack

Built-in headphone amplifier for each re-tasking jack

Supports external volume knob control

Supports GPIO (General Purpose Input/Output) for customized applications

1.2.6 ANPEC APA2056 Audio Power Amplifier

Compatible with PC 99 desktop line-out Into 10-KW load

Internal gain control, which eliminates external gain-setting resistors

2-W/Ch output power Into 3-W load

Input MUX select terminal

PC-beep input

MiTac Secret

Confidentia

l Docum

ent


31

Depop circuitry

Stereo input MUX

Fully differential input

Low supply current and shutdown current

Surface-mount power packaging 24-Pin TSSOP power PAD

1.2.7 Keyboard System – Winbond W83L951D Universal Keyboard Controller

Core logic

• 8-bit turbo 8052 microprocessor code based, speed up to 24 MHz

• 256 bytes Internal RAM

• 64 K bytes embedded programmable flash memory

• 2 K bytes external SRAM

Host interface

• Software optional with LPC interface

• Primary programmable I/O address communication port in LPC mode

MiTac Secret

Confidentia

l Docum

ent


32

SMBus

• Support 2 SMBus interface support master mode

Timers

• Support four timer signal with three pre-scalars

• Timer 1 and 2 shard the same pre-scalar and are free-running only

• Timer X and Y have individual pre-scalar and support up to four control modes, free. Running, pulse output, event counter and pulse width measurement

PWM

• Support four PWM channels

• PWM 0 and 1 are 8-bits and programmable frequency from 62 Hz to 7.5 KHz

• PWM 2 and 3 are 16-bits and programmable frequency from 6 Hz to 3 MHz

Fan Tachometer

• Support two fan tachometer input

A/D converter

• Firmware programmable optional with 10-bit or 8-bit resolution

MiTac Secret

Confidentia

l Docum

ent


33

D/A converter

• Support eight channels

• 8-bit resolution

• Support two channels

PS2

• Support three hardware PS2 channels

• Optional PS2 clock inhibit by hardware or firmware

Keyboard controller

• Support 16*8 keyboard matrix-scan, expanding to 18*8 and 20*8

GPIO

• Support 104 useful GPIO pins totally and bit–addressable to facility firmware coding

Flash

• Support external on-board 64 K flash via matrix interface (GP0, 1, 3)

CIR

MiTac Secret

Confidentia

l Docum

ent


34

RTC

• Support decoding for the NEC consumer IR remote control format

• Real time clock generator with 32.768 KHz input

ACPI

• Support ACPI appliance

• Secondary programmable I/O address communication port in LPC mode

Package

• 128 pin QFP and 128 pin LQFP package options

1.2.8 System Flash Memory (BIOS) – SST49LF004B

512 K x 8 (4 Mbit)

Flexible erase capability

• Uniform 4 KByte sectors

• Uniform 64 KByte overlay blocks

• Chip-erase for PP mode only

MiTac Secret

Confidentia

l Docum

ent


35

Single 3.0-3.6 V read and write operations

• Real time clock generator with 32.768 KHz input

Superior reliability

• Endurance: 100,000 cycles (typical)

• Greater than 100 years data retention

Low power consumption

• Active read current: 6 mA (typical)

• Standby current: 10 µA (typical)

Fast sector-erase/byte-program operation

• Sector-erase time: 18 ms (typical)

• Block-erase time: 18 ms (typical)

• Chip-erase time: 70 ms (typical)

• Byte-program time: 14 µs (typical)

• Chip rewrite time: 8 seconds (typical)

MiTac Secret

Confidentia

l Docum

ent


36

Two operational modes

• Low Pin Count (LPC) interface mode forin-system operation

• Parallel Programming (PP) mode for fast production programming

LPC interface mode

• 5-signal LPC bus interface supporting byte read and write

• 33 MHz clock frequency operation

• WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block

• Block locking registers for individual block write-lock and lock-down protection

• JEDEC standard SDP command set

• Data# polling and toggle bit for end-of-write detection

• 5 GPI pins for system design flexibility

• 4 ID pins for multi-chip selection

Parallel Programming (PP) mode

• 11-pin multiplexed address and 8-pin data I/O interface

MiTac Secret

Confidentia

l Docum

ent


37

• Supports fast programming in-system on programmer equipment

CMOS and PCI I/O compatibility

1.2.9 VIA VT6103L 10Base – T/100Base – TX Integrated Ethernet LANPHY/Transceiver

Single chip 100Base -TX/10Base -T physical layer solution

Dual speed – 100/10 Mbps

Half and full duplex

MII interface to Ethernet controller

MII Interface to Configuration & Status

Auto power saving mode

Auto negotiation: 10/100, full/half duplex

Meet all applicable IEEE 802.3, 10Base -T and 100Base -Tx standards

On chip wave shaping – no external filters required

Adaptive equalizer

MiTac Secret

Confidentia

l Docum

ent


38

Baseline wander correction

LED outputs

• Link status

• Duplex status

• Speed status

• Collision

48 pin SSOP package

MiTac Secret

Confidentia

l Docum

ent


39

1.3 Other Functions

1.3.1 Hot Key Function

KeysCombination Feature Meaning

Fn + F1 Wireless LAN on/off Enable or disable wireless LAN functionFn + F2Fn + F3 Volume down Audio volume downFn + F4 Volume up Audio volume upFn + F5 LCD/external CRT switching Rotate display mode in LCD only, CRT only

and simultaneously displayFn + F6 Brightness down Decreases the LCD brightnessFn + F7 Brightness up Increases the LCD brightnessFn + F8Fn + F9

Fn + F10 Mute off/on Toggle mute on/offFn + F11 Panel off/on Toggle panel on/offFn + F12 Suspend to DRAM/HDD Force the computer into either suspend to HDD or

suspend to DRAM mode depending on BIOS setup

1.3.2 Quick Key Function

Internet, e-mail, P1

MiTac Secret

Confidentia

l Docum

ent


40

1.3.3 Power on/off/suspend/resume Button

1.3.3.1 APM Mode

At APM mode, power button is on/off system power

1.3.3.2 ACPI Mode

At ACPI mode, windows power management control panel set power button behavior. You could set "standby", "power off“ or "hibernate” (Must enable hibernate function in power management) to power button function.

Continue pushing power button over 4 seconds will force system off at ACPI mode

1.3.4 Cover Switch

System automatically provides power saving by monitoring cover switch. It will save battery power and prolongthe usage time when user closes the notebook cover

At ACPI mode there are three functions to be chosen at windows XP power management control panel

• None

• Standby

MiTac Secret

Confidentia

l Docum

ent


41

• Off

• Hibernate (Must enable hibernate function in power management)

1.3.5 LED Indicators

1.3.5.1 Six LED Indicators Above Keyboard

System has six status LED indicators to display system activity, which include six above keyboard

From left to right that indicates WLAN, power status, battery charge status, caps lock status, num lock status, HDD/ODD status

WLAN power status

• On: WLAN power on

• Off: WLAN power off

Power status

• On: System power on

• Off: Suspend to RAM power management mode (Flash rate: 1 Hz)

MiTac Secret

Confidentia

l Docum

ent


42

• Off: System power off

Battery charge status

• Green: Battery was fully charged (AC mode)

• Orange: Battery was under charging (AC mode)

• Red (Flash): Battery low (Under 10%, battery mode, flash rate: 1 Hz)

CAPS lock status

• Green: Active state

NUM lock status

• Green: Active state

HDD/ODD status

• The LED light green when HDD or ODD is working

MiTac Secret

Confidentia

l Docum

ent


43

1.3.6 Battery Status

1.3.6.1 Battery Warning

System also provides battery capacity monitoring and gives user a warning so that users have chance to save hisdata before battery dead. Also, this function protects system from mal-function while battery capacity is low

Battery warning: Capacity below 10%, battery capacity LED flashes per second, system beeps per 2 seconds

System will suspend to HDD after 2 minutes to protect users data

1.3.6.2 Battery Low State

After battery warning state, and battery capacity is below 5%, system will generate beep sound for twice per second

1.3.6.3 Battery Dead State

When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the battery packs' life

MiTac Secret

Confidentia

l Docum

ent


44

1.3.7 Fan Power on/off Management

1.3.7.1 CPU Fan

FAN is controlled by W83L951D embedded controller-using ADM1032 to sense CPU temperature andW83L951D PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature willget faster fan speed

1.3.8 CMOS Battery

There is a standard CR2032 3 V 220 mAh lithium coin battery to supply RTC power. When AC in or system main battery inside, CMOS battery consumes no power to save coin battery’s life cycle

MiTac Secret

Confidentia

l Docum

ent


45

1.4 Peripheral Components

1.4.1 LCD Panel

15.4" WXGA, resolution: 1280x800

1.4.2 HDD

Support 2.5" 60 GB/80 GB/100 GB/120 GB HDD (9.5 mm) 5400/7200 rpm, PATA, SATA I/F

1.4.3 ODD

Combo/DVD-dual, super multi (12.7 mm)

1.4.4 DDR SO - DIMM

0 MB DDRII 533 SDRAM memory on board

2 memory SO- DIMM slots for memory expansion

200 pins DDRII 533 SDRAM SO-DIMM memory module

MiTac Secret

Confidentia

l Docum

ent


46

1.4.5 Keyboard

European keyboard layout

19 mm key pitch/3 mm stroke

MiTac Secret

Confidentia

l Docum

ent


47

1.5 Power Management

1.5.1 System Management Mode

The 8515 system has built in several power saving modes to prolong the battery usage. User can enable and configure different degrees of power management modes via ROM CMOS setup (Booting by pressing F2 key). Following are the descriptions of the power management modes supported

Full on mode

• In this mode, each device is running with the maximal speed. CPU clock is up to its maximum

Doze Mode

• In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode

Standby Mode

• For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device

- CPU: Stop grant

MiTac Secret

Confidentia

l Docum

ent


48

- LCD: Backlight off

- HDD: Spin down

Suspend to DRAM

• The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device

- CPU: Off

- Twister K: Partial off

- VGA: Suspend

- PCMCIA: Suspend

- Audio: Off

- SDRAM: Self refresh

Suspend to HDD

• All devices are stopped clock and power-down. System status is saved in HDD. All system status will be restored when powered on again

MiTac Secret

Confidentia

l Docum

ent


49

1.5.2 Battery Only Power off Mode

The 8515 system has built in battery only power off mode to prolong the battery usage. In this mode, Universal Keyboard Controller (KBC) will be power off. In addition, the system leakage current shall be less than 0.5 mA,therefore system power consumption is lower in this mode

MiTac Secret

Confidentia

l Docum

ent


50

2.1 System View

2.1.1 Front View

2. System View and Disassembly

2.1.2 Left-side View

Top Cover Latch

○

Ventilation Openings

External MIC Jack

Power Jack

HP Jack

USB Port*1

Express Card Socket

MiTac Secret

Confidentia

l Docum

ent


51

2.1.3 Right-side View

2.1.4 Rear View

ODD Drive

○

Kensington LockRJ-11 Connector

RJ-45 Connector

CRT ConnectorUSB Port*2

USB Port*1

MiTac Secret

Confidentia

l Docum

ent


52

2.1.5 Bottom View

2.1.6 Top-open View

Battery Park

CPU & DDR2 SO-DIMM & Mini Express Card (Wireless) & HDD

LCD Screen

Stereo Speaker SetKeyboard

Mail/Internet/P1 ButtonDevice LED Indicators

Internal MICTouch Pad

Power Button

MiTac Secret

Confidentia

l Docum

ent


53

2.2 Tools Introduction

2 mm

2 mm

Bit Size

#0

Screw Size Tooling Tor. Bit Size

1. M2.0 Auto Screwdriver 2.0-2.5 kg/cm2 #0

2. Auto screw driver for notebook assembly & disassembly.

1. Screw driver with bit size for notebook assembly & disassembly.

MiTac Secret

Confidentia

l Docum

ent


54

2.3 System Disassembly The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power.

Modular Components

LCD Assembly Components

NOTEBOOK

2.3.1 Battery Pack

2.3.2 Keyboard

2.3.3 CPU

2.3.4 DDR2-SDRAM

2.3.5 HDD Module

2.3.6 ODD Drive

2.3.7 LCD ASSY

2.3.8 LCD Panel

2.3.9 Inverter Board

2.3.10 System Board

2.3.11 Modem CardBase Unit Components

MiTac Secret

Confidentia

l Docum

ent


55

1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you heara clicking sound.

1. Carefully put the notebook upside down.2. Take the battery pack out of the compartment ( ). (Figure 2-1)

2.3.1 Battery Pack

Disassembly

Reassembly

Figure 2-1 Remove the battery packMiTac Secret

Confidentia

l Docum

ent


56

2.3.2 Keyboard

Disassembly

1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)2. Remove one screw then push firmly to slide the easy start buttons cover to the right ( ). Then lift the easy start

buttons cover up ( ). (Figure 2-2, Figure 2-3)

Figure 2-2 Remove one screw Figure 2-3 Left the keyboard cover

MiTac Secret

Confidentia

l Docum

ent


57

Figure 2-4 Remove the keyboard

Reassembly

1. Reconnect the keyboard cable and fit the keyboard back into place.2. Replace the keyboard cover and secure with one screw.3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

3. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-4)

MiTac Secret

Confidentia

l Docum

ent


58

2.3.3 CPU

Disassembly

1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)2. Remove four screws fastening the CPU cover. (Figure 2-5)3. Remove three screws that secure the fan, disconnect the fan’s power cord from system board and remove four

screws fastening the heatsink. (Figure 2-6)

Figure 2-5 Remove four screws Figure 2-6 Free the heatsink and fan

MiTac Secret

Confidentia

l Docum

ent


59

Reassembly

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pinsinto the holes. Tighten the screw by a flat screwdriver to locking the CPU.

2. Connect the fan’s power cord to the system board, replace the fan and heatsink, then secure with seven screws.3. Replace the CPU cover and secure with four screws.4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

4. To remove the existing CPU, loosen the screw by a flat screwdriver, upraise the CPU socket to unlock the CPU. (Figure 2-7)

Figure 2-7 Remove the CPUMiTac Secret

Confidentia

l Docum

ent


60

Disassembly

1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)2. Remove four screws fastening the CPU cover. (Refer to section 2.3.3 Disassembly)3. Pull the retaining clips outwards ( ) and remove the SO-DIMM ( ). (Figure 2-8)

2.3.4 DDR2-SDRAM

1. To install the DDR2, match the DDR2's notched part with the socket's projected part and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR2 into position

2. Replace the CPU cover and secure with four screws.3. Replace the battery pack. (See section 2.3.1 Reassembly)

Reassembly

Figure 2-8 Remove the SO-DIMM

MiTac Secret

Confidentia

l Docum

ent


61

2.3.5 HDD Module

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)2. Remove four screws fastening the CPU cover. (Refer to section 2.3.3 Disassembly)3. Remove one screw fastening the HDD, then slide the HDD module out of the compartment. (Figure 2-9)

Figure 2-9 Remove HDD module

MiTac Secret

Confidentia

l Docum

ent


62

4. Remove four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-10)

Reassembly

1. Attach the bracket to hard disk drive and secure with four screws.2. Slide the HDD module into the compartment and secure with one screw.3. Replace the CPU cover and secure with four screws.4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

Figure 2-10 Remove hard disk drive

MiTac Secret

Confidentia

l Docum

ent


63

2.3.6 ODD Drive

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)2. Remove one screw fastening the ODD drive. (Figure 2-11) 3. Insert a small rod, such as a straightened paper clip, into ODD drive’s manual eject hole ( ) and push

firmly to release the tray. Then gently pull out the ODD drive by holding the tray that pops out ( ). (Figure 2-11)

Reassembly

1. Push the ODD drive into the compartment and secure with one screw.2. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

Disassembly

Figure 2-11 Remove the ODD drive

MiTac Secret

Confidentia

l Docum

ent


64

2.3.7 LCD ASSY

Disassembly

1. Remove the battery pack, keyboard. (Refer to sections 2.3.1 and 2.3.2 Disassembly)2. Remove four screws fastening the CPU cover. (Refer to step 2 of section 2.3.3 Disassembly)3. Remove two hinge covers, then carefully put the notebook upside down. (Figure 2-12)4. Remove four screws. (Figure 2-13)

Figure 2-13 Remove four screwsFigure 2-12 Remove the hinge covers

MiTac Secret

Confidentia

l Docum

ent


65

1. Attach the LCD assembly to the base unit and secure with six screws. 2. Reconnect the LCD cable and replace two hinge covers.3. Replace the CPU cover and secure with four screws. (Refer to section 2.3.3)4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)

Reassembly

5. Disconnect LCD cable from the system board. Remove two screws to free the LCD assembly. (Figure 2-14)

Figure 2-14 Free the LCD assembly

MiTac Secret

Confidentia

l Docum

ent


66

2.3.8 LCD Panel

Disassembly

1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.7 Disassembly)2. Remove two screws fastening the LCD cover. (Figure 2-15)3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process

until the cover is completely separated from the housing.4. Remove six screws and disconnect two cables. (Figure 2-16)

Figure 2-15 Remove LCD cover Figure 2-16 Remove six screws anddisconnect two cables

MiTac Secret

Confidentia

l Docum

ent


67

Reassembly

Figure 2-17 Remove four screws Figure 2-18 Free the LCD panel

5. Remove four screws that secure with the LCD bracket. (Figure 2-17)6. Disconnect the LCD cable to free the LCD panel. (Figure 2-18)

1. Reconnect the LCD cable to the LCD panel.2. Attach the LCD panel’s bracket back to LCD panel and secure with four screws. 3. Replace the LCD panel into LCD housing, fasten the LCD panel by six screws.4. Replace the LCD cover and secure with two screws.5. Replace the LCD assembly, keyboard, battery pack. (See sections 2.3.7, 2.3.2 and 2.3.1Reassembly)

MiTac Secret

Confidentia

l Docum

ent


68

2.3.9 Inverter Board

Disassembly

1. Remove the battery, keyboard, LCD assembly and LCD panel. (Refer to section 2.3.1, 2.3.2, 2.3.7 and 2.38Disassembly)

2. Remove three screws and free the inverter board. (Figure 2-19)

Figure 2-19 Remove three screws

Reassembly

1. Fit the inverter board back into place and secure with three screws. 2. Replace the LCD Panel, LCD assembly, keyboard and battery pack. (Refer to sections 2.3.8, 2.3.7, 2.3.2 and 2.3.1

Reassembly)

MiTac Secret

Confidentia

l Docum

ent


69

2.3.10 System Board

Disassembly

1. Remove the battery, keyboard, CPU, DDR2, HDD, ODD drive and LCD assembly.(Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.7 Disassembly)

2. Remove fifteen screws and two hex nuts fastening the housing. (Figure 2-20, Figure 2-21)

Figure 2-21 Free the system board Figure 2-20 Remove fifteen screws

MiTac Secret

Confidentia

l Docum

ent


70

3. Remove two screws and disconnect the two speaker’s cables, then free the system board. (Figure 2-22)

Figure 2-22 Free the system board

Reassembly

1. Replace the system board back into the housing, secure with two screws and reconnect two speaker’s cables.2. Replace the top cover into the housing.3. Secure with fifteen screws and two hex nuts fasten the housing. 4. Replace the LCD assembly, DDR2, ODD, HDD, CPU, keyboard and battery pack. (Refer to previous section

reassembly)

MiTac Secret

Confidentia

l Docum

ent


71

2.3.11 Modem Card

Disassembly

1. Replace the modem card back into the system board and secure with two screws, then reconnect the cable. 2. Replace the system board, the LCD assembly, ODD, HDD, DDR2, CPU, keyboard and battery pack.

(Refer to previous section reassembly)

Reassembly

1. Remove the battery, keyboard, CPU, DDR2, HDD, ODD, LCD assembly and system board. (Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7 and 2.3.10 Disassembly)

2. Disconnect the modem cable and remove two screws, then free the modem card. (Figure 2-23)

Figure 2-23 Remove the modem card

MiTac Secret

Confidentia

l Docum

ent


72

3. Definition & Location of Connectors/Switches

3.1 Mother Board (Side A)

PJ501 : Power Jack

PJ502 : Battery Connector

J501 : CRT Connector

J502 : RJ11 & RJ45 Connector

J503, J506 : USB Port

J504 : USB Port*2

J505 : MDC Jump Wire Connector

J507 : MDC Connector

J510 : SATA HDD Connector

J512 : HP Jack

J514 : External MIC Jack

J513, J515 : DDR2 SO-DIMM Socket

J516 : Mini Express (Wireless) Connector

J518, J519 : Stereo Speaker Connector

PJ501J506

J503

J501

J504

J502

J505J507 J511

PJ502

J513,J515

J516

J514J512

J518

J519

J510

MiTac Secret

Confidentia

l Docum

ent


73

3. Definition & Location of Connectors/Switches

3.1 Mother Board (Side B)

J1

J2J3

SW5

SW2

SW3

SW4SW6

SW7

J4

J1 : LCD Inverter Connector

J2 : Internal Keyboard Connector

J3 : Touch-Pad Connector

J4 : Express Card Socket

SW2 : Mail Button

SW3 : Internet Button

SW4 : P1 Button

SW5 : Power Button

SW6 : Touch-Pad Left Button

SW7 : Touch-Pad Right Button

MiTac Secret

Confidentia

l Docum

ent


74

4. Definition & Location of Major Components

4.1 Mother Board (Side A)

U506 : LAN Controller VT6103L

U507 : Intel Merom Socket

U512 : Clock Generator ICS953009

U513 : VIA VN896 North Bridge

U514 : VIA VT8237A South Bridge

U507 U513

U506

U514

U512

MiTac Secret

Confidentia

l Docum

ent


75

4. Definition & Location of Major Components

4.1 Mother Board (Side B)

U10 : W83L951D Keyboard Controller

U21 : System BIOS

U21

U10

MiTac Secret

Confidentia

l Docum

ent


76

5. Pin Descriptions of Major Components

5.1 Intel Merom Processor CPU -1CPU Pin Description Signal Name Type Description A[35:3]# I/O

A[35:3]# (Address) define a 2*36-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmittransaction type information. These signals must connect the appropriate pins of both agents on the Celeron FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. Note: When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected

A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor’s address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

ADSTB[1:0]# I/O

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.

Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB[0]# A[35:17]# ADSTB[1]#

BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.

CPU Pin Description (Continued) Signal Name Type Description BNR# I/O BNR# (Block next request) is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus stall, the current bus owner can not issue any new transactions.

BPM[2:1]# BPM[3,0]#

I/O BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron FSB agents. This includes debug or performance monitoring tools.

BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

BR0# I/O BR0# is used by the processor to request the bus. The arbitration is done between Celeron processor (Symmetric Agent) and (G) MCH-M (High Priority Agent).

BSEL[2:0] O BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. The table defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Celeron processor 500 series operates at a 533-MHz system bus frequency (133MHz BCLK[1:0] frequency). BSE[2:0] Encoding for BCLK Frequency

BSEL[2] BSEL[1] BSEL[0] BCLK Frequency

L L L Reserved L L H 133MHz

COMP[3:0] Analog COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more implementation details.

MiTac Secret

Confidentia

l Docum

ent


77

5.1 Intel Merom Processor CPU -2CPU Pin Description (Continued) Signal Name Type Description D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit

data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups

Data Group DSTBN#/DSTBP# DINV#D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3

Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBR# O DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents.

DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents.

CPU Pin Description (Continued) Signal Name Type Description DINV[3:0]#

I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus

Bus Signal Data Bus Signals DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]#

DPRSTP# I DPRSTP# is not used by the Celeron processor. For termination requirements please refer to the platform design guide

DPSLP# I DPSLP# when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH8M I/O controller.

DPWR# I DPWR# is a control signal used by the chipset to reduce power on the processor data bus input buffers. This is not utilized by the Celeron processor 500 series.

DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents.

DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]#

MiTac Secret

Confidentia

l Docum

ent


78

5.1 Intel Merom Processor CPU -3CPU Pin Description (Continued) Signal Name Type Description DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]#

FERR#/PBE# O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# assertion indicates that an unmasked floating point error has been detected. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. In both cases, assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel Architecture Software Developer’s Manual and the Intel Processor identification and CPUID instruction application note. For termination requirements please refer to the appropriate platform design guide.

GTLREF I GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1.Please refer to the appropriate platform design guide for details on GTLREF implementation.

HIT# HITM#

I/O I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

CPU Pin Description (Continued) Signal Name Type Description IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to

ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT# I INIT#(Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers, The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write Instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction, INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Selt-Test(BIST).

LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

MiTac Secret

Confidentia

l Docum

ent


79

5.1 Intel Merom Processor CPU -4CPU Pin Description (Continued) Signal Name Type Description LOCK# I/O LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB,it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock.

PRDY#

O Probe Ready signal used by debug tools to determine processor debug readiness.

PREQ# I Probe Request signal used by debug tools to request debug operationof the processor.

PROCHOT# I/O As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. TCC will remain active until the system deasserts PRCCHOT#. For termination requirements please refer to the appropriate platform design guide. This signal may require voltage translation on the motherboard.

PSI# O Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep). Please refer to the IMVP-6 Mobile processor and Mobile chipset voltage regulation with power status indicator(PSI) specification for more details on the PSI# signal.

PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation.

REQ[4:0] I/O REQ[4:0]#(Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to definethe currently active transaction type. These signals are source synchronous to ADSTB[0]#.

CPU Pin Description (Continued) Signal Name Type Description RESET# I Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. There is a 55-Ω(normal) on die pull up resistor on this signal.

RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents.

RSVD Reserved/No Connect

These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the appropriate platform design guide for more details.

SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.

SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

MiTac Secret

Confidentia

l Docum

ent


80

5.1 Intel Merom Processor CPU -5CPU Pin Description (Continued) Signal Name Type Description STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter

a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port).

TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.

TEST1, TEST2 TEST3, TEST4

I TEST1 and TEST2 must have a stuffing option of separate pull down resistor to Vss. For testing purposes it is recommended, but not required, to route the TEST3 and TEST4 pins through a ground referenced 55 ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. THERMTRIP# O The processor protects itself from catastrophic overheating by use of

an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.

TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents.

TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

Vcc I Processor core power supply. Vcca I Vcca provides isolated power for the internal processor core PLL’s. Vccp I Processor I/O Power Supply.

CPU Pin Description (Continued) Signal Name Type Description Vcc_sense O Vcc_sense together with Vss_sense are voltage feedback signals to

Intel MVP6 that control the 2.1 mohm loadline at the processor die. It should be used to sense or measure power near the silicon with little noise.

VID[6:0] O VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Celeron processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. The VR must supply the voltage that is requested by the pins, or disable itself.

Vss_sense O Vss_sense together with Vcc_sense are voltage feedback signals to Intel MVP6 that control the 2.1mohm loadline at the processor die. It should be used to sense or measure ground near the silicon with little noise.

MiTac Secret

Confidentia

l Docum

ent


81

5.2 VIA VN896 North Bridge -1CPU Interface Signals

Signal Name Type Description HA[31:3]# IO Host CPU Address Bus. Connect to the address bus of the host

CPU. Inputs during CPU cycles and driven by the North Bridge during cache snooping operations.

HADSTB0P# (HADSTB0#) HADSTB0N# HADSTB1#

IO Host Address Strobe. (P4 Host Protocol) Source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0]# at a 2x transfer rate. HADSTB1# is the strobe for HA[31:17]# and HADSTB0# is the strobe for HA[16:3] and HREQ[4:0]#. (V4 Host Protocol) HADSTB0P# / HADSTB0N# are negativeedge going data strobes used to latch HA[30, 16:3]# and HREQ[2:0]# on even and odd data beat transfers respectively. Note: The ball HADSTB0# means HADSTB0P# in V4 Bus.

HD[63:00]# IO Host CPU Data. These signals are connected to the CPU data bus.HDBI[3:0]# IO Host CPU Dynamic Bus Inversion. Driven along with HD[63:0]#

to indicate if the associated signals are inverted or not. Used to limit the number of simultaneously switching signals to 8 for the associated 16-bit data pin group (HDBI3# for HD[63:48]#, HDBI2# for HD[47:32]#, HDBI1# for HD[31:16]#, and HDBI0# for HD[15:0]#). HDBIn# is asserted such that the number of data bits driven low for the corresponding group does not exceed 8.

HDSTB[3:0]P# HDSTB[3:0]N#

IO Host CPU Differential Data Strobes. Source synchronous strobes used to transfer HD[63:0]# and HDBI[3:0]# at a 4x transfer rate. HDSTB3P#/HDSTB3N# are the strobes for HD[63:48]# & HDBI3#; HDSTB2P#/HDSTB2N# are the strobes for HD[47:32]# & HDBI2#; HDSTB1P#/HDSTB1N# are the strobes for HD[31:16]# & HDBI1#; and HDSTB0P#/HDSTB0N# are the strobes for HD[15:0]# & HDBI0#.

HADS# IO Address strobe: The CPU asserts ADS# in T1 of the CPU bus cycle.

HDBSY# IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring more than one cycle.

HDRDY# IO Data Ready. Asserted for each cycle that data is transferred. HHIT# IO Hit. Indicates that a caching agent holds an unmodified version of

the requested line. Also driven in conjunction with HITM# by the target to extend the snoop window.

HHITM# IO Hit Modified. Asserted by the CPU to indicate that the address is modified in the L1 cache and needs to be written back.

HLOCK# IO Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the negation of HLOCK# must be atomic.

CPU Interface Signals (Continued) Signal Name Type Description

HREQ[4:0]# IO Request Command. Asserted during both clocks of the request phase. In the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type.

HTRDY# O Host Target Ready. Indicates that the target of the processor transaction is able to enter the data transfer phase.

HRS[2:0]# O Response Signals. Indicates the type of response per the table below:

RS[2:0]# Response type RS[2:0]# Response type 000 Idle State 100 Hard Failure 001 Retry

Response 101 Normal Without

Data 010 Defer

Response 110 Implicit

Writeback 011 Reserved 111 Normal With

Data HDPWR# O Data Bus Power Reduction. Request to reduce power on the

mobile CPU data bus input buffer. Connect to mobile CPU if used.

HBREQ0# IO Bus Request 0. Bus request output to CPU. HBPRI# O Priority Agent Bus Request. The owner of this signal will always

be the next bus owner. This signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the HLOCK# signal is asserted. The VN896 drives this signal to gain control of the processor bus.

HBNR# IO Block Next Request. Used to block the current request bus owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth.

HDEFER# O Defer. The VN896 uses a dynamic deferring policy to optimize system performance. The VN896 also uses the DEFER# signal to indicate a processor retry response.

CPURST# O CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground should be provided per CPU manufacturer’s recommendations.

MiTac Secret

Confidentia

l Docum

ent


82

5.2 VIA VN896 North Bridge -2DDR SDRAM Memory Controller Signal Descriptions

Signal Name Type Description MD[63:0] IO Memory Data. These signals are connected to the

DRAM data bus. MA[13:0] O Memory Address. DRAM address lines. MSRAS# MSCAS# MSWE#

O Row Address, Column Address and Write Enable Command Indicator Set.

MBA[2:0] O Bank Address: defines which bank will receive an ACTIVE, READ, WRITE, or PRECHARGE command.

MCS[3:0]# O Chip Select. Chip select of each bank. MDQM[7:0]# O DDR Data Mask. Data mask of each byte lane. MDQS[7:0]+/- IO DDR Data Strobe. Data strobe of each byte . MCKE[3:0] O Clock Enables. Clock enables for each DRAM bank for powering

down the SDRAM or clock control for reducing power usage and for reducing heat/temperature in highspeed memory systems.

MEMDET I Memory Detect: Strap low for DDR. Strap high for DDR2.

MODT[3:0] O On Die Termination. Enables termination resistance internal to the DDR2 SDRAM

CRT and Serial Bus Signal Descriptions

Signal Name Type Description CRTAR, CRTAG, CRTAB

AO Analog Red/Green/Blue. DAC outputs.

CRTHSYNC O Horizontal Sync. Output to CRT. CRTVSYNC O Vertical Sync. Output to CRT. CRTRSET AI Reference Resistor. Tie to GND through an external resistor to

control the RAMDAC full-scale current value. DVPSPCLK DVPSPD

IO DVPSPCLK is typically used for I2C communications DVPSPD is typically used for I2C communications

CRTSPCLK CRTSPD

IO Serial Port Clock and Data. Clock for serial data transfer. Data signals used for serial data transfer. It is typically used for CRT display DDC communications.

V-Link Signal Descriptions Signal Name Type Description

VD[7:0] IO V-Link Data Bus. During system initialization, VD[7:0] are used to transmit strap information from the South Bridge. Check the strapping table for details.

VPAR IO Parity. VBE# IO V-Link Byte Enable. VUPCMD I V-Link Command from Client (South Bridge) to Host (North

Bridge). VUPSTB+ I V-Link Strobe from Client to Host. VUPSTB– I V-Link Complement Strobe from Client to Host. VDNCMD O V-Link Command from Host (North Bridge) to Client (South

Bridge). VDNSTB+ O V-Link Strobe from Host to Client. VDNSTB– O V-Link Complement Strobe from Host to Client.

Clock Signal Descriptions

Signal Name Type Description VCLK I V-Link Clock. This signal receives the 66 MHz clock used to

generate the internal clocks required by V-Link interface between the North Bridge and South Bridge.

HCLK+ I Host Clock. This signal receives the host CPU clock (100/133/166/200 MHz). This clock is used by all VN896 logic that is in the host CPU domain.

HCLK– I Host Clock Complement. Used for Quad Data Transfer on host CPU bus.

PEXCLK+ PEXCLK–

I PCI Express Differential Clock. These signals receive the 100 MHz clock used by the internal PCI Express logic. Multiplied up to 2.5 GHz onchip for use by the integrated PCI Express PHY to transmit/receive data.

MCLKO+ O Memory (SDRAM) Clock. Output from internal clock generator to external memory interface clock buffer (if required for fanout)

MCLKO- O Memory (SDRAM) Clock Complement. MCLKI I Memory (SDRAM) Clock Feedback. Input from MCLKO. DISPCLKI I Dot Clock (Pixel Clock) In. Used for external EMI reduction

circuit if used. Connect to GND if external EMI reduction circuit not implemented.

DISPCLKO O Dot Clock (Pixel Clock) Out. Used for external EMI reduction circuit if used. NC if external EMI reduction circuit not implemented.

MiTac Secret

Confidentia

l Docum

ent


83

5.2 VIA VN896 North Bridge -3PCIe-multiplexed Digital Video Port Interface Signal

Signal Name Type Description DVP0D[11:0] DVP1D[11:0]

O 12-Bit LVDS Mode: DVP1D[11:00] is for 12-Bit LVDS Interface. 18-Bit LVDS Mode: DVP0D[11:06, 03:00] and DVP1D[11:10, 07:02] are for 18-Bit LVDS Interface. 24-Bit LVDS Mode: DVP0D[11:00] and DVP1D[11:00] are for 24-Bit LVDS Interface.

DVP0HS O Horizontal Sync. 24-bit mode or DVP0 in 12-bit mode. DVP0VS O Vertical Sync. 24-bit mode or DVP0 in 12-bit mode. DVP0DE O Data Enable. 24-bit mode or DVP0 in 12-bit mode. DVP0CLK O Clock Out. 24-bit mode or DVP0 in 12-bit mode. DVP1HS O Horizontal Sync. For DVP1 in 12-bit mode. DVP1VS O Vertical Sync. For DVP1 in 12-bit mode. DVP1DE O Data Enable. For DVP1 in 12-bit mode. DVP1DET I Display Detect. For DVP1 in 12-bit mode. DVP1CLK O Clock Output. For DVP1 in 12-bit mode.

Dedicated Digital Video Interface Signals Signal Name Type Description

DVP2D[11:00] O Data Output [11:00]. DVP2HS O Horizontal Sync. DVP2VS O Vertical Sync. DVP2CLK O Clock Output. DVP2TVCLKR/ DVP2DET

I Clock Return.

DVP2DE O Data Enable.

LCD Panel Power Control Signal Descriptions Signal Name Type Description

LVDSENVDD O Enable Panel VDD Power. LVDSENBLT O Enable Panel Back Light.

Power Signal Descriptions (Analog Power/Ground) Signal Name Type Description

VCCA33HCK P Power for Host CPU Clock PLL (3.3V ±5%). 400 MHz for CPU/DRAM frequencies of multiples of 100, 133, and 200 MHz.

GNDAHCK P Ground for Host CPU Clock PLL. Connect to main ground plane. VCCA33MCK P Power for Memory Clock PLL (3.3V ±5%) GNDAMCK P Ground for Memory Clock PLL. Connect to main ground plane. VCCA33PLL[3:1] P Power for Graphics Controller PLL (3.3V ±5%). GNDAPLL P Ground for Graphics Controller PLL. Connect to main ground

plane. VCCA33DAC[2:1] P Power for DAC. (3.3V ±5%) GNDADAC P Ground for DAC. Connect to main ground plane. GNDAPEX[2:0] P Ground for PCI Express Ports. GNDAPEXCK P Ground for PCI Express Clock. VCCA33PEX[2:0] P Power for PCI Express Port. VCCA33PEXCK P Power for PCI Express Clock.

Power Signal Descriptions (Digital Power/Ground) Signal Name Type Description

VTT P Power for CPU I/O Interface Logic. Voltage is CPU dependent. See Design guide for details.

VCCMEM P Power for Memory I/O Interface Logic. 2.5V (DDR)/1.8V (DDR2) ±5%.

VCC15VL P Power for V-Link I/O Interface Logic. 1.5V ±5% VCC33PEX P Power for PCIe I/O Interface Logic. 3.3V ±5% VCC33GFX P Power for Graphics Display I/O Logic. 3.3V ±5% VCC15 P Power for internal Logic. 1.5V ±5% VSUS15 P Suspend power. 1.5V ±5% VSUS15PEX P PCI Express Suspend Power. 1.5V ±5% GND P Digital Ground. Connect to main ground plane.

T r u ste d P la tfo r m M id u le S ig n a l D e sc r ip tio n s

S ig n a l N a m e Ty p e D e s c r ip tio n T C S E N # I T ru s te d C o n f ig u ra tio n S p a c e E n a b le .

MiTac Secret

Confidentia

l Docum

ent


84

5.2 VIA VN896 North Bridge -4Reset, Power Control, GPIO, Interrupt and Test Signal Descriptions

Signal Name Type Description XIN I Reference Frequency Input. External 14.31818 MHz clock source.

All internal graphics controller clocks are synthesized on chip using this frequency as a reference.

PWROK I Power OK. Connect to South Bridge and Power Good circuitry. SUSST# I Suspend Status. For implementation of the Suspend-to-DRAM

feature. Connect to an external pull-up to disable. RESET# I Reset. Input from the South Bridge chip. When asserted, this

signal resets the VN896 and sets all register bits to the default value. The rising edge of this signal is used to sample all power-up strap options.

CPUSLPIN# I Input from SLP# of South Bridge chip. This signal is used to inform North Bridge when the processor is in C3/C4 state.

BUSY# O Busy. Indicates that master cycles are pending in the chip. Used by the power management system to avoid changing the system power state while a master cycle is in progress.

GPOUT O General Purpose Output. This signal reflects the state of SRD[0].GPO0 O General Output Port. When SR1A[4] is cleared, this pin reflects

the state of CR5C[0]. PEXWAKE# OD PCI Express Wake. Indicates that a system wake event has

occurred on the PCI Express bus. Used to waken the chip from deep sleep mode (S3/S4/S5 states). Wire-OR with other system WAKE# signals (including PEWAKE# on the PCI Express bus connector) and connect to the South Bridge PME input.

PEXPMESCI# OD PCI Express PME SCI. System Control Interrupt to indicate Power Management Event. Connect to South Bridge SCI input (GPIO pin).

PEXHPSCI# OD PCI Express Hot-Plug SCI. System Control Interrupt to indicate Hot Plug occurred. Connect to South Bridge SCI input (GPIO pin).

PEXINTR# OD PCI Express Interrupt. Connect to South Bridge interrupt input to indicate that an interrupt condition was detected on PCI Express bus or the internal APIC.

INTA# O Interrupt. PCI interrupt output (handled by the interrupt controller in the south bridge).

PEXDET I PCI Express Detect. Used to determine the presence of an externalPCI Express device

TESTEN# I Test Enable. This signal is used for testing.

Compensation Signal Descriptions Signal Name Type Description

VLCOMPP AI V-Link P Compensation. VLCOMPN AI V-Link N Compensation. HGTLCOMPP AI AGTL P Compensation. HGTLCOMPN AI AGTL N Compensation. MEMCOMP AI DRAM Compensation. Memory interface IO buffer

calibration. PEXCOMP0 AI PCI Express Port G Compensation 0. PEXREXT0 AI PCI Express Port G External Resistor 0. PEXCOMP1 AI PCI Express Port G Compensation 1. PEXREXT1 AI PCI Express Port G External Resistor 1. PEXCOMP2 AI PCI Express Port 0 Compensation. PEXREXT2 AI PCI Express Port 0 Compensation Resistor.

Reference Voltage Signal Descriptions Signal Name Type Description

HGTLVREF[1:0] P Host CPU Interface AGTL+ Voltage Reference. 2/3 VTT ±2% typically derived using a resistive voltage divider. See design guide.

MEMVREF[1:0] P Memory Voltage Reference. ½ VCCMEM ±2% typically derived using a resistive voltage divider.

VLVREF P V-Link Voltage Reference. 0.45V / 0.625V ±2% derived using a resistive voltage divider.

PCI Express Interface Signals Signal Name Type Description

PEXRX[15:00]+/– I PCI Express Port G Differential Receive Data [15:00]. These signals are multiplexed with Digital Video Port Signal.

PEXTX[15:00]+/– O PCI Express Port G Differential Transmit Data [15:00]. PEXRX16+/– I PCI Express Port 0 Differential Receive Data 0. PEXTX16+/– O PCI Express Port 0 Differential Transmit Data 0.

MiTac Secret

Confidentia

l Docum

ent


85

5.3 VIA VT8237A South Bridge -1CPU Interface Signals

Signal Name Type Description A20M# OD A20 Mask. Connect to A20 mask input of the CPU to control

address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

FERR# I Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the CPU. Internally generates interrupt 13 if active.

IGNNE# OD Ignore Numeric Error. This signal is connected to the CPU “ignore error” pin.

INIT# OD Initialization. The VT8237A asserts INIT# if it detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register.

INTR OD CPU Interrupt. INTR is driven by the VT8237A to signal the CPU that an interrupt request is pending and needs service.

NMI OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The VT8237A generates an NMI when PCI bus SERR# is asserted.

SLP# OD Sleep. Used to put the CPU to sleep. SMI# OD System Management Interrupt. SMI# is asserted by the VT8237A

to the CPU in response to different Power-Management events. STPCLK# OD Stop Clock. STPCLK# is asserted by the VT8237A to the CPU to

throttle the processor clock. THRMTRIP#/GPI1 I Thermal Detect Power Down. This signal is to indicate a thermal

trip from the processor.

Serial ATA Interface Signals Signal Name Type Description

SRX0+/– I SATA Port 0 Differential Receiver. SRX1+/– I SATA Port 1 Differential Receiver. STX0+/– O SATA Port 0 Differential Transmitter. STX1+/– O SATA Port 1 Differential Transmitter. SXI I SATA Crystal In. SXO O SATA Crystal Out. SATALED# O SATA LED SREXT AI SATA External Resistor.

V-Link Interface Signals Signal Name Type Description

VD[15:0] IO Data Bus. All bits 15-0 are implemented for use with VIA north bridge chips which support this capability (if not, only bits 7-0 are used). VD[7:0] are also used to send strap information to the chipset north bridge (see strap table below for details). The specific interpretation of these straps is north bridge chip design dependent.

VPAR IO Parity. If the VPAR function is implemented in a compatible manner on the north bridge, this pin should be connected to the north bridge VPAR. If VPAR is not implemented in the north bridge chip or is incompatible with the VT8237A (4x V-Link north bridges) connect this signal to an 8.2 K pullup to 2.5 V.

VBE# IO Byte Enable. Connect to same named pin on north bridge. VCLK I V-Link Clock. 66 MHz. Supplied by clock gennerator. UPCMD O Command from Client-to-Host. Connect to same named pin on

north bridge. DNCMD I Command from Host-to-Client. Connect to same named pin on

north bridge. UPSTB+ O Strobe from Client-to-Host. Connect to same named pin on north

bridge. UPSTB- O Complement Strobe from Client-to-Host. Connect to same named

pin on north bridge. DNSTB+ I Strobe from Host-to-Client. Connect to same named pin on north

bridge. DNSTB- I Complement Strobe from Host-to-Client. Connect to same named

pin on north bridge.

General Purpose Output Interface Signals

Signal Name Type Description GPO0 O General Purpose Output 0. GPO1 O General Purpose Output 1. GPO2/SUSA# O General Purpose Output 2. GPO3/SUSST# O General Purpose Output 3. GPO4/SUSCLK O General Purpose Output 4. GPO5/CPUSTP# O General Purpose Output 5. GPO6/PCISTP# O General Purpose Output 6. GPO7/GNT5# O General Purpose Output 7. GPO9 O General Purpose Output 9.

MiTac Secret

Confidentia

l Docum

ent


86

5.3 VIA VT8237A South Bridge -2PCI Bus Interface Signals

Signal Name Type Description AD[31:0] IO Address/Data Bus. Multiplexed address and data. The address is

driven with FRAME# assertion and data is driven or received in following cycles.

CBE[3:0]# IO Command/Byte Enable. The command is driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks.

DEVSEL# IO Device select. The VT8237A asserts this signal to claim PCI transactions through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8237A-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.

FRAME# IO Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator.

IRDY# IO Initiator Ready. Asserted when the initiator is ready for data transfer.

TRDY# IO Target Ready. Asserted when the target is ready for data transfer.STOP# IO Stop. Asserted by the target to request the master to stop the

current transaction. SERR# I System Error. SERR# can be pulsed active by any PCI device that

detects a system error condition. Upon sampling SERR# active, the VT8237A can be programmed to generate an NMI to the CPU.

PERR# - Parity Error. PERR#, sustained tri-state, is only for the reporting of data parity errors during all PCI transactions except for a Special Cycle.

PAR IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

INTA# INTB# INTC# INTD# INTE#/GPI12,/ GPO12, INTF#/GPI13,/ GPO13, INTG#/GPI14,/ GPO14, INTH#/GPI15,/ GPO15

I PCI Interrupt Request. The INTA# through INTD# pins are typically connected to the PCI bus INTA#-INTD# pins per the table below. INTE-H# are enabled by setting. BIOS settings must match the physical connection method.

INTA# INTB# INTC# INTD# PCI Slot 1 INTA# INTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTE# PCI Slot 3 INTC# INTD# INTE# INTF# PCI Slot 4 INTD# INTE# INTF# INTG# PCI Slot 5 INTE# INTF# INTG# INTH# PCI Slot 6 INTF# INTG# INTH# INTA#

PCI Bus Interface Signals (Continued) Signal Name Type Description

REQ5#/GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0#

I PCI Request. These signals connect to the VT8237A from each PCI slot (or each PCI master) to request the PCI bus

GNT5#/GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0#

O PCI Grant. These signals are driven by the VT8237A to grant PCI access to a specific PCI master.

PCIRST# O PCI Reset. This signal is used to reset devices attached to the PCI PCICLK I PCI Clock. This signal provides timing for all transactions on the

PCI bus. CLKRUN# IO PCI Bus Clock Run. This signal indicates whether the PCI clock

is or will be stopped (high) or running (low). The VT8237A drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping.

SMBus Interface Signals Signal Name Type Description

SMBCK1 OD SMB/I2C Channel 1 Clock. Mater Mode. SMBDT1 OD SMB/I2C Channel 1 Data. Mater Mode. SMBCK2/GPI27/ GPO27

OD SMB/I2C Channel 2 Clock. Slave Mode.

SMBDT2/GPI26/ GPO26

OD SMB/I2C Channel 2 Data. Slave Mode.

SMBALT# I SMB SMB Alert. Enabled by System Management Bus I/O space. When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event.

MiTac Secret

Confidentia

l Docum

ent


87

5.3 VIA VT8237A South Bridge -3

Low Signal Count Pin Interface Signals Signal Name Type Description

LPCAD[3-0] IO LPC Address/Data. LPCFRAME# O LPC Frame. LPCDRQ[1-0]# I LPC DMA/Bus Master Request 0.

MII Interface Signals Signal Name Type Description

MCOL I MII Collision Detect. From the external PHY. MCRS I MII Carrier Sense. Asserted by the external PHY when the media

is active. MDC O MII Management Data Clock. Sent to the external PHY as a

timing reference for MDIO. MDIO IO MII Management Data I/O. Read from the MDI bit or written to

the MDO bit. MRXC I MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY. MRXD[3:0] I MII Receive Data. Parallel receive data lines driven by the

external PHY synchronous with MRXC. MRXDV I MII Receive Data Valid. MRXER I MII Receive Error. Asserted by the PHY when it detects a data

decoding error. MTXC I MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied

by the PHY. MTXD[3:0] O MII Transmit Data. Parallel transmit data lines synchronized to

MTXC. MTXEN O MII Transmit Enable. Signals that transmit is active from the MII

port to the PHY. PHYRST# O External PHY Reset. PHYPWRDN# O PHY Power Down. Output when PHY is in power state as D1 hot,

D2 hot or D3 hot with no PME and WOL enable.

PC/PCI DMA Interface Signals Signal Name Type Description

PCREQA/GPI24/ GPO24 (GPIOA)

I PC/PCI Request A.

PCREQB/GPI25/ GPO25 (GPIOB)

I PC/PCI Request B.

PCGNTA/GPI30/ GPO30 (GPIOC)

O PC/PCI Grant A.

PCGNTB/GPI31/ GPO31 (GPIOD)

O PC/PCI Grant B.

CPU Speed Control Interface Signals Signal Name Type Description

VGATE/GPI8/ GPO8

I Voltage Gate. Signal from the CPU voltage regulator. High indicates the voltage regulator output os stable.

VIDSEL/GPI28/ GPO28

OD Voltage Regulator ID Select. Connected to the CPU voltage regulator. Low selects the voltage ID from the CPU; high selects a different fixed voltage ID (the lower voltage used for CPU deep sleep mode).

VRDSLP/GPI29/ GPO29

OD Voltage Regulator Deep Sleep. Connected to the CPU voltage regulator. High selects the proper voltage for deep sleep mode.

GHI#/GPI22/ GPO22

OD CPU Speed Select. Connected to the CPU voltage regulator, used to select high speed (L) or low speed (H).

DPSLP#/GPI23/ GPO23

OD CPU Deep Sleep. Used to put the CPU into a deeper sleep mode.

CPUMISS/GPI17 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS signal of the CPU socket. The state of this signal may be read in the SMBus 2 registers.

AGPBZ#/GPI6 I AGP Busy. Low indicates that an AGP master cycle is in progress (CPU speed transitions will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.

S eria l IR O In terfa ce S ig na ls S ign a l N a m e Typ e D escr ip tion

S E R IR Q I S eria l IR Q . T h is s ign al has an in terna l pu ll-up resisto r.

APIC Interface Signals Signal Name Type Description

APICD1/GPIO11 O Internal APIC Data 1. APICD0/GPIO10 O Internal APIC Data 0. APICCLK/GPI19 I Internal APIC Clock.

Programming Chip Selects Signals Signal Name Type Description

PCS0#/AZSDIN2/ GPIO20

O Programmable Chip Select 0. AZSDIN2 is multiplexed with this pin. PCS0# can optionally be used as GPIO20.

PCS1#/AZSDIN3/ GPIO21

O Programmable Chip Select 1. AZSDIN3 is multiplexed with this pin. PCS1# can optionally be used as GPIO21.

MiTac Secret

Confidentia

l Docum

ent


88

5.3 VIA VT8237A South Bridge -4USB 2.0 Interface Signals

Signal Name Type Description USBP0+/– IO USB Port 0 Differential Data. USBP1+/– IO USB Port 1 Differential Data. USBP2+/– IO USB Port 2 Differential Data. USBP3+/– IO USB Port 3 Differential Data. USBP4+/– IO USB Port 4 Differential Data. USBP5+/– IO USB Port 5 Differential Data. USBP6+/– IO USB Port 6 Differential Data. USBP7+/– IO USB Port 7 Differential Data. USBCLK I USB Clock. 48 MHz clock input for the USB interface USBOC0# I USB Port 0 Over Current Detect. Port 0 is disabled is disabled of

low. USBOC1# I USB Port 1 Over Current Detect. Port 1 is disabled is disabled of







low. USBREXT AI USB External Resistor.

Serial EEPROM Interface Signals Signal Name Type Description

SEECS O Serial EEPROM chip select. SEECK O Serial EEPROM clock. SEEDO I Serial EEPROM Data Output. Connect to EEPROM Data Out pin.SEEDI O Serial EEPROM Data Input. Connect to EEPROM Data In pin.

General Purpose Input Interface Signals Signal Name Type Description

GPI0 I General Purpose Input 0. GPI1/THRMTRIP# I General Purpose Input 1. GPI2/EXTSMI# I General Purpose Input 2. GPI3/RING# I General Purpose Input 3. GPI4/LID# I General Purpose Input 4. GPI5/BATLOW# I General Purpose Input 5. GPI6/AGPBZ# I General Purpose Input 6. GPI7/REQ5# I General Purpose Input 7. GPI8/GPO8/ VGATE

I General Purpose Input 8.

GPI9 I General Purpose Input 9. GPI16/ INTRUDER#


GPI17/CPUMISS I General Purpose Input 17. GPI18/THRM#/ AOLGPI


GPI19/APICCLK I General Purpose Input 19.

Internal Keyboard Controller Interface Signals Signal Name Type Description

MSCK IO Mouse Clock. From internal mouse controller. MSDT IO Mouse Data. From internal mouse controller. KBCK IO Keyboard Clock. From internal keyboard controller. KBDT IO Keyboard Data. From internal keyboard controller.

Speaker Interface Signals Signal N am e Type D escription

SPK R O Speaker. Strap low to enable (high to disable) CPU frequency strapping.

MiTac Secret

Confidentia

l Docum

ent


89

5.3 VIA VT8237A South Bridge -5Enhanced IDE Interface Signals

Signal Name Type Description PDIORDY/ PDDMARDY/ PDSTROBE

I EIDE Mode: Primary I/O Channel Ready. Device read indicator

UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device may assert PDDMARDY to pause output transfers Primary Device Strobe. Input data strobe (both edges). The device may stop PDSTROBE to pause input data transfers

SDIORDY/ SDDMARDY/ SDSTROBE

I EIDE Mode: Secondary I/O Channel Ready. Device ready indicator

UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The device may assert SDDMARDY to pause output transfers Secondary Device Strobe. Input data strobe (both edges). The device may stop SDSTROBE to pause input data transfers

PDIOR#/ PHDMARDY/ PHSTROBE

O EIDE Mode: Primary Device I/O Read. Device read strobe UltraDMA Mode: Primary Host DMA Ready. Primary channel

input flow control. The host may assert PHDMARDY to pause input transfers Primary Host Strobe. Output data strobe (both edges). The host may stop PHSTROBE to pause output data transfers

SDIOR#/ SHDMARDY/ SHSTROBE

O EIDE Mode: Secondary Device I/O Read. Device read strobe UltraDMA Mode: Secondary Host DMA Ready. Input flow

control. The host may assert SHDMARDY to pause input transfers Second Host Strobe. Output strobe (both edges). The host may stop SHSTROBE to pause output data transfers

PDIOW#/PSTOP O EIDE Mode: Primary Device I/O Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the

host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst

Enhanced IDE Interface Signals (Continued) Signal Name Type Description

SDIOW#/SSTOP O EIDE Mode: Secondary Device I/O Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by

the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

PDDREQ I Primary Device DMA Request. Primary channel DMA request SDDREQ I Secondary Device DMA Request. Secondary channel DMA

request PDDACK# O Primary Device DMA Acknowledge. Primary channel DMA

acknowledge SDDACK# O Secondary Device DMA Acknowledge. Secondary channel DMA

acknowledge IRQ14 I Primary Channel Interrupt Request. IRQ15 I Secondary Channel Interrupt Request. PDCS1# O Primary Master Chip Select. This signal corresponds to CS1FX#

on the primary IDE connector. PDCS3# O Primary Slave Chip Select. This signal corresponds to CS3FX# on

the primary IDE connector. SDCS1# O Secondary Master Chip Select. This signal corresponds to

CS17X# on the secondary IDE connector. SDCS3# O Secondary Slave Chip Select. This signal corresponds to CS37X#

on the secondary IDE connector. PDA[2:0] O Primary Disk Address. PDA[2:0] are used to indicate which byte

in either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VD[6:4].

SDA[2:0] O Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed.

PDD[15:0] IO Primary Disk Data. SDD[15:0] IO Secondary Disk Data.

MiTac Secret

Confidentia

l Docum

ent


90

5.3 VIA VT8237A South Bridge -6General Purpose Input/Output Interface Signals

Signal Name Type Description GPIO8/VGATE/ SLPBTN#

IO General Purpose I/O 8.

GPIO10/APICD0 IO General Purpose I/O 10. GPIO11/APICD1 IO General Purpose I/O 11. GPIO12/INTE# IO General Purpose I/O 12. GPIO13/INTF# IO General Purpose I/O 13. GPIO14/INTG# IO General Purpose I/O 14. GPIO15/INTH# IO General Purpose I/O 15. GPIO20/AZSDIN2/ PCS0#


GPIO21/AZSDIN3/ PCS1#


GPIO22/GHI# IO General Purpose I/O 22. GPIO23/GPI23/ DPSLP#

IO General Purpose Output 23.

GPIO24/GPIOA/ PCREQA

IO General Purpose I/O A/24.

GPIO25/GPIOB/ PCREQB

IO General Purpose I/O B/25.

GPIO26/SMBDT2 IO General Purpose I/O 26. GPIO27/SMBCK2 IO General Purpose I/O 27. GPIO28/VIDSEL IO General Purpose I/O 28. GPIO29/VRDSLP IO General Purpose I/O 29. GPIO30/GPIOC/ PCGNTA

IO General Purpose I/O C/30.

GPIO31/GPIOD/ PCGNTB

IO General Purpose I/O D/31.

Analog Power and Ground (SATA Controller)

Signal Name Type Description VCCA25SXO P SATA Oscillator Power. 2.5V ±5%. GNDASXO P SATA Oscillator Ground. VCCA25RXSATA P SATA Analog Power. 2.5V ±5%. VCCA25TXSATA P SATA Analog Power. 2.5V ±5%. GNDARXSATA P SATA Analog Ground. GNDATXSATA P SATA Analog Ground.

High Definition Audio Interface Signals Signal Name Type Description

AZRST# O High definition audio reset. AZBITCLK O High definition audio bit clock.

24MHz AZSYNC O High Definition Audio Sync.

48 KHz Frame Sync and outbound tag signal AZSDOUT O High definition audio serial data output.

Bussed serial data output signal 0. AZSDIN0 I High definition audio serial data input 0.

Point-to-point serial data input signal 0. AZSDIN1 I High definition audio serial data input 1.

Point-to-point serial data input signal 1. AZSDIN2/PCS0#/GPIO20

I High definition audio serial data input 2. Point-to-point serial data input signal 2. AZSDIN2 is multiplexed with PCS0#. AZSDIN2 can optionally be used as GPIO20.

AZSDIN3/PCS1#/GPIO21

I High Definition Audio Serial Data Input 3 Point-to-point serial data input signal 3. AZSDIN3 is multiplexed with this pin PCS1#. AZSDIN3 can optionally be used as GPIO21.

Compensation and Reference Voltage Signal Description Signal Name Type Description

VLCOM P AI V-Link Compensation. VLVREF P V-Link Voltage Reference.

Analog Power and Ground (PLL Analog) Signal Name Type Description

VCCA25PLL P PLL Analog Power. 2.5V ±5%. Connect to VCC through a ferrite bead.

GNDAPLL P PLL Analog Ground. Connect to GND through a ferrite bead.

MiTac Secret

Confidentia

l Docum

ent


91

5.3 VIA VT8237A South Bridge -7Power Management and Event Signals

Signal Name Type Description PWRBTN# I Power Button. Used by the Power Management subsystem to

monitor an external system on/off button or switch. Internal logic powered by VSUS33.

SLPBTN#/ VGATE/GPIO8

I Sleep Button. Used by the Power Management subsystem to monitor an external sleep button or switch.

RSMRST# I Resume Reset. Resets the internal logic connected to the VSUS33 power plane and also resets portions of the internal RTC logic. Internal logic powered by VBAT.

EXTSMI#/GPI2 IO External System Management Interrupt. When enabled to allow it, a falling edge on this input causes an SMI# to be generated to the CPU to enter SMI mode. EXTSMI# can optionally be used as GPI2

PME# I Power Management Event. SMBALT# I SMB Alert. When programmed to allow it, assertion generates an

IRQ, SMI, or power management event. LID#/GPI4 I Notebook Computer Display Lid Open / Closed Monitor. Used by

the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high or high-to-low transitions to generate an SMI#. LID# can optionally be used as GPI4.

INTRUDER#/ GPI16

I Intrusion Indicator. INTRUDER# can optionally be used as GPI16.

THRM#/GPI18/ AOLGPI

I Thermal Alarm Monitor. This signal is to enable the throttling mode for the duty cycle control of stop clock. AOLGPI is multiplexed with this pin. THRM# can optionally be used as GPI18.

RING#/GPI3 I Ring Ondicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. RING# can optionally be used as GPI5.

BATLOW#/GPI5 I Battery Low Indicator. BATLOW# can optionally be used as GPI5.

CPUSTP#/GPO5 O CPU Clock Stop. Signals the system clock generator to disable the CPU clock outputs. Not connected if not used.

PCISTP#/GPO6 O PCI Clock Stop. Signals the system clock generator to disable the PCI clock outputs. Not connected if not used.

WAKE# I For a Wake-up Event. Connect to PCI Express PEWAKE# signal.SUSA#/GPO2 O Suspend Plane A Control. Asserted during power management

POS, STR, and STD suspend states. Used to control the primary power plane.

Power Management and Event Signals (Continued) Signal Name Type Description

SUSB# O Suspend Plane B Control. Asserted during power management STR and STD suspend states. Used to control the secondary power plane.

SUSC# O Suspend Plane C Control. Asserted during power management STD suspend state. Used to control the tertiary power plane. Also connected to ATX power-on circuitry.

SUSST#/GPO3 O Suspend Status 1. Typically connected to the North Bridge to provide information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states.

SUSCLK O Suspend Clock. It is an output clock of the RTC generator circuit to use by other chips for refresh clock.

CPUMISS/GPI17 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This signal may be used as CPUMISS and GPI17 at the same time.

AOLGPI/GPI18/ THRM#

I Alert On LAN. The state of this pin may be read in the SMBus 2 registers. This signal may be used as AOLGPI, GPI18 and THRM# all at the same time.

Resets, Clock and Power Status Interface Signals Signal Name Type Description

PWRGD I Power Good. Connected to the Power Good signal on the Power Supply.

PWROK O Power OK. Internal logic powered by VSUS33. PCIRST# O PCI Reset. Active low reset signal for the PCI bus. The VT8237A

will assert this pin during power-up or from the control register. OSC I Oscillator. 14.31818 MHz clock signal used by the internal Timer. RTCX1 I RTC Crystal Input: 32.768 KHz crystal or oscillator input. RTCX2 O RTC Crystal Output: 32.768 KHz crystal output. TEST I Test. TPO O Test Pin Output. Output pin for test mode.

MiTac Secret

Confidentia

l Docum

ent


92

5.3 VIA VT8237A South Bridge -8

Analog Power and Ground (USB Controller) Signal Name Type Description

VCCA25PLLUSB P USB PLL Analog Voltage. Connect to VCC through a ferrite bead. 2.5V ±5%.

GNDAPLLUSB P USB PLL Analog Ground. Connect to GND through a ferrite bead.

Digital Power and Ground Signal Name Type Description

VCC25 P Core Power. 2.5V ±5%. This supply is turned on only when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high.

VCC33 P I/O Power. 3.3V ±5%. VBAT P RTC Battery. Battery input for internal RTC (RTCX1, RTCX2).GND P Ground. Connect to primary motherboard ground plane. VCC25VL P V-Link Compensation Circuit Voltage. 2.5V ±5%. VSUS25 P Suspend Power. 2.5V ±5%. VSUS33 P Suspend Power. 3.3V ±5%. Always available unless the

mechanical switch of the power supply is turned off. If the “soft-off” state is not implemented, then these signal balls can be connected to VCC33.

VCC33MII P MII Power. 3.3V ±5% I/O Power for LAN Media Independent Interface (interface to external PHY).

VSUS25MII P MII Suspend Power. 2.5V ±5%. VCC33USB P USB Power. 3.3V ±5%. GNDUSB P USB Ground. VSUS25USB P USB Suspend Power. 2.5V ±5%.

MiTac Secret

Confidentia

l Docum

ent


93

6. System Block Diagram

VIAVT1637

LCD PANEL

CRT

U514South Bridge

VIA VT8237A

DDR2 400/533/667 MHz

U507CPU

Intel Merom

U513North BridgeVIA VN896

CD ROM

HDD

MDCModule

Audio codecALC268

AMPLIFIERAPA2056

NEW

CARD

PHY

10/100 LAN VIA VT6103L

SYSTEM

BIOS 512 K

6 LEDsAC+Battery, Charger, WLAN,ODD & HDD, Num, Caps

Mini-PCIEWireless

TOUCHPAD

Keyboard BIOS WINBONDW83L951D

THM Sensor G781f

Fan

PWR S/W G577D5U

Quick Keys

E-mail Internet PI (Reserved)

CLOCK GENERATOR

ICS953009

USB 0/1/2/3

32.768 KHz

25 KHz

PATA

SATA/PATA

AZALIA

MII BUS

RJ45/RJ11HPJACK

SPEAKER SPEAKER

EXT MIC

RGB

DVO LVDS

15.4” WXGA

USB

PCI-EXPRESS/USB

PCI-EXPRESS/USB

LPC BUS

12 MHz

I-LIMITPS/2

KEY

M

ATR

IX

FSB533/667/800 MHz

V-Link 4X/8X533 MHz

14.318 MHz

MiTac Secret

Confidentia

l Docum

ent


94

7. Trouble Shooting

7.1 No Power (*1)

7.2 No Display (*2)

7.3 Graphics Controller Test Error LCD No Display

7.4 External Monitor No Display

7.5 Memory Test Error

7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error

7.7 Hard Disk Drive Test Error

7.8 ODD Drive Test Error

7.9 USB Port Test Error

7.10 Audio Test Error

7.11 LAN Test Error

7.12 Mini Express (Wireless) Socket Test Error

7.13 Express Card Socket Test Error

MiTac Secret

Confidentia

l Docum

ent


95

*1: No Power DefinitionBase on ACPI Spec. We define the no power as while we press the power button, the system can’t leave S5 statusor none the PG signal send out from power supply. Judge condition:

Check whether there are any voltage feedback control to turn off the power.Check whether no CPU power will cause system can’t leave S5 status.

If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sendingout the PG signal. If yes, we should add the effected analysis into no power chapter.

*2: No Display Definition Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as while system leave S5 status but can’t get into S0 status.Judge condition:

Check which power will cause no display.Check which reset signal will cause no display.Check which Clock signal will cause no display.

Base on these three conditions to analyze the schematic and edit the no display chapter.

Keyword:S5: Soft OffS0: Working

For detail please refer the ACPI specification.

MiTac Secret

Confidentia

l Docum

ent


96

7.1 No Power -1When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

ACPower

BatteryBATTBATT_TBATT_VBATT_CBATT_D

U10PU506PJ502PF502PQ516PD512PD501PQ520PL505

Where frompower source problem

(first use AC to power it)?

Check following parts and signals:


Parts: Signals:No

Board-levelTroubleshooting

ReplaceMotherboard

No Power

Try another known goodbattery or AC adapter.

Is thenotebook connected

to power (either AC adaptoror battery)?

Connect AC adaptoror battery.

No

Replace the faulty ACadaptor or battery.

PowerOK?

Yes

Yes

Parts:

U10PU501PU506PF1PQ1PQ2PD4PD2PR5EL545

Signals:

+PWR_VDDIN+DVMAINADINPLEARNINGADEN#I_LIMIT

MiTac Secret

Confidentia

l Docum

ent


97

7.1 No Power -2When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

: Page 30 on M/B circuit diagram.

: Through by part PD708.

NOTE :

PD708

P30

Main Voltage Map

+DVMAINADINPPOWER IN

+PWR_VDDIN

PJ501

PF1

PD501Discharge

PD2

PD4

BATTPF501,EL534,PQ516,PL505PU506,PD512

PQ520,PR45,PR46,PQ8,PQ7

Charge

Discharge

U9,F2

+VDD3_ALW

PR5PQ1

+VDD3_AVREFQ502

P26

P27P27P27

P27

P21 P21

+VDD3_RTCD11

P11

+VDD3_KBC_AVREFEL524

P19

+CPU_COREPU502,EL523,PQ509,PQ507,PQ508,PQ510PQ511,PQ512,PL503,PL504 P25

+VDD3SQ507

P21

PQ504A,PQ504BPL501

+3V_PP24EL514,PU503

PQ503,PQ505PL502 +5V_P

P24

+0.9V_PP23

+1.8V_PP23

EL544,PU3 PQ519,PQ518,PL506

Q504+3V

EL6+VDD3S_SB

+VDD3S_KBC

U510+VDD2.5S

EL525

P21

P12

P21

P19

PR37

MiTac Secret

Confidentia

l Docum

ent


98

When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

7.1 No Power -3

+PWR_VDDINA K

PC29470P

PF16.5A/32VDC

PC5891000P

PQ1AO4419

LEARNING35

PQ22N7002K

U10

KBC

W83L951D

P19

PR50.01

PR50110

4

5

6

RS+

RS-PU501

PC5021U

PC5040.1U

3VCC

GND1

OUT1 GND0

G

S

D

2 316 7 85

PQ520AO4409

+DVMAIN

BATT

POWER IN

PJ501

1

2

3 4

PR3470K

ADINP1

2

PD4PDS1040

PR14.7K

PR24.7K

3

PR45 100K

PR4633K

PQ82N7002K

PR44 226K

PQ7DTC144WK

PC5821000P

PC5801000P

PC5791000P

PC5871000P

GND

GND

GNDGND

GND

GND

GND

GND

GND

2

1

PJO1OPEN-SMT4

PR71M

PR4100K

PR60

PD2EC10QS04

ADEN#

G

S D

23

1678

5

P27

PC5831000P

PC5771000PPD3

BZV55C24PD1

BZV55C24

EC56018P

EC118P

EL545120Z/100M

PR50210

PR620

I_LIMIT110

MiTac Secret

Confidentia

l Docum

ent


99

Charge


7.1 No Power -4

ADINP

P26PL50533UH

C1,C2

PD508BAS32L

PR5564.7K

PR5584.7K

PQ514MMBT2222A

8,11

PR564100K

PD509B340A

4

G

S D

23

1678

5

PQ516AO4419

I_CTRL

From P19 U10

BATT

PC5694.7U

PR5680

PQ32N7002KG

S

D

PQ4DTA144WK

PC5650.1U

VCC

OUTPUTCTRL

REF2IN-

DTC 4FEEDBACK

PR567100K

3

1IN-

2IN+ 16

2

PU506

TL594C

CHARGING

From P19 U102IN+12

13

14

5

6

CT

RT

PR56610K

PC5631000P

PC100.01U

PC5641U

PC5660.1U

PR5736.19K

P26

PR57010K

PC5670.1U

15

REF

PR57147K

PJS2SHORT-SMT3

PR5722.49K

PF501TR/3216FF-3A

PC5561000P

PC5571000P

PC5734.7U

BATTERY_TYPETo P19 U10

PR2420K

PR2113.7K

PR2223.7K

PQ62N7002KG

S

D

PQ52N7002KG

S

DCHARGING

From P19 U10

PD512B340A

EL534120Z/100M

PC5584.7U

PC5714.7U

PC5741000U

PC5704.7U

PR20332K

MiTac Secret

Confidentia

l Docum

ent


100

Discharge


7.1 No Power -5

+VDD3S_KBC

1 23

C680.1U

C690.1U

D9BAV70LT1

107

111

PC5750.1U

PR575100K

PR576499K

PF502TR/SFT-10A

PC5780.1U

1,2

5

+VDD3_KBC_AVREF

PR414.99K

PR4220K

PC280.1U

BATT_T

BATT_V

BATT_C

BATT_D

U10

Keyboard

BIOS

W83L951D

41

42

BAT_CLK

BAT_DATA

PJ502

Battery C

onnector

P27

P19

3

4

PR480

PR470

PQ82N7002K

PR4633K

ADEN#3

+DVMAIN

PR45100K

+PWR_VDDIN

ZD15BAV99

ZD14BAV99

PQ7DTC144WK

PR44226K

ADINP

R6122

BATT

BAT_TEMP

BAT_VOLT

R492.7K

R422.7K

+VDD3S_KBC

G

SD

23

1678

5

PQ520AO4409

4

PC330.1U

R4822

R4122

R6322

PD501EC10QS04

+VDD3_KBC_AVREF +VDD3_KBC_AVREF

PC29470P

PR430

PC5760.1UMiTac Secret

Confidentia

l Docum

ent


101

7.2 No Display -1There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.

No Display

Monitoror LCD module

OK?

Replace monitoror LCD.


SystemBIOS writes

error code to port by MiniPCI-E debug

card?Yes

No

Yes

No

Refer to port error code descriptionsection to find out which part is causing the problem.

Make sure that CPU module,DIMM memory are installedProperly.

DisplayOK?

Yes

No

Correct it.

Check system clock, reset circuit and reference power

ReplaceMotherboard

1.Try another known good CPU module,DIMM module.

2.Remove all of I/O device ( HDD,ODD…….) from motherboardexcept LCD or monitor.

DisplayOK?

1. Replace faulty part.2. Connect the I/O device to the M/B

one at a time to find out whichpart is causing the problem.

Yes

No

Q10BQ17AQ17BJ4J516

SMBDATASMBCLKUSBCLK_SBOSC_SBVCLK_SBPCICLK_SBCPU_STOP#STOP_PCI#HCLK_CPU+/-PCICLK_KBCPCICLK_FWMPCIECLK_NCARD+/-


U507U10U21U516U513U512U514U511J511X504SW5Q10A

PCIEREQ_NCARD#PCIECLK_MINI+/-PCIEREQ_MINI#VCLK_NBPCIECLK_NB+/-HCLK_NB+/-SB_PWRGDPCI_RESET#KBC_PCIRST#FWM_PCIRST#NB_PCIRST#RSMRST#

Parts: Signals:

MiTac Secret

Confidentia

l Docum

ent


102

****** System Clock Check ******

7.2 No Display -2

R623 2217 PCICLK_KBC

R627 2218 PCICLK_FWM

36PCIEREQ_NCARD#

R137 33 42PCIECLK_NCARD+

R140 33 41PCIECLK_NCARD-

J4

P15

19

Express CardConnector

18

16

R624 3338PCIECLK_MINI+

R628 33 37PCIECLK_MINI-

J516

P15

13

11

35PCIEREQ_MINI#7

R608 2211 PCICLK_SB

6

7

X50414.318MHz

C57810P

12

31 SMBCLK

R834.7K

R844.7K

48 SMBDATA

U514

South Bridge

VIA VT8237A

P11

23 USBCLK_SB

R589 22

27

OSC_SB

VCLK_SB

5

22R636

R631 22

R605 3350 HCLK_CPU-

R600 33

53

4

HCLK_NB-

GUICLK

U507CPUIntel

Merom

P3

U513North Bridge

VIAVN896

P6

+3VS

EL532120Z/100M

+3.3VS_CLK

R620 33

R594 33

R638 22

R616 33

43

54

27

44

PCIECLK_NB-

HCLK_NB+

VCLK_NB

PCIECLK_NB+

U512

ClockGenerator

ICS953009

P8

1,3..

51 HCLK_CPU+

R597 33

R116 22

C57910P

P12

34 CPU_STOP#

D503BAT54

C57322U

P5

Q10B2N7002DW

Q10A2N7002DW

33 STOP_PCI#

D504BAT54

U10Keyboard Controller

W83L951D

P19

U21System BIOS

P20

51

31

Wireless LANCard Connector

+3VS

R984.7K

+VDD3S_SB

R5824.7K

MiTac Secret

Confidentia

l Docum

ent


103

7.2 No Display -3****** Power Good & Reset Circuit Check ******

29

3

KBC_RESET#50 4

+VDD3S_KBC

C5480.01U

MN

RESET# VCC

GND1

2

U514

South

Bridge

VIA

VT8237A

U10

KBC

W83L951D

P196 PWRBTN#

U508

R541100K

P21

SB_PWRBTN#

37 SB_PWRGD

P12P11SW513

245

R171K

C131000P

R54410K

RSMRST#30

4

53

+3VSU511

AHC1G08DBV

1

2

SB_PWRGD

PCI_RESET#

ODD ConnectorP13

J511+5VS

R21810K

Q17BDDC144TU

+5VS

R20410K

Q17ADDC144TU

U21System BIOS

P20

KBC_PCIRST#JL501

JP_NET10

FWM_PCIRST#

JL506JP_NET10

R508100 2

U513North BridgeVIA VN896

P6

JL505JP_NET10 NB_PCIRST#

J516P15Wireless LAN

Card Connector

JL502JP_NET10 MINIPCIE_PCIRST# 22

JL504JP_NET10

IDE

_PC

IRST

#

R21133

5

53 KBC_PCIRST#

+VDD3_ALW

ZJO14

R2860

2

R54310K

MiTac Secret

Confidentia

l Docum

ent


104

7.3 Graphics Controller Test Error LCD No Display -1There is no display or picture abnormal on LCD although power-on-self-test is passed.

DisplayOK?

Replace faultyLCD or monitor.

DisplayOK?

Graphics Controller Test ErrorLCD No Display

1. Confirm LCD panel or monitor is good and check the cable are connected properly.

2. Try another known good monitor or LCD module.

Remove all the I/O device & cable from motherboard except LCD panel or extended monitor.

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

Yes

No

Yes

No

Re-soldering.

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.


ReplaceMotherboard

Yes

No

Check if J1 is coldsolder?

Parts

U513U504U514U10U6J1EL540EL541EL542EL543

Signals

PANEL_ID0/1LCD_SPCLKLCD_SPD+DVMAINBLADJENABKL_LCDH8_ENABKL+3VS

EL4EL1Q5Q4ER512ER513

LCD_A_TXD0+/-LCD_A_TXD1+/-LCD_A_TXD2+/-LCD_A_CLK+/-LTX0+/-LTX1+/-LTX2+/-LCLK+/-ENVDD_NB

MiTac Secret

Confidentia

l Docum

ent


105

7.3 Graphics Controller Test Error LCD No Display -2There is no display or picture abnormal on LCD although power-on-self-test is passed.

1,2

J1

ENVDD_NB

6

8

U513

North BridgeVIA VN896

LCD_SPCLK

LCD_SPD

LCD

Inverter Board

LCD

/Inverter Connector

P10

LCD_A_TXD[0..2]-,LCD_A_CLK-U504

LVDSEncoderVT1637

P9

P6

9,15,21,27

11,17,23,29

16,18,21,24

15,17,20,23 LCD_A_TXD[0..2]+,LCD_A_CLK+

U514

South BridgeVIA

VT8237A

P11

PANEL_ID0

PANEL_ID1

5

4

U10KBC

W83L951D

P19

BLADJ 24

H8_ENABKL 22

+D/VMAIN 14,16

ENVDD_NB

LCD_SPCLK

LCD_SPD

LTX[0..2]-,LCLK-

LTX[0..2]+,LCLK+

PANEL_ID0

PANEL_ID1

BLADJ

ENABKL_LCDChange to

Change to

Change to

MiTac Secret

Confidentia

l Docum

ent


106

DisplayOK?

DisplayOK?

External Monitor No Display

1. Confirm monitor is good and checkthe cable are connected properly.

2. Try another known good monitor.

Remove all the I/O device & cable from motherboard except monitor.

Replace faulty monitor.

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

Yes

No

Yes

No

YesRe-soldering.

No

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.

Parts:

U513U517U518J501Q1A/BEL501EL502EL505EL506EL507EL22EL28

Signals:

+5VS+3VSCON_DDDACON_HSYNCCON_VSYNCCON_DDCKCON_REDCON_GREENCON_BLUECRT_BLUECRT_GREEN


ReplaceMotherboard

Check if J501is cold solder?

7.4 External Monitor No Display -1There is no display or picture abnormal on CRT monitor, but it is OK for LCD.

CRT_REDCRT_DDC_DATACRT_DDC_CLKCRT_VSYNCCRT_HSYNCCRT_IN#

MiTac Secret

Confidentia

l Docum

ent


107

7.4 External Monitor No Display -2There is no display or picture abnormal on CRT monitor, but it is OK for LCD.

CRT_RED

CRT_GREEN

CRT_BLUE

1

2

CON_RED

CON_GREEN

CON_BLUE

CRT_DDC_DATA

CRT_DDC_CLK 15

14U513

VIA VN896

North Bridge

P6

J501

P10

External CR

TC

onnector

CON_DDCK

13CON_HSYNC

CON_VSYNC

12CON_DDDA

Change to

Change to

Change to

Change to

CRT_VSYNC

CRT_HSYNC

Change to

Change to

Change to

U10KBC

W83L951D

P19

CRT_IN#CRT_IN#

3

11

MiTac Secret

Confidentia

l Docum

ent


108

7.5 Memory Test Error -1Extend DDR2 SO-DIMM is test error or system hangs up.

Memory Test Error

One of the following components or signals on the motherboard may be defective ,Use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.

TestOK? Correct it.

Yes

No

Parts:

U513U19U514J513J515Q10A/BR249R250R251R252R254R253R256R255

Signals:

1. Check the extend SO-DIMM module is installed properly. ( J513, J515)

2. Confirm the SO-DIMM socket (J513, J515) is ok, no band pins.

If your system host bus clock running at 533/667 MHZ then make sure that SO-DIMM module meet require of PC4200/PC5400.

TestOK?

Yes

No

DDR_A_DQ[0..63]DDR_A_DM[0..7]DDR_A_BS[0..2]DDR_A_MA[0..13]DDR_A_RAS#DDR_A_CAS#DDR_A_WE#DDR_CS#[0..3]DDR_CKE[0..3]DDR_ODT[0..3]DDR_A_DQS[0..7]DDR_A_DQS#[0..7]DDR_CLK[0..3]+DDR_CLK[0..3]-


ReplaceMotherboard

Replace the faulty DDR2 SODIMM module.

SMB_DATASMB_CLK+1.8V+3VSMiTac Secret

Confidentia

l Docum

ent


109

7.5 Memory Test Error -2Extend DDR2 SO-DIMM is test error or system hangs up.

J513

P7

DIM

M1

U514

South BridgeVIA VT8237A

SMBDATA

SMBCLK

J515

P7

DIM

M0

P12

U513

North Bridge

VIA VN896

P5

DDR_A_RAS#, DDR_A_CAS#, DDR_A_WE#

DDR_A_MA[0..13], DDR_CKE[0..3], DDR_CS#[0..3]

DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7]

DDR_A_DM[0..7], DDR_A_BS[0..2], DDR_ODT[0..3]

SMB_DATA

SMB_CLK

SMB_DATA

SMB_CLK

U19

ICS9P956

P8DDR_CLK[0,1]+, DDR_CLK[0,1]-

DDR_CLK[2,3]+, DDR_CLK[2,3]-











Change to

Change to

MiTac Secret

Confidentia

l Docum

ent


110

7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error -1Error message of keyboard or touch-pad test error is shown or any key does not work.

Keyboard(K/B) or Touch-Pad(T/P)Test Error

Try another known good Keyboard or Touch-pad.

TestOk?

Replace the faulty Keyboard or Touch-Pad.

CheckJ2, J3

are cold solder?

Yes

No

One of the following parts or signals on the motherboardmay be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.

Yes

No

Re-soldering.

Parts

U514U10J2J3SW6SW7EL30EL31EL26

Is K/B or T/Pcable connected to notebook

properly?

Yes

NoCorrect it.


ReplaceMotherboard Signals

+5VKI[0..7]KO[0..15]T_CLKT_DATATP_CLKTP_DATATP_LEFTTP_RIGHTLPC_AD[0..3]LPC_FRAME#

MiTac Secret

Confidentia

l Docum

ent


111

7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error -2Error message of keyboard or touch-pad test error is shown or any key does not work.

U10

Keyboard BIOS

W83L951DT_CLK

T_DATA

48

47

11,12TP_CLK

TP_DATA 9,10

U514South Bridge

VIA VT8237A

P11

SERIRQ 54

J3

+5V

Touch-Pad

P20

TP_RIGHT 5,6

7,8TP_LEFT

LPC_AD[0..3]

P19

KI[0..7]

KO[0..15]

3..10

11..26

InternalKeyboard Connector

P19

J295..102

79..94

KBD_US/JP＃ 2

56..59

SW61

45

32

145

3

SW72

RSMRST#

LPC_FRAME#

30

52

77

1,2

P12

Change to

Change to

SW_LEFT

SW_RIGHT

MiTac Secret

Confidentia

l Docum

ent


112

7.7 Hard Disk Drive Test Error -1Either an error message is shown, or the drive motor spins non-stop, while reading data from or writingdata to hard disk.

Hard Disk Drive Test Error

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.Yes

No

Re-bootOK? Replace the faulty parts.

1. Check if BIOS setup is OK?.2. Try another working drive.

Check the system driver for proper installation.

No

Re - TestOK? End

Yes


Parts: Signals:

U514J510J509R269R268R267R266

SATA_RX0+/-SATA_TX0+/-HDD_DD[0..15]IDE_PDD[0..15]HDD_DA[0..2]IDE_PDA[0..2]IDE_PDCS[1,3]#HDD_DCS[1,3]#IDE_PDACK#HDD_DACK#

ReplaceMotherboard

IDE_PIRDYHDD_IRDYIDE_PIRQHDD_IRQHDD_DIOR#IDE_PDIOR#HDD_DREQIDE_PDREQIDE_PDIOW#HDD_DIOW#

MiTac Secret

Confidentia

l Docum

ent


113


SATA_TX0-

SATA_TX0+

SATA_RX0-

SATA_RX0+U514

South Bridge

VIA

VT8237A

P12

J510

P13

SAT

A H

DD

Connector

MiTac Secret

Confidentia

l Docum

ent


114


U514

South Bridge

VIA

VT8237A

IDE_PDCS1#

HDD_DA[0..2]

HDD_DCS1#

Primary E

IDE

Connector

27~42

18

7

14

22

+5VS 3,4

HDD_DD[0..15]

HDD_DREQ

HDD_DCS3#

HDD_IRQ

HDD_DIOW#

HDD_DIOR# 20

24

J509

P11

P13

IDE_PDD[0..15]

IDE_PDREQ

IDE_PDA[0..2]

HDD_IRDY IDE_PIRDY

IDE_PDCS3#

IDE_PIRQ

IDE_PDIOW#

IDE_PDIOR#

9,10,12

8

Change to

Change to

Change to

Change to

Change to

Change to

Change to

Change to

Change to

Change to IDE_PDACK# 20HDD_DACK#

MiTac Secret

Confidentia

l Docum

ent


115

7.8 ODD Drive Test Error -1An error message is shown when reading data from ODD drive.

ODD Drive Test Error

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement.

Yes

No

TestOK? Replace the faulty parts.

1. Try another known good compact disk.2. Check install for correctly.

Check the ODD drive for proper installation.

No

Re - TestOK?

Yes


End

ReplaceMotherboard

Parts: Signals:

U514U511J511R648Q17AQ17B

+5VS+3VSODD_DD[0..15]ODD_DA[0..2]ODD_DCS[1,3]#ODD_DIOR#ODD_DIOW#ODD_DACK#ODD_IRDYODD_DREQODD_RST#ODD_LED#ODD_IRQ

MiTac Secret

Confidentia

l Docum

ent


116

7.8 ODD Drive Test Error -2An error message is shown when reading data from ODD drive.

5

6..21

31,33,34

29

28

24

25

22

27

35,36

ODD_RST#Refer Section 8.2(No display-3)

J511

P13

OD

D C

onnector

ODD_LED#+3VS

37

D5CL-190G

+5VS 32

U514

South Bridge

VIA

VT8237A

P12

ODD_IRQ

ODD_DIOR#

ODD_DIOW#

ODD_DREQ

ODD_DACK#

ODD_IRDY

ODD_DA[0..2]

ODD_RST#

ODD_DD[0..15]

ODD_DCS[1,3]#

ODD_IRQ

ODD_DIOR#

ODD_DIOW#

ODD_DREQ

ODD_DACK#

ODD_IRDY

ODD_DA[0..2]

ODD_DD[0..15]

ODD_DCS[1,3]#

D7BAT54A

MiTac Secret

Confidentia

l Docum

ent


117

7.9 USB Port Test Error -1An error occurs when a USB I/O device is installed.

Re-testOK?

TestOK?

USB Port Test Error

Check if the USB device is installed properly.

No

Yes

No

Yes

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.

Replace another known good USBdevice.


Correct it.

Correct it.

ReplaceMotherboard

Signals:

USBP0+/-USBP1+/-USBP2+/-USBP3+/-+5V_USB_1+5V_USB_2+5V_USB_3+5V_USB_4USB_OC0USB_OC1SW_VDD3

Parts:

U514U505U4J504J506J503EL509EL510EL521EL508EL2EL516EL3EL515

MiTac Secret

Confidentia

l Docum

ent


118

7.9 USB Port Test Error -2An error occurs when a USB I/O device is installed.

U514

South Bridge

VIA VT8237A

P11

USB

Port

J5032

P14

+5V_USB_4

USBP3-

USBP3+

USB

Port

J506

3

2

1

+3V

USB

Port

J504

A2

3

2

P14

P14

3

USBP3-

USBP3+

1

+5V_USB_3USB_OC1

U505

P14VIN

4VOUT 5

1 CEGND

3FLG

U10Page 19 +5V

SW_VDD3

USBP2-

USBP2+

USBP2-

USBP2+

USBP0-

USBP0+

USBP1-

USBP1+ A3

USBP0-

USBP0+

USBP1-

USBP1+

U4

P14VIN

4VOUT 5

1 CEGND

3FLG

U10Page 19 +5V

SW_VDD3

+3V +5V_USB_1

+5V_USB_2

1

A1

USB_OC0

MiTac Secret

Confidentia

l Docum

ent


119

7.10 Audio Test Error -1No sound from speaker after audio driver is installed.

Re-test OK?

Test OK?

Audio Test error

1. Check if speaker cables are connected properly.

2. Make sure all the drivers are installed properly.

Try another known goodspeaker, CD-ROM.


Yes

Yes

Check the following parts for cold solder or one of the following parts on the motherboard may be defective,use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement.

1.If no sound causeof line out, check the following parts & signals:

2. If no sound cause of MIC, check the followingparts & signals:

No

NoParts:

U10U14U17J519J518J512EL537EL536EL539EL538EL24EL27

Signals:

ROUTP/NLOUTP/NHP_OUTR/LHP_SENSE#SPK_OFFAMP_RIGHTAMP_LEFTHP_RIGHTHP_LEFT

Parts:

U17U514U10U14J514EL34EL35R236R231R238R226

Signals:

+5VS+3VSMIC1_VREFRMIC1_VREFLMIC1_RMIC1_LMIC_SENSE#ACZ_RST#ACZ_SYNCACZ_SDIN0ACZ_BITCLKACZ_SDOUT

Correct it.

Correct it.

ReplaceMotherboard

MiTac Secret

Confidentia

l Docum

ent


120

7.10 Audio Test Error -2 (Audio In)No sound from speaker after audio driver is installed.

41 HP_RIGHT

39 HP_LEFT

HP_RIGHTTo next page

HP_LEFTTo next page

U17

Audio Codec

ALC268

U514

South Bridge

VIAVT8237A SPK_OFF

To next page

DVDD1,21,9

P17

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

ACZ_SDIN0

ACZ_BITCLK

8

5

10

11

6

P12 28

21

36 AMP_RIGHT

35 AMP_LEFT

+3VS

AMP_RIGHTTo next page

AMP_LEFTTo next page

KBC_BEEP 12PCBEEP

PC_BEEP

U10

KBCW83L951D

P19

72

ExternalMIC

J514

1263

5

4

P17

78

32 MIC1_VREFR

MIC1_VREFL

MIC1_VREFR

MIC1_VREFL

22 MIC1_R

MIC1_L

MIC_SENSE#13

HP_SENSE#From next page

SENSE_A Change to

Change to

MiTac Secret

Confidentia

l Docum

ent


121

7.10 Audio Test Error -3 (Audio Out)No sound from speaker after audio driver is installed.

U14

Audio

Amplifier

APA2056

P18

22

21

ROUT+

ROUT-

HP_RIGHTFrom previous page

4

6INL_H

INR_H

+5V 19 HVDD

26

8

9

LOUT+

LOUT-INR_A

AMP_LEFTFrom previous page

3

5 INL_A

SPK_OFFFrom previous page

Internal SpeakerConnector

J5191

2

HP_LEFTFrom previous page

AMP_RIGHTFrom previous page

SPK_OFF#

ROUTP

ROUTN

LOUTP

LOUTN

HP Jack

J512

1263

54

P18

78

HP_OUTR

HP_OUTL

HP_SENSE#To previous page

17

J5181

2 P18

P18

18

Change to

HP_RIGHT

HP_LEFT

AMP_LEFT

AMP_RIGHT

MiTac Secret

Confidentia

l Docum

ent


122

7.11 LAN Test Error -1An error occurs when a LAN device is installed.

LAN Test Error

Yes

No

TestOK?

No

Check if BIOS setup is ok.

Re-testOK?


Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscopeto check the following signal or replace the parts one at a time and test after each replacement.

Parts: Signals:

1.Check if the driver is installed properly.2.Check if the notebook connect with the

LAN properly.

Yes

U514U506U503J502EL518EL519X501R519RP503

RJ45_PJ7RJ45_PJ4PJRX+/-PJTX+/-LAN_TXP/NLAN_RXP/NLAN_DATAIOLAN_DCLKLAN_MTXCLAN_MRXD[0..3]LAN_MTXD[0..3]LAN_MTXELAN_COLLAN_CRS

Correct it.

Correct it.

ReplaceMotherboard

LAN_MRXCLAN_MRXDVLAN_MRXER+3VMiTac Secret

Confidentia

l Docum

ent


123

7.11 LAN Test Error -2An error occurs when a LAN device is installed.

C5260.1U

R518300

U506

LAN

Controller

VT6103L

P16

+3V20,21,22,23

40

39

2 1

C53322P

C52922P

X50125MHZ

XI

XO

U503

NS681680P

8

P16

PJTX+

PJRX+

PJTX-

PJRX-

10

9

16

15

8

7

6

3

P16

J5027

RJ45 LA

N C

onnector

LAN_TXP

LAN_TXN

35

34

LAN_RXP

LAN_RXN

27

262

1

6+3V_LAN

EL520130Z/100M

U514

South Bridge

VIA

VT8237A

P11

LAN_DATAIO

LAN_DCLK

LAN_MRXDV

43

44

3

LAN_MRXD[0..3] 45..48

LAN_COL

LAN_CRS

LAN_MTXC

15

16

9

LAN_MTXD[0..3] 11..14

LAN_MTXE 10

LAN_MRXC 4

LAN_MRXER 5

R519300K

11

14

R50675

R50575

R50375

R50475

C5041000P

RJ45_PJ4

RJ45_PJ7

4,5

1,2

MiTac Secret

Confidentia

l Docum

ent


124

7.12 Mini Express (Wireless) Socket Test Error -1An error occurs when a wireless card device is installed.

1. Check if the wireless card device is installed properly.

2. Confirm wireless driver is installed ok.

TestOK?

Re-testOK?

Yes

No

Yes

No

Change the faulty part then end.

Try another known good wireless card device.

Correct itReplace

Motherboard



+3VSPCIEREQ_MINI#PCIECLK_MINI+/-SIO_48MPCI_EXP_RX0+/-PCI_EXP_TX0+/-LPC_AD[0..3]LPC_FRAME#LPC_DRQ#0SERIRQLPC_DBG_CLKWLAN_PD#

USBP4+/-SMB_CLKSMB_DATA

Mini Express (Wireless) Socket Test Error

U512U513U514J516C605C605C606R653.R654R655R656R657

Parts: Signals

R658R659R624R628

MiTac Secret

Confidentia

l Docum

ent


125

7.12 Mini Express (Wireless) Socket Test Error -2An error occurs when a wireless card device is installed.

J516

Mini E

xpress (Wireless) C

onnectorU514

South Bridge

VIA VT8237A

P11

P15

U512

ClockGenerator

ICS953009

P8

PCIECLK_MINI-

PCIEREQ_MINI#35 7

PCIECLK_MINI+

37

38

11

13

SIO_48M 17

31

48

SMB_CLK

SMB_DATA

30

32

PCI_EXP_TX0-

PCI_EXP_TX0+

PCI_EXP_RX0-

PCI_EXP_RX0+

LPC_AD[0..3]

LPC_FRAME#

LPC_DRQ#0

SERIRQ

WLAN_PD#

USBP4-

USBP4+

31

33

23

25

37..43

45

47

49

20

36

38

MINIPCIE_PCIRST#Refer Section 8.2(No display-3)

22

U513North Bridge

VIAVN896

P6

P12

24

MiTac Secret

Confidentia

l Docum

ent


126

7.13 Express Card Socket Test Error -1An error occurs when a express card device is installed.

1. Check if the express card device is installed properly.

2. Confirm express card driver is installed ok.

TestOK?

Re-testOK?

Yes

No

Yes

No

Change the faulty part then end.

Try another known goodexpress card device.

Correct itReplace

Motherboard



Express Card Socket Test Error

Parts: Signals

+3V+3VS+3.3VS_CARDUSBP5+/-SMB_CLKSMB_DATAPCIEREQ_NCARD#PCIECLK_NCARD+/-PCI_EXP_RX16+/-PCI_EXP_TX16+/-CPUSB#

CARD_RST#CPPE#PCIE_WAKE_UP#NCARD_TX16+/-

U512U513U514U516U20J4C322C333R278R693

MiTac Secret

Confidentia

l Docum

ent


127

7.13 Express Card Socket Test Error -2An error occurs when a express card device is installed.

U20

G577D5U

P151SB_CARD_PCIRST# 8

11

12

CARD_RST#

CPUSB#

CPPE#

13

4

17U514

South Bridge

VIA VT8237A

U512

ClockGenerator

ICS953009

P8

PCIECLK_NCARD-

PCIEREQ_NCARD#36 16

PCIECLK_NCARD+

41

42

18

19

31

48

SMB_CLK

SMB_DATA

7

8

PCI_EXP_TX16-

PCI_EXP_TX16+

PCI_EXP_RX16-

PCI_EXP_RX16+

PCIE_WAKE_UP#

USBP5-

USBP5+

24

25

21

22

11

2

3

U513North Bridge

VIAVN896

P6

P11

J4

Express C

ard Connector

P15

P12

NCARD_TX16-

NCARD_TX16+

Change to

Change to

4

53

+3VU516

AHC1G08DBV

1

2PCI_RESET#

PCIECLK_NCARD-

PCIEREQ_NCARD#

PCIECLK_NCARD+

SMB_CLK

SMB_DATA

PCIE_WAKE_UP#

USBP5-

USBP5+

MiTac Secret

Confidentia

l Docum

ent

Reference Material

Intel Merom Processor Intel.Inc

VIA VN896 North Bridge VIA.Inc

VIA VT8237A South Bridge VIA.Inc

8515 Hardware Engineering Specification Technology.Corp./MITAC

System Explode Views Technology.Corp./MITAC

SERVICE MANUAL FOR 8515SERVICE MANUAL FOR 8515SERVICE MANUAL FOR 8515

Sponsoring Editor : Ally Yuan

Author : Guangna Zhang

Publisher : MiTAC Technology Corp.

Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C

Tel : 086-512-57367777 Fax : 086-512-57385099

Second Edition : Oct.2007

E-mail : Ally.Yuan @ mic.com.tw

Web : http: //www.mitac.com http: //www.mtc.mitacservice.com

Sponsoring Editor : Ally Yuan

Author : Guangna Zhang

Publisher : MiTAC Technology Corp.

Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C

Tel : 086-512-57367777 Fax : 086-512-57385099

Second Edition : Oct.2007

E-mail : Ally.Yuan @ mic.com.tw

Web : http: //www.mitac.com http: //www.mtc.mitacservice.com

Documents

8515 Service Ma8515 service manuanual (1)