A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

1710 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007

A Wideband �� Digital-RF Modulator forHigh Data Rate Transmitters

Albert Jerng, Member, IEEE, and Charles G. Sodini, Fellow, IEEE

Abstract—A wideband software-defined digital-RF modulatortargeting Gb/s data rates is presented. The modulator consists ofa 2.625-GS/s digital�� modulator, a 5.25-GHz direct digital-RFconverter, and a fourth-order auto-tuned passive LC RF band-pass filter. The architecture removes high dynamic range analogcircuits from the baseband signal path, replacing them withhigh-speed digital circuits to take advantage of digital CMOSscaling. The integration of the digital-RF converter with anRF bandpass reconstruction filter eliminates spurious signalsand noise associated with direct digital-RF conversion. An ef-ficient passgate adder circuit lowers the power consumption ofthe high-speed digital processing and a quadrature digital-IFapproach is employed to reduce LO feedthrough and imagespurs. The digital-RF modulator is software programmable tosupport variable bandwidths, adaptive modulation schemes, andmulti-channel operation within a frequency band. A prototypeIC built in 0.13- m CMOS demonstrates a data rate of 1.2 Gb/susing OFDM modulation in a bandwidth of 200 MHz centered at5.25 GHz. In-band LO and image spurs are less than 59 dBcwithout requiring calibration. The modulator consumes 187 mWand occupies a die area of 0.72 mm2.

Index Terms—Delta-sigma, digital-IF, DRFC, OFDM, quadra-ture modulator, software radio, wideband.

I. INTRODUCTION

NEXT-GENERATION wireless systems aim to providehigh data rates on the order of 1 Gb/s in order to sup-

port demand for high-speed mobile Internet applications. Inaddition to increasing channel bandwidths, wireless systemsare employing techniques such as orthogonal frequency-divi-sion multiplexing (OFDM) and modulation schemes such as64-QAM to pack more bits per hertz. The system choices leadto higher signal-to-noise ratio (SNR) requirements and higherpeak-to-average power ratios (PAPR) in the signals. Thus,higher dynamic range is required in the circuits.

The 802.11n standard for wireless local area networking(WLAN) targets a maximum data rate of 540 Mb/s. UWBsystem proposals under the 802.15.3a task group are targetingdata rates up to 1.32 Gb/s using channel bandwidths of 528 MHzfor short-range, high rate wireless personal area networks [1].Recent allocation of over 5 GHz of contiguous bandwidth inthe unlicensed 60 GHz band enables transmission of muchhigher data rates. The multitude of wireless standards requires

Manuscript received November 20, 2006; revised January 30, 2007. Thiswork was supported by the MIT Center for Integrated Circuits and Systems.Chip fabrication was provided by IBM Microelectronics.

A. Jerng was with the Massachusetts Institute of Technology, Cambridge, MA02139 USA. He is now with Broadcom, San Diego, CA 92127 USA.

C. G. Sodini is with the Massachusetts Institute of Technology, Cambridge,MA 02139 USA.

Digital Object Identifier 10.1109/JSSC.2007.900255

Fig. 1. Conventional and proposed modulator architectures.

distinct radio designs for each set of specifications. A wide-band, programmable RF modulator with high dynamic range isa key building block for a universal transmitter targeting futurehigh data rate systems.

The conventional I–Q modulator, shown in Fig. 1, consistsof a digital-to-analog converter (DAC), analog filter, and analogmixer. The DAC and analog filter become more difficult to de-sign as the bandwidth and dynamic range requirements of thetransmitter increase. At high frequencies, timing errors and non-linear capacitances limit DAC dynamic range [2], rather thanstatic DC errors. Power consumption in the analog reconstruc-tion filter increases proportionally to the signal bandwidth fora constant dynamic range [3]. The scaling of CMOS transistorsand supply voltages creates further challenges from the stand-point of dynamic range. Mismatch between I and Q paths andDC offsets cause modulator image and local oscillator (LO)leakage signals, respectively.

The proposed wideband digital-RF modulator, shownin Fig. 1, consists of oversampling I and Q digital mod-ulators, and a quadrature digital-RF converter with integratedRF bandpass filter. The digital-RF modulator replaces highdynamic range analog circuits with high-speed digital circuits,and active analog lowpass filters with a passive RF bandpassfilter. In this architecture, no analog impairments are presentin the I–Q baseband signal path. Thus, analog design issuessuch as noise/linearity tradeoffs, DC offsets, and I–Q matchingare eliminated. Unlike the conventional I–Q modulator, thedigital-RF modulator benefits from digital CMOS scaling sincethe power and area of the high-speed modulators will de-crease as channel lengths and supply voltages are reduced. Thedigital-RF converter (DRFC) building block [4], [5] combinesthe functionality of a DAC and mixer, and enables greaterintegration. Passive RF filtering is attractive because it has highdynamic range and consumes no power.

The fundamental difficulty with direct digital-RF conversion[4], [5] is the transmission of spurs outside the signal band thatare difficult to filter at RF frequencies. The frequency spec-trum of the digital input to the DRFC repeats at multiples ofthe sampling frequency. Clock images and quantization noise

0018-9200/$25.00 © 2007 IEEE

JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS 1711

Fig. 2. Quadrature digital-RF converter core.

are up-converted without any filtering besides the sinc responseassociated with the zero-order hold in the digital-RF interface.In previous work on direct digital-RF conversion [4]–[6], addi-tional off-chip filtering is required to avoid transmitting out-of-band spurs.

In this work, the spurious problem is solved through the in-tegration of a high- passive LC bandpass filter into the loadof the digital-RF conversion circuit. As signal bandwidths in-crease, active analog filters consume more power for a givendynamic range, while on-chip passive LC bandpass filters be-come feasible due to a reduction in required . Thus, direct dig-ital-RF conversion is attractive for wideband systems.

The new contributions of this work are the application of thedirect DRFC concept towards wideband systems, and the inte-gration of an auto-tuned RF bandpass filter and a high-speeddigital modulator in the designed digital-RF modulator.Due to its wideband capability, the digital-RF modulator can besoftware-defined to transmit multiple frequency channels withina band, with variable bandwidths and modulation schemes whileusing a fixed LO. The modulator can be used to transmit in aband of spectrum on an adaptive basis, depending on wirelesschannel conditions and interferers, or upon the specifications ofa given standard. In the following sections, the system and cir-cuit design details will be discussed, experimental results willbe presented, and conclusions will be made.

II. MODULATOR ARCHITECTURE

A simplified schematic of the multi-bit DRFC core is shownin Fig. 2. Each unit cell, similar to [5], consists of a currentsource, a differential pair driven by an LO signal, and a differen-tial current-steering switch. The converter cells share a commoncascode device that isolates the output signal from the switches,preventing data-dependent switching that causes distortion. Thedifferential LO current in each unit cell is multiplied by 1 or

1, depending on the digital input bit. Summation of the unitcell LO output currents yields a modulated RF signal that isobscured by a large amount of quantization noise. RF band-pass reconstruction filtering removes the out-of-band quantiza-tion noise.

Fig. 3. Aliasing problem in up-conversion.

The DRFC performs multiplication of the sampled and heldbits with the LO signal. In the frequency domain, this corre-

sponds to a convolution of the frequency spectra of the respec-tive signals, as depicted in Fig. 3 for DC inputs. In digital-RFconversion, aliasing of quantization noise and sampling clockimages can occur. Quantization noise and clock images fromthe convolution with spill into the positive frequencyspectrum, corrupting the signal spectrum centered at . Like-wise, noise and images from the convolution with spills intothe negative frequency spectrum. The only filtering that occursbefore the convolution is the sinc response associated with thezero-order hold in the digital-RF interface.

Aliased clock images will appear as an image signal in the RFpassband, degrading the achievable image rejection of the mod-ulator. The finite image rejection, however, is correctable. Sincethe signal is known and the sinc transfer function is known, themagnitude and phase of the aliasing clock images are knownas well. For moderate oversampling ratios, the image signal issmall, and pre-distortion of the digital input signal effectivelyremoves the aliasing images. Aliased quantization noise, on theother hand, can degrade the in-band SNR of the signal. In orderto prevent degradation of SNR, the following condition must bemet between and :

(1)

By satisfying (1), only quantization noise notches will aliasinto the RF passband, having negligible impact on in-band SNR.In practice, device mismatches in the lower differential paircause leakage from the digital input port to the output. Thedigital inputs contain large amounts of quantization noise at oddmultiples of . This noise leaks to the output and lies in thesignal passband when is chosen to be an odd multiple of

. Thus, (1) should be modified to

(2)

A. Co-Design of NTF and BPF

The dynamic range of a modulator is a function of itsoversampling ratio (OSR). In a RF modulator, the OSR canbe related to the of the RF bandpass filter (BPF).


The of an LC bandpass filter is limited by and re-lated to the system center frequency and RF bandwidththrough

(3)

Meanwhile, the OSR is related to the oversampling clock fre-quency and RF bandwidth through

OSR (4)

Expressing in terms of in (4), and using (2) to substituteinto (3), we find a relation between OSR and .

OSR (5)

Equation (5) says that the oversampling ratio of the mod-ulator is constrained to be less than the of the RF BPF. Intu-itively, a high OSR corresponds to a narrower bandwidth fora given clock frequency and LO frequency. A narrower band-width requires a higher filter. In current technologies,ranges from 10–25, depending on the top-level metal’s resis-tance and distance to the substrate.

A second-order, 1-bit modulator is an ideal modulator choicedue to its inherent linearity and stability. However, for lowOSR in the range of 10–16, a second-order, 1-bit modulator islimited to an SNR of around 40 dB [7]. A higher order 1-bitmodulator can provide higher SNR, but increases the slopeat which out-of-band quantization noise rises, making thedesign of an on-chip RF BPF much more difficult. A low-ordermulti-bit modulator, on the other hand, provides good SNRperformance for moderate OSR, and also reduces the amountof out-of-band quantization noise. The multi-bit modulatorrequires good matching between unit cells, but is essential forlowering the required attenuation and order of the RF BPF.

B. Targeted System Parameters

A prototype digital-RF modulator targets Gb/s data ratesusing OFDM modulation with 1-MHz sub-carrier spacing and200-MHz RF bandwidth centered at 5.25 GHz. If 256-QAMmodulation is used on each sub-carrier, a maximum data rateof 1.6 Gb/s can be transmitted. Assuming a required SNR of30 dB for 256-QAM and a PAPR of 15 dB for the 200 sub-carrierOFDM signal, the modulator should provide an SNR 45 dB.With an LO frequency at 5.25 GHz, is chosen to be 2 in (2)so that 2.625 GS/s and OSR 13.

Table I lists several topologies and their simulated SNRwith OSR 13. The 1-bit topologies all use optimized zerolocations [8]. Matching requirements to maintain the SNR ofthe modulator are based on Monte Carlo simulations inMATLAB using random mismatches with variance betweenunit elements. The results show that the second-order 3-bit mod-ulator maximizes the in-band SNR and also relaxes the RF fil-tering requirements.

Fig. 4 plots the output spectrum of a second-order, 3-bitRF modulator before and after filtering with a fourth-orderBessel RF BPF with bandwidth of 260 MHz. Out-of-bandquantization noise is low enough to pass the spurious emis-sion requirements outside the 5.15–5.35 GHz UN-II band.

TABLE ISIMULATED �� SNR WITH OSR = 13

Fig. 4. RF output spectrum using second-order, 3-bit�� modulator.

According to the FCC, spurious emissions must be below27 dBm/MHz outside the 5.15–5.35 GHz UN-II band [9].

The limits drawn assume a maximum power of 20 dBm anda PAPR of 16 dB for the final transmit signal out the antenna.In Fig. 4, the output signal is a pure sine wave with PAPR of3 dB and its power is normalized to 0 dB. It then follows thatthe spurious emissions limits are 60 dBc/MHz.

III. QUADRATURE DIGITAL-IF

The in-band RF output spectrum of the digital-RF mod-ulator can still be degraded by LO and image spurs due to LOleakage and quadrature LO phase mismatches. The direct mod-ulator architecture can be reconfigured into a digital-IF trans-mitter by adding a digital-IF quadrature up-converter after the

digital modulators. LO and image spurs from the digital-RFconverter will be separated from the RF output by and

, respectively. If the IF frequency is high enough, both sig-nals will be filtered by the RF BPF. When implemented digi-tally, the IF quadrature modulator will not introduce any spursof its own.

One can implement a multiplier-free quadrature modulationand eliminate the power consumption of the high-speed digitalmixer by choosing the IF frequency to be , [10], sincequadrature digital sines and cosines at only have valuesof 1, 1, or 0. Unfortunately, conventional digital-IF up-con-version at of a modulated digital baseband signalcauses severe aliasing of quantization noise into the IF signalpassband. This occurs because the baseband spectrum hasnoise peaks at while the positive and negative IF fre-quencies are separated by . A plot of a digital-IF spec-trum at is shown in Fig. 5.


Fig. 5. Digital-IF output spectrum with f = f =4.

Fig. 6. Quadrature digital-IF �� RF modulator.

A quadrature digital-IF topology, shown in Fig. 6, greatlyreduces the noise aliasing by cancelling either the positive ornegative IF sideband through the use of two sets of quadra-ture modulators providing quadrature IF outputs. The cancella-tion is accomplished in the subsequent RF up-conversion of thequadrature DRFC and is affected by non-ideal phase matchingof the quadrature LO signals driving the DRFC. MATLAB sim-ulations of the system in Fig. 6 benchmark the degradation inSNR due to quadrature LO phase inaccuracies when using asecond-order, 3-bit modulator. The results are plotted inFig. 7. The SNR remains above 50 dB for LO phase errorsless than 1.3 . Increasing the number of bits in the quantizerof the modulator reduces the level of out-of-band quanti-zation noise and can lower the sensitivity of the SNR to noisealiasing.

Bandpass modulation at can also be used to pro-vide a digital-IF output. The quadrature digital-IF topology waschosen because it easily enables multiplexing between a directmodulation architecture and a digital-IF architecture, and alsoreduces the order of the modulator compared to a bandpassarchitecture.

The following equations relate the IF, clock, and LO fre-quencies given a desired RF output frequency for a digital-IFarchitecture.

(6)

(7)

Fig. 7. SNR versus LO phase error for quadrature digital-IF.

For 5.25 GHz and 2.625 GHz, is offset to4.6 GHz (for upper-sideband mixing).A drawback of this frequency plan that was experimentally

observed is the presence of spurious energy at 5.25 GHz. Thehigh-speed digital circuits clocking at 2.625 GHz create asecond harmonic at 5.25 GHz. In order to prevent this spur,the clock frequency for the modulator can be offset from

. For example, the choice of 2.4 GHz sets600 MHz and 4.65 GHz.

When is no longer an integer multiple of , violating(1), aliasing of quantization noise is a concern. The amount ofaliasing depends on the magnitude of the quantization noiseappearing at 5.25 GHz, and the filtering provided by thefrequency response of a zero-order hold. The rectangular pulseimpulse response of a zero-order hold assumes infinitely fastclock edges. When considering the actual rise and fall times ofthe clock signal, the impulse response looks like a trapezoidalpulse. The frequency response of a trapezoidal pulse withsampling period and rise/fall time is

(8)

equals the multiplication of two sinc functions.The first sinc function has nulls at multiples of similar tothe ideal zero-order hold. The second sinc function has nullsat multiples of and adds additional attenuation at higherfrequencies. Fig. 8 compares the frequency responses of therectangular pulse with infinite rise/fall times and the trapezoidalpulse with rise/fall time of 75 ps.

We are interested in the attenuation provided at around11 GHz since and are separated by 10.5 GHz.

According to Fig. 8, the trapezoidal impulse response pro-vides 15 dB additional attenuation in the frequency range ofinterest. MATLAB simulations of Fig. 6 with 4.65 GHzand 2.4 GHz indicate an SNR of 38 dB with an idealrectangular pulse and an SNR of 53 dB with the trapezoidalpulse. Thus, in practice, can be offset slightly fromin the quadrature digital-IF modulator without substan-tial degradation in SNR. The quadrature digital-IF topologyapproaches the performance of an ideal transmitter where the


Fig. 8. Frequency response of zero-order hold.

RF output spectrum contains only the desired signal, with noLO feedthrough or image spurs.

IV. RF BANDPASS RECONSTRUCTION FILTER

The multi-bit modulator design allows a fourth-orderBessel bandpass filter with 260-MHz bandwidth at 5.25 GHzto meet out-of-band noise requirements. However, variationsin capacitance or inductance cause a shift in the filter centerfrequency and a large amplitude loss in the fixed RF bandwidthof the system. A practical realization must include an automaticcontrol loop to stabilize the filter center frequency over processand temperature variations.

A. 5.25-GHz Filter Design

A narrowband approximation to a bandpass ladder filtercan be realized with shunt LC resonator sections that arecapacitively coupled [11]. This topology minimizes the numberof inductors required in the filter. Further area reduction isachieved by converting the topology into its differential form.The coupled resonator design methodology follows in a manneranalogous to conventional ladder design using filter look-uptables [11]. Based on the normalized resonator quality factordefined as

(9)

the normalized coefficients of coupling , and normalizedsource and load values are tabulated for coupled ladderlowpass prototypes. In (9), is the filter bandwidth, isthe filter center frequency, and is the unloaded resonator .

For a particular filter order, there is a minimum required torealize the filter’s transfer function. The minimum unloaded res-onator required for a fourth-order Bessel BPF at 5.25 GHzwith bandwidth 260 MHz is [11]

(10)

A schematic of the filter is shown in Fig. 9. A three-turn dif-ferential inductor was designed and optimized for using theEM simulator Sonnet. The process featured a 4- m-thick top

Fig. 9. LC BPF schematic.

metal 7 layer and an M7–substrate spacing greater than 12 m.A ground shield consisting of strips of M1 was placed under-neath the inductor and connected to an AC ground to reducesubstrate losses. Simulated differential inductance and were2.2 nH and 26 at 5.25 GHz.

The resonator load capacitance is implemented usingPN-junction varactors to allow tunability of the filter. MIMcapacitors in series with the varactors linearize the varactorC–V characteristics. The PN varactor is configured with itscathode at a virtual ground point of the differential resonatorso that its parasitic substrate diode does not degrade resonator

. The filter is designed to tune from 4.8 GHz to 5.6 GHz, cor-responding to a tuning range of 8%. Parallel plate capacitorsusing the top two metal layers are utilized to implement thesmall 26.3-fF coupling capacitors. Minimizing resistance in thelayout connections to the varactors and inductors is critical formaintaining a high quality factor in the resonator.

B. Automatic Tuning Loop

Automatic frequency tuning can be implemented by config-uring a replica resonator or the filter itself as a voltage-controlledoscillator (VCO) and locking it to a separate reference frequencyin a phase-locked loop (PLL) [12]. These PLL tuning systemsare costly in terms of die area and circuit complexity.

This design adapts a tuning technique used in baseband filters[13] for use at RF frequencies. The tuning scheme takes advan-tage of the fact that the phase difference between filter inputand filter output is 90 at the center frequency. Fig. 10 showsa simplified block diagram of the self-tuning loop using single-ended signals. All circuits are implemented differentially andall signals are taken differentially except for the operationalamplifier (opamp) output. The filter input and output are coupledthrough small capacitors to a high-frequency phase detector.The differential outputs of the phase detector are applied to a dif-ferential-input single-ended-output opamp that drives the con-trol voltage of the varactors in the resonators. The feedback loopforces zero differential voltage between the phase detector out-puts, which corresponds to the condition of 90 phase differencebetween the phase detector inputs. Since the filter will always becentered at the system LO frequency, the 5.25-GHz LO signaldriving the digital-RF converter can be used to calibrate thefilter. The filter does not need to be reconfigured as an oscillator.Self-tuning avoids matching issues and adds minimal additional


Fig. 10. Tuning loop block diagram.

circuitry. Most importantly, the filter can be calibrated in itsactual circuit implementation within the integrated digital-RFconverter, including all parasitic effects of the circuit and layout.

The opamp is a basic two-stage Miller-compensated differ-ential-to-single-ended amplifier. It has a DC gain of 77 dB,unity-gain bandwidth of 2 MHz, and phase margin of 88 .For small excursions from the 90 condition, the effective feed-back factor in the loop is close to 1, and the settling time isapproximately 0.5 s. The phase detector circuit is based onthe use of a Gilbert-cell multiplier [14]. At high frequencies,the conventional Gilbert-cell multiplier suffers from phase mis-matches between its two unsymmetrical input ports. The mis-match arises from a difference in effective input capacitancebetween the bottom port and top port. A finite driving resis-tance causes a phase delay related to the RC product. If the twoports have a phase mismatch term , the multiplier will outputa non-zero DC voltage when its inputs are in quadrature. Byusing two Gilbert-cell multipliers with cross-coupled inputs asin Fig. 10, the DC term due to the phase mismatch can be can-celled by summing the outputs together.

Variations in tuning sensitivity and phase detector gain onlyaffect the DC gain of the feedback loop. DC offsets at the outputof the phase detector and the input of the opamp cause a finitephase error (from 90 ) based on the phase detector gain whenthe phase detector differential output is near zero. In this design,a DC offset of 20 mV can be tolerated at the input of the opampfor a 5-MHz error in the calibrated center frequency.

The coupled resonators ideally have identical resonance fre-quencies. Small mismatches in loading capacitances betweenthe input and output nodes of the filter can cause a differencein resonance frequencies and degrade the filter transfer func-tion. When a mismatch is present, the filter center frequencywill no longer correspond to the condition of 90 phase differ-ence between input and output. Routing lines to the filter inputand output must be carefully extracted and equalized during thelayout phase. The loading on filter input and output must alsobe equalized. Dummy transistor loads are placed on the outputnodes to match the cascode transistors from the DRFC that loadthe filter input nodes.

C. Distortion Versus Tunability

An important consideration in a tunable LC filter is distor-tion. As shown in Fig. 11, the voltage across the varactor variesas a function of the input signal driving the filter. This creates asignal-dependent capacitance that causes distortion. The magni-tude of the distortion products can be calculated by first writing

Fig. 11. Differential resonator with nonlinear C(V).

an equation for the tank capacitance as a function of the inputsignal using a power series expansion.

(11)

The analysis is greatly simplified by assuming that onlycontains frequencies of the input current signal. This assumptionis valid because the distortion products are much smaller thanthe fundamental frequency and will not influence C(V). One canthen derive an expression for the resonator current as a func-tion of the resonator voltage to determine the level of distortionproducts:

(12)

The relevant distortion products are those that fall into thepassband of the filter. Two-tone inputs at frequencies andcreate IM3 products due to nonlinearity at frequencies

and . In the differential implementation shown inFig. 11, the tank capacitance C(V) is an even function of thedifferential tank voltage. In other words,due to the symmetry of the circuit. Note that the differentialcapacitance C(V) in Fig. 11 is the series combination of C1,C2, CV1, and CV2. Since C(V) is an even function, only theeven powers of in (11) are required. Equation (11) and

can be substituted into (12), and thefollowing equation for can be written:

(13)

In (13), it is assumed that , and only the firstthree coefficients of C(V) are used. Near resonance,and will approximately cancel. The relevant terms fromthe multiplication in (13) for IM3 calculations are then

(14)


Given the voltage magnitude of the two tones, the powerratio between the IM3 tones and the fundamental tones is cal-culated to be

IM3(dBc) (15)

The IM3 depends on the second-order coefficient, , of thepower series expansion of C(V), and the effective resistanceof the tank at resonance. A higher tank will have higherand result in worse IM3 performance. This indicates a tradeoffbetween filter selectivity and filter distortion in tunable filters.A higher also causes worse distortion. In general, reducingthe tuning range of the filter will lower .

Using (15) and assuming a maximum expected differentialpeak voltage of 0.6 V in the filter, the IM3 products are calcu-lated to be 46.5 dBc with 0.3-V differential output for eachof the two fundamental tones. Circuit simulations in SpectreRFshowed the IM3 products to be 51 dBc under the same condi-tions. The tradeoff between tuning range and distortion can bealleviated by providing an additional coarse tuning capabilityusing switchable fixed capacitances [15]. This allows a reduc-tion in tuning sensitivity of the varactor which minimizes . Afurther refinement is to replace the analog varactor with a bankof digitally switchable capacitances, replace the opamp with acomparator, and modify the analog tuning loop to an all-digitaltuning loop.

D. Test Filter Measured Results

The performance of the filter and automatic tuning loopwas verified using an on-wafer probe test structure. Broadbandon-chip buffers resistively matched to 50 were used at theinput and output ports to interface to the filter. The test filterwas driven in current mode, in the same way it would be usedin the actual RF modulator. Measured filter responses withmanual tuning are plotted in Fig. 12. The filter tunes from4.8 to 5.4 GHz. The ideal response, assuming a resonator Qof 26, is plotted alongside the measured response centered at5.2 GHz. Resistive losses in the varactor and the metal routinglower the resonator to 20. As a result, the measured 3-dBfilter bandwidth is 280 MHz, slightly wider than the targeted260-MHz bandwidth.

In Fig. 13, tuning curves are plotted for both manual and au-tomatic tuning. In the case of automatic tuning, the input fre-quency to the filter is varied and the resulting tune voltage is readout. The results indicate excellent agreement between manualand automatic tuning curves, confirming proper operation of theauto tuning loop. The tuning algorithm, as proposed, digitallystores the calibrated tuning voltage using an ADC and register,and reapplies the voltage during normal circuit operation usinga DAC. The ADC and DAC do not require high speed or highresolution, and were not implemented on our test chip.

V. HIGH-SPEED DIGITAL DESIGN

A high clock frequency is used in the digital modulatorsto achieve high dynamic range and relax RF filtering require-ments. The drawback is high dynamic power consumption inthe digital processing. Optimizing the high-speed digital power

Fig. 12. Measured filter response for different vtune.

Fig. 13. Measured manual tuning and auto tuning curves.

consumption is important to justify replacing the analog circuitsused in conventional I–Q modulators.

A. Modulator Topology

A MASH topology [16], consisting of two cascadedfirst-order error feedback stages, implements second-ordernoise shaping and was chosen for its simplicity. A block dia-gram of the implementation is shown in Fig. 14. By placing allzeros of the noise transfer function at DC, multipliers requiringprecise coefficients are avoided, saving power. The critical pathconsists of a single 12-bit adder.

B. Low-Power Passgate Adder

A conventional static mirror adder requires extensivepipelining to operate at 2.5 GS/s in 0.13- m CMOS. A fastercarry chain can be designed using a passgate style adder whosecarry chain consists of one nMOS passgate per bit. The reducedlogic swing in the carry chain can be amplified back to fullCMOS levels using a differential sense-amplifier flip-flopscheme [17].

A simplified schematic of the nMOS passgate adder is shownin Fig. 15. The carry chain is implemented differentially. For

, CMOS transmission gates implement the XOR function. For, nMOS passgates are used since full logic levels are not re-

quired. In our implementation, the gate count is reduced by notusing logic to produce generate and kill signals from the adderinputs and . Instead, transmission-gate-based adder logic


Fig. 14. Second-order MASH error feedback topology.

Fig. 15. NMOS passgate adder simplified schematic.

is adopted where the output carry is either equal to the inputcarry or , depending on the value of [18]. A pair of nMOSpassgates with drains connected together provide two parallelpaths to implement the logic, minimizing the capacitance onthe critical carry chain nodes. The sense-amplifier flip-flop isa pMOS version of the modified SAFF design in [19]. It is de-signed for a delay of less than 170 ps for inputdifferential voltages as small as 200 mV.

The transistor-level schematic for a passgate adder cell isshown in Fig. 16. A reset technique is used to pull all carry chainnodes to ground through a small nMOS transistor during the firsthalf of the clock cycle [17]. This reduces the available time forcarry propagation to less than half the clock period (200 ps),but it also insures that all passgates start in their linear region.Given the typical delay of the sense-amplifier flip-flop drivingan adder input, the propagate signal gating the carry chain willnot be valid until approximately the end of the first half of theclock cycle anyway. When the carry chain nodes reset to ground,there is a possibility that the input may be shorted to groundthrough the passgate controlled by , which is not valid yet.In order to prevent current from flowing, a gated-clock versionof is used to open the passgate whenever the clock signalis high. The additional logic does not affect the resistance orcapacitance of the carry chain RC network. The adder consists

Fig. 16. Passgate adder cell.

TABLE IIADDER COMPARISON

mainly of static CMOS inverters and passgates. A 6-bit carrychain has a simulated worst case propagation delay of 72 ps.

A 12-bit adder was built using a two-stage pipeline of 6-bitnMOS passgate adders. This is an efficient choice since in the

modulator architecture, a delay element is required afterthe adder. Most of the pipelining flip-flops are absorbed into themodulator implementation at no cost. Simulation results com-paring the passgate adder to a 12-bit static mirror adder at 75 Cand 1.3-V supply using nominal process models are summa-rized in Table II. The mirror adder required a pipeline of six2-bit ripple carry adders. A static transmission-gate edge-trig-gered flip-flop is used to implement all pipeline delays. Powerconsumption numbers do not include the power needed to drivethe adder inputs, but do include the power consumed by theclock driver. Layout parasitics are extracted and included in thesimulations. Compared to the static mirror adder, the passgateadder dissipates less than half the power for the same simulationconditions.

C. Top-Level Implementation

A top-level digital block diagram is shown in Fig. 17. The dig-ital block takes I–Q digital data as input bits and outputs 3-bit, Iand Q, IF bitstreams. The I–Q processing consists of a 4interpolator, a second-order, 3-bit, digital modulator, and adigital up-converter with IF frequency of . The digital-IFfunction can also be bypassed, allowing the I and Q baseband

bits to directly drive the subsequent digital-RF converter.Thus, both homodyne and digital-IF transmitters are supported.

The quadrature digital-IF up-converter output bits alternatebetween I and Q at the sample rate . The bits are invertedevery two clock samples. The quadrature bitstreams are offsetby one clock sample, corresponding to a 90 phase shift at the


Fig. 17. Digital block diagram.

Fig. 18. Digital-IF up-converter implementation.

IF frequency of . The gate-level digital implementationis shown in Fig. 18. A transmission gate multiplexer controlledby a half-rate clock is used to swap between I and Q. It is at thefull sample rate. Another multiplexer, with one inverter in serieswith one of its transmission gates, is controlled by a quarter-rate clock to invert the bits every two clock samples. The entireblock can be bypassed with another multiplexer, which eitherdirectly routes I and Q to the output, or passes I and Q throughthe digital-IF up-converter. The up-converter block consumesmuch less power than the modulator.

VI. DRFC CIRCUIT DESIGN

A multi-bit DRFC is sensitive to mismatches betweenunit elements. Traditional DACs are characterized by metricssuch as differential nonlinearity (DNL) and integral nonlinearity(INL) at DC, and spurious-free dynamic range (SFDR) at highfrequencies. The output of a DRFC is a digitally modulated RFsignal. Element mismatches cause noise and distortion in the RFoutput spectrum. In this case, the signal-to-noise plus distortionratio (SNDR) is a more meaningful metric. Knowledge of thequantitative relation between element mismatch and SNDR isuseful to circuit designers.

Fig. 19. SNDR (mean) versus percent mismatch.

DAC mismatch effects have been analyzed extensively [2],[20]–[22]. The design of a DRFC introduces a new mismatchterm due to the need to match the high-frequency LO signalcurrent in amplitude and phase across all unit cell differentialpairs. LO phase mismatches can be treated as an effective am-plitude mismatch for small phase errors using the small angleapproximation.

(16)

A behavioral model of a multi-bit QDRFC was devel-oped in MATLAB to quantify the relationship between mis-match among DRFC unit cells and SNDR. It is assumed thatthe multiple sources of amplitude and phase mismatch are sta-tistically independent, and a single Gaussian random variableis used to model the mismatch. The 3-bit DRFC is pseudo-seg-mented using 7 unit cells. The MSB drives 4 unit cells in par-allel, the ISB drives 2 unit cells in parallel, and the LSB drives1 unit cell. In the model, a sample rate of 2.5 GS/s is used andthe data bits switch linearly with a rise/fall time of 50 ps.

Single-tone sine-wave inputs are used to characterize theSNDR performance. Fig. 19 plots the mean of the simulatedSNDR versus percent mismatch for a bandwidth of 200 MHz.Mismatch less than 1% is required to achieve an SNDR greaterthan 50 dB.

Gain mismatch requirements can be translated into phasematching requirements using (16). For a given LO frequency,an allowable timing spread for the LO signal can be derivedfrom the required phase matching. Fig. 20 plots the equivalenttiming spread versus effective gain mismatch for different LOfrequencies. As the LO frequency becomes higher, the allow-able timing spread of the LO signal becomes very small. For a5-GHz LO frequency, the timing spread needs to be less than250 fs to maintain SNDR greater than 50 dB. An advantage ofthe approach is that the number of DRFC unit cells is small.A 3-bit modulator requires only 7 unit cells, leading tosmall layout area and minimal timing spread in the LO signal.

Fig. 21 shows a circuit schematic of the DRFC unit cell anddata driver. Each unit cell is biased at 250 A, resulting in atotal current of 3.5 mA for the quadrature DRFC. Standard


Fig. 20. LO timing spread versus effective gain mismatch.

Fig. 21. DRFC unit cell and data driver.

techniques [20] are used to match the current sources to 0.5%based on values for and provided by the foundry.The gates of the cascode transistors are connected directly tothe supply voltage of 2.5 V. It is acceptable to use a minimumlength device for the cascode transistor since the maximumsource–drain voltage across the device is 0.8 V during circuitoperation. The biasing voltages are chosen to allow differentialvoltage swings of 0.6 Vpk-pk in both the LO signal and datasignals.

The data drivers consist of a latch and buffer, implementedusing source-coupled logic. The load resistance and buffer cur-rent are chosen to be 1.5 k and 400 A, respectively, providinga 0.6 Vpk-pk differential swing with approximately 75-ps tran-sition time. The three buffers drive different load capacitancesand need to be scaled to provide identical timing of their datasignals. The parasitic capacitances of the routing lines to theDRFC were actually larger than the input capacitance of theDRFC current-steering switches. Thus, the ISB and LSB bufferswere identical in size, and biased at 400 A each, while the MSBbuffer was biased at 500 A, accounting for its slightly largercapacitive load.

Fig. 22. Test chip block diagram.

VII. EXPERIMENTAL RESULTS

A prototype IC implemented in 0.13- m CMOS integratestwo high-speed digital modulators, a quadrature digital-RFconverter, an RF bandpass filter with auto-tuning circuitry, anda quadrature LO path with polyphase filter and LO limitingbuffers. A block diagram is shown in Fig. 22. The quadratureLO signals are generated with a two-stage RC-polyphase filter.All I/Os are shown single-ended, but are implemented differ-entially. Digital data is generated in MATLAB and loaded intothe RAM of a Xilinx Virtex-4 field-programmable gate array(FPGA). The FPGA provides 11-bit LVDS digital signals at

650 MS/s to the IC, where they are up-sampled by 4, filtered,and processed by the modulators. A digital control inputis used to select between direct up-conversion and digital-IFup-conversion. The IC was packaged in an 88-QFN packagewith exposed ground paddle.

All measurements are performed after filter calibration.Fig. 23 plots the output spectrum with a 12-MHz sine-waveinput using direct up-conversion. Measured LO feedthrough is

51 dBc, and measured image rejection is 46 dB. Spurs dueto harmonic distortion are less than 55 dBc. Fig. 24 showsthe output spectrum when using the digital-IF up-converter.The LO frequency is shifted to 5.85 GHz, while the clockfrequency is 2.4 GHz. The LO and IF image signals are nowout-of-band. In-band image noise is below the noise floor ofthe output spectrum. The largest spur is a third harmonic toneat 52 dBc that is due to random element mismatch in themulti-bit converter. Measured SNDR is 49 dB. Output power is

8 dBm, after accounting for board and cable losses.Fig. 25 shows a wideband plot with 2-GHz span, using direct

up-conversion. The bandpass filter is effective in attenuatingout-of-band quantization noise from the second-order, 3-bitmodulator. Fig. 26 shows the output spectrum of a 160-MHz256-QAM OFDM signal. The FCC spectral limits outside the5.15–5.35 GHz UN-II band are also shown, indicating that thespurious requirements are met. Fig. 27 and Fig. 28 show theoutput spectrum for a 20-MHz 64-QAM OFDM channel forthe 802.11a standard, and a pair of 20-MHz 256-QAM OFDMchannels.


Fig. 23. Measured output spectrum: direct up-conversion, 12-MHz sine-waveinput.

Fig. 24. Measured output spectrum: digital-IF, 12-MHz sine-wave input.

The error vector magnitude (EVM) of a 100-MHz 256-QAMOFDM signal was measured using a discrete receiver test plat-form from the MIT WiGLAN project. The receiver was usedto down-convert and digitize the RF output signal from thedigital-RF modulator. The digitized signal was then capturedusing an FPGA and processed with MATLAB scripts. Mea-sured SNR is plotted on a per sub-carrier basis in Fig. 29. TheWiGLAN testing platform SNR was limited to 30 dB by theresolution of the on-board ADC. The SNR of the digital-RFmodulator alone is estimated to be 30 dB. According to Fig. 29,almost every sub-carrier can support 64-QAM modulation whileseveral can support 256-QAM. Assuming 64-QAM modulationacross all 200 MHz, the presented modulator can transmit a datarate of at least 1.2 Gb/s over its intended bandwidth.

The power consumption and die area of the entire modulatoris summarized in Table III. All blocks use a supply voltageof 1.5 V except for the DRFC core. A die photo is shown

Fig. 25. Measured output spectrum: wideband plot.

Fig. 26. Measured output spectrum: 160-MHz 256-QAM OFDM signal.

Fig. 27. Measured output spectrum: 20-MHz OFDM channel for 802.11a.

in Fig. 30. The modulator consumes 187 mW and occupiesa die area of 0.72 mm . A general figure of merit (FOM)


Fig. 28. Measured output spectrum: pair of 20-MHz OFDM channels.

Fig. 29. SNR measurement using WiGLAN receiver.

TABLE IIIDIGITAL-RF MODULATOR POWER CONSUMPTION/DIE AREA

characterizing the energy/bit efficiency of a modulator is. For our modulator,

(17)

Since 2/3 of the power is consumed in the digital processing,this FOM can be expected to improve with digital processscaling.

Fig. 30. Die photo.

VIII. CONCLUSION

The digital-RF modulator is a power and area efficientmodulator for wideband systems. Measured results demonstratea 1.2-Gb/s data rate over 200-MHz RF bandwidth centered at5.25 GHz. Spurs associated with direct digital-RF conversionhave been eliminated through the integration of a high- ,self-tuned RF bandpass filter. The digital-RF modulator isamenable to digital CMOS scaling and software radio.

ACKNOWLEDGMENT

The authors are grateful to Prof. A. Chandrakasan and Prof.M. Perrott for their valuable suggestions and contributions tothis research, and to K. Tan for his help in measuring SNR.

REFERENCES

[1] High Rate Ultra Wideband PHY and MAC Standard, ECMA-368, Dec.2005 [Online]. Available: www.ecma-international.org

[2] W. Schofield, D. Mercer, and L. S. Onge, “A 16 b 400 MS/s DAC with< �160 dBm/Hz noise power spectral density,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, pp. 126–127.

[3] F. Rezzi, I. Bietti, M. Cazzaniga, and R. Castello, “A 70-mW seventh-order filter with 7–50 MHz cutoff frequency and programmable boostand group delay equalization,” IEEE J. Solid-State Circuits, vol. 32,no. 12, pp. 1987–1998, Dec. 1997.

[4] S. Luschas, R. Schreier, and H. Lee, “Radio frequency digital-to-analogconverter,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1462–1467,Sep. 2004.

[5] P. Eloranta and P. Seppinen, “Direct-digital RF modulator IC in 0.13�m CMOS for wideband multi-radio applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2005, pp. 532–533.

[6] S. M. Taleie, T. Copani, B. Bakkaloglu, and S. Kiaei, “A bandpassDelta-Sigma RF-DAC with embedded FIR reconstruction filter,” inIEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2006,pp. 578–579.

[7] R. Schreier, “An empirical study of high-order single-bit delta-sigmamodulators,” IEEE Trans. Circuits Syst. II, Analog Digit. SignalProcess., vol. 40, no. 8, pp. 461–466, Aug. 1993.


[8] W. Lee and C. Sodini, “A topology for higher order interpolativecoders,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1987,pp. 459–462.

[9] “Radio frequency devices,” Title 47—Telecommunications, ch. 1, pt.15, p. 128. Federal Communications Commission, 2006.

[10] J. Vankka, J. Sommarek, J. Ketola, I. Teikari, and K. Halonen, “A dig-ital quadrature modulator with on-chip D/A converter,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1635–1642, Oct. 2003.

[11] A. Zverev, Handbook of Filter Synthesis. New York: Wiley, 1967.[12] X. He and W. Kuhn, “A 2.5 GHz low power, high dynamic range, self-

tuned Q enhanced LC filter in SOI,” IEEE J. Solid-State Circuits, vol.40, no. 8, pp. 1618–1628, Aug. 2005.

[13] H. Khorramabadi and P. Gray, “High-frequency CMOS contin-uous-time filters,” IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp.939–948, Dec. 1984.

[14] B. Gilbert, “A precise four-quadrant multiplier with subnanosecondresponse,” IEEE J. Solid-State Circuits, vol. SC-3, no. 4, pp. 365–373,Dec. 1968.

[15] A. Kral, F. Behbahani, and A. Abidi, “RF CMOS oscillators withswitched tuning,” in Proc. IEEE Custom Integrated Circuits Conf.(CICC), 1998, pp. 555–558.

[16] J. Candy and A. Huynh, “Double interpolation for digital-to-analogconversion,” IEEE Trans. Commun., vol. COM-34, no. 1, pp. 77–81,Jan. 1986.

[17] M. Matsui, H. Hara, Y. Uetani, L. Kim, T. Nagamatsu, Y. Watanabe,A. Chiba, K. Matsuda, and T. Sakurai, “A 200 MHz 13 mm2 2-D DCTmacrocell using sense-amplifying pipeline flip-flop scheme,” IEEE J.Solid-State Circuits, vol. 29, no. 12, pp. 1482–1490, Dec. 1994.

[18] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Cir-cuits–A Design Perspective, C. G. Sodini, Ed., 2nd ed. EnglewoodCliffs, NJ: Prentice Hall, 2003.

[19] B. Nikolic, V. Oklobdzija, V. Stoyanovic, W. Jia, J. Chiu, and M.Leung, “Improved sense-amplifier-based flip-flop: Design and mea-surements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884,Jun. 2000.

[20] M. Pelgrom, C. Duinmaijer, and A. Welbers, “Matching properties ofMOS transistors,” IEEE Trans. Circuits Syst. II, Analog Digit. SignalProcess., vol. 24, pp. 1433–1439, Oct. 1989.

[21] A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A10-bit 1-Gsample/s Nyquist current-steering CMOS D/A converter,”IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001.

[22] K. Doris, A. van Roermund, and D. Leenaerts, “Mismatch-basedtiming errors in current steering DACs,” in Proc. IEEE Int. Symp.Circuits and Systems (ISCAS), 2003, pp. 977–980.

Albert Jerng (M’97) received the B.S.E.E. andM.S.E.E. degrees from Stanford University, Stan-ford, CA, in 1994 and 1996, respectively.

He was with Advanced Micro Devices from 1996to 1999, designing analog and RF integrated circuits.From 1999 to 2002, he worked at DSP Group, wherehe developed CMOS RF transceivers for 900-MHzand 2.4-GHz cordless phone systems. He received thePh.D. degree from MIT in 2006, where his researchinterests included low phase noise CMOS VCO de-sign, and high data rate transmitters. He is currently

a Principal Scientist at Broadcom in San Diego, CA.

Charles G. Sodini (S’80–M’82–SM’90–F’94) re-ceived the B.S.E.E. degree from Purdue University,West Lafayette, IN, in 1974, and the M.S.E.E. andthe Ph.D. degrees from the University of Californiaat Berkeley in 1981 and 1982, respectively.

He was a Member of the Technical Staff atHewlett-Packard Laboratories from 1974 to 1982,where he worked on the design of MOS memoryand later, on the development of MOS devices withvery thin gate dielectrics. He joined the faculty of theMassachusetts Institute of Technology, Cambridge,

MA, in 1983, where he is currently a Professor in the Department of ElectricalEngineering and Computer Science. He was the Associate Director of MIT’sMicrosystems Technology Laboratories from 1989 to 1996. His researchinterests are focused on integrated circuit and system design with emphasis onanalog, RF and memory circuits and systems. Along with Prof. Roger T. Howe,he is a coauthor of an undergraduate text on integrated circuits and devicesentitled Microelectronics: An Integrated Approach (Prentice Hall, 1997). Healso studied the Hong Kong electronics industry and co-authored a chapterwith Prof. Rafael Reif in a recent book entitled Made in Hong Kong (OxfordUniversity Press, 1997).

Dr. Sodini held the Analog Devices Career Development Professorship ofMassachusetts Institute of Technology’s Department of Electrical Engineeringand Computer Science, and was awarded the IBM Faculty Development Awardfrom 1985 to 1987. He has served on a variety of IEEE conference committees,including the International Electron Device Meeting, where he was the 1989General Chairman. He was the 1992 Technical Program Co-Chairman and the1993–1994 Co-Chairman of the Symposium on VLSI Circuits. He served onthe Electron Device Society Administrative Committee from 1988 to 1994. Heis the past president of the IEEE Solid-State Circuits Society and a member ofits Administrative Committee.

Documents

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters