1 © 2012 The MathWorks, Inc.

Accelerating Mixed-Signal Design

김 용정 부장

Senior Application Engineer

MathWorks

2

Agenda

Introduction of Mixed-signal Design Flow

Sigma-Delta ADC : Digital portion

PLL Design : Analogue Portion

Digital Predistorter

User Stories and Q & A

3

VERIFICATION

Mixed-signal design flow issues

Customer reported issues:

SPICE simulation slow

Analog digital groups

disconnected

Too detailed too quickly

Difficult to test entire system

before tape out

Do you see something similar?

DESIGN

TAPEOUT

DESIGN

SPECIFICATION

Analog Digital

SPICE VHDL,

Verilog

FOUNDRY

Test equipment

4

MathWorks’ long history in mixed-signal

Early 1990’s - first papers

Now – 2 mixed-signal

papers per day mentioning

MATLAB & Simulink

0

100

200

300

400

500

600

700

1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010

Pap

ers

& p

ate

nts

pe

r ye

ar

Year

Papers and patents mentioning MATLAB and Simulink and mixed-signal

5

Mixed-signal design flow with MathWorks

Faster design through

abstraction

Fewer errors through

combing analog-digital

design

Easy adoption through

links to other tools

SYSTEM-DESIGN

Analog

SPICE

Digital

VHDL,

Verilog

System

Simulink

PROTOTYPE

TAPEOUT

FOUNDRY

Test equipment

SPECIFICATION

TE

ST

& V

ER

IFIC

AT

ION

6

Why MathWorks?

Faster design through abstraction

– Simulations much faster than SPICE

Fewer errors through combing analog-digital design

– Errors found and corrected earlier

Easy adoption through links to other tools

– Links to ModelSim, SPECTRE, test equipment…

7

Why MathWorks?

Faster design through abstraction

– “Simulink is the only tool fast enough for our jitter-tolerance

simulations”, William Walker, Fujitsu Laboratories of America

Fewer errors through combing analog-digital design

– “With a shared design environment, engineers could easily

understand each other’s work and quickly integrate design

diagrams”, Wang Wen-Chi, Realtek

Easy adoption through links to other tools

– “The team produced a test chip based on the results of the

Simulink-Spectre simulations alone…this was a huge

endorsement of our new system-level design process”, Shayan Frahvash, RFMD

8

Adoption by industry (some examples)

Company Application

Alcatel-Lucent Digital predistortion

Atmel RF front-end

Broadcom PLL

Epson ADC

Fujitsu SERDES

IDT-Newave PLL

Nujira Power amplifier

Realtek Semiconductor Audio codec

RFMD Transceiver

9

Digital plus Analog

Spectrum of Modeling Approaches for Digital

Implementation

level Z transform H(z)

Behavioral models

of components

High speed

Co simulation with third-party HDL

simulators

Simulink Fixed Point Simulink Floating Point

High fidelity

Co simulation with third-party circuit

simulators

Spectrum of Modeling Approaches for Analog

Implementation

level Laplace H(s)/ODEs

Behavioral models

of components

High speed

RF Blockset SimPowerSystems

Simulink

High fidelity

10

Agenda

Introduction of Mixed-signal Design Flow

Sigma-Delta ADC : Digital portion

PLL Design : Analogue Portion

Digital Predistorter

User Stories and Q & A

11

Case study: ADC design

Purpose:

Introduce methods using straightforward design

Design Challenge:

Sigma-delta ADC to process AM signals around 1,600

kHz

12

Behavioral ADC

Second-order sigma-delta

ADC

Rapid model

construction

Libraries

Feedback

Time handling

Filter design

13

Sigma-Delta ADC: Digital Portion

Filter Design

HDL Code-Generation

HDL Co-Simulation

Decimation Filter Design

Fixed-Point Conversion HDL Code-Generation Verification

using Co-Simulation

ADC Output Sampling Rate: 8 KHz

Decimation Filter: Fixed-point

Multistage (3 stages)

Nyquist SFilter

Develop the digital portion by following the workflow described above.

Below are some additional specifications:

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Single Stage Decimation Filter

Follow the instructions and create a single stage

decimation filter using FilterBuilder (section 3.2)

>> filterbuilder

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Model Elaboration – 3 Stage Decimation Filter

Follow the instructions and elaborate the model to include a

3 stage decimation filter using FilterBuilder (section 3.3)

16

Model Elaboration - Fixed-Point Design

Follow the instructions and elaborate the model to include

fixed-point details by using the Fixed-Point Tool (section 3.4)

Min/Max/Overflow Logging

Automatic Scaling

Control Rounding Mode

Bit-Exact Fixed-Point Code-

Generation

17

HDL Code-Generation and Co-Simulation

18

Agenda

Introduction of Mixed-signal Design Flow

Sigma-Delta ADC : Digital portion

PLL Design : Analogue Portion

Digital Predistorter

User Stories and Q & A

19

Phase-Locked Loop

Feedback control system

– Generates a signal with a fixed relation

to the phase of a reference signal

– Used for frequency synthesis, synchronization

Measurements of interest

– Time: rise time, overshoot, lock time, jitter

– Frequency: phase noise, spurs

VCO Phase

Detector

Loop

Filter

1/N

20

PLL Design – Examples from MathWorks

Jitter measurement

Fast simulation

Up to atto-sec (10-18)

accuracy

Analog variable step

21

PLL Design flow

Ideal Model

Elaborate Circuit Model

Model with s-

domain ideal

blocks

Elaborated Model

with RC Circuit

Circuit Level

Model

Elaborate individual Simulink blocks to their equivalent circuit

level implementation.

Use SimPowerSystems, an extension to Simulink, to model a

detailed circuit design that can be transitioned to a high fidelity

model realized in a circuit simulator.

22

Phase Domain Model

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Sequence of Model Elaborations

Start with a basic

“Phase Domain”

Linear PLL

End with a model that

is a starting point for

detailed circuit design

Loosely Based on

AN535 from

Freescale

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Elaborating the Loop Filter:

Laplace Domain Representation vs RC Circuit

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Co-simulation with Simulink

Verify the transistor level design:

– within the context of a full system simulation

– using the visualization and analysis capabilities of Simulink and

MATLAB

– testing each module independently of other modules

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Simulink + SimPowerSystems

Charge pump

Simulation time ~30s

Simulink + AMSD Charge

pump

Simulation time > 2hr

Co-simulation Results

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Loop filter redesign and final co simulation

28

Agenda

Introduction of Mixed-signal Design Flow

Sigma-Delta ADC : Digital portion

PLL Design : Analogue Portion

Digital Pre-distorter

User Stories and Q & A

29

Behavioral modeling of RF power amplifiers

We used a memory polynomial model1

– K = order of the model, M = memory depth

This particular model considers diagonal terms only (i.e. no cross products such

as x(n − 2) |x(n − 1)| ).

1. Morgan, Ma, Kim, Zierdt, and Pastalan. “A Generalized Memory Polynomial Model for Digital Predistortion of RF Power Amplifiers”. IEEE Trans.

on Signal Processing, Vol. 54, No. 10, Oct. 2006

kK

k

M

m

kmMP mnxmnxany

1

0

1

0

)(

x(n) y(n)

Amplifier 0 50 100 150 200 250

-0.04

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

Sample

Am

plit

ude

In-Phase

Quadrature

0 50 100 150 200 250-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

Sample

Am

plit

ude

In-Phase

Quadrature

30

pn

n

n

MK

K

K

K

pn

n

n

kK

k

M

m

kmMP

a

a

a

pMnxpMnxpnxpnx

MnxMnxnxnx

MnxMnxnxnx

y

y

y

mnxmnxany

1

1,1

01

00

1

1

1

1

1

0

1

0

1)1()1()(

2)2()11()1(

1)1()1()(

)(

We know x, we know y, how do we solve for a?

Extracting memory polynomial coefficients

- rearranging this equation into vector form:

31

PA modeling results

32

Modeling the DPD

Power amplifier model is:

We want the reverse, which

is:

DPD + PA = Ideal

Power amplifier characteristic

PA DPD

kK

k

M

m

km mnymnyanx

1

0

1

0

)(

kK

k

M

m

kmMP mnxmnxany

1

0

1

0

)(

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Modeling the DPD

Same MATLAB code as

before.

Parameters fit by:

>> a_coef = x_terms \ y;

Model results given by:

>> y = x_terms * a;

Power amplifier characteristic

PA DPD

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DPD + PA - linearization

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Digital pre-distortion

Measure real PA data

Generate test waveform

Model & compare PA

Model & verify DPD

Simulate system

Signal processing

Links to test equipment

Linear algebra,

visualization

Time domain simulation

What we need to do How we need to do it

DSP System Toolbox,

Communications System Toolbox

MATLAB

Simulink

Instrument Control Toolbox

36

Agenda

Introduction of Mixed-signal Design Flow

Sigma-Delta ADC : Digital portion

PLL Design : Analogue Portion

Digital Pre-distorter

User Stories and Q & A

37

Alcatel-Lucent Develops DPD System

for Multicarrier GSM Transceivers with

Model-Based Design

Challenge Develop a highly efficient and linear multicarrier GSM

transceiver

Solution Use Model-Based Design to model, simulate, test, and

deploy digital predistortion filters and algorithms on

FPGA and DSP hardware

Results 30% reduction in development time

Elimination of two hardware development cycles

Approximately 90% algorithm reuse

―Using MATLAB and Simulink, our

development team quickly moved

from algorithm simulation to testing

on real hardware. This workflow was

critical in reducing overall

development time and hardware

development cycles.‖

Dr. Rudolf Wessel

Alcatel-Lucent

Link to user story

An Alcatel-Lucent

multicarrier transceiver.

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Early Verification of Digital-Analog

Designs Using System-Level Cosimulation

Challenge Verify embedded electronic system performance before

implementation

Solution Cosimulate digital baseband components in MATLAB®

and Simulink® with the analog components in Cadence®

Virtuoso® AMS Designer

Results System performance verified during design phase

Production costs and development time reduced

Analog and digital development processes integrated

―Using MATLAB and Simulink as

a multidomain integration,

development, and verification

platform is a big step toward our

goals of first-time-right silicon

and no respins.‖

Hans-Werner Groh and Thomas Janz

Atmel

Link to article

A top-level Simulink model of the DAB

receiver.

39

Epson Toyocom Designs and Verifies Mixed-

Signal Integrated Circuit in Two Months

Challenge Develop a mixed-signal integrated circuit with a new 16-

bit analog-to-digital converter in two months

Solution Use MathWorks tools for Model-Based Design to model,

simulate, verify, and improve the system-level design

Results Simulation time reduced from days to minutes

Development time cut by 33%

Millions of dollars saved

―Circuit-level simulations took

three days. With Verilog-A they took

20 minutes—still too long to enable

sufficient exploration of design

alternatives. Using MATLAB and

Simulink, we reduced simulation

time to just one minute.‖

Jun Uehara

Epson Toyocom

Link to user story

Simulink model of the delta-sigma ADC with

power spectral density plot.

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Fujitsu Develops and Tests State-of-the-Art

40 Gbps Optical Transponder

Challenge Develop a 40 Gbps serializer/deserializer integrated

circuit for an optical transponder

Solution Use Simulink to model and simulate key components of

the design, and use MATLAB and Instrument Control

Toolbox to automate chip testing and characterization

Results First-silicon-success for components verified in

Simulink

Faster verification of mixed-signal designs

Test time reduced by 90%

―By including circuit-level simulation

results in our Simulink models we

can simulate millions of cycles with

the accuracy needed to account for

noise and other transient effects.

Simulink is the only tool fast enough

for our jitter-tolerance simulations.‖

William Walker

Fujitsu Laboratories of America

Link to user story

SERDES chips mounted on inert substrate

for testing.

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Free mixed-signal library

Library contents:

– 40+ blocks

– 20+ demos

– Tutorials

Devices:

– ADCs,

– PLLs,

– Digital pre-distortion,

– Switched-mode power supplies…

– …and more

Available free from:

– http://www.mathworks.com/programs/mixed-signal/

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Summary

Proven tools for mixed-signal

– Long history

– Industry adoption

Key benefits seen by users:

– Faster design through abstraction

– Fewer errors through combing analog-digital design

– Easy adoption through links to other tools

Clear adoption path