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8/12/2019 AD7858
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FUNCTIONAL BLOCK DIAGRAM
2.5VREFERENCE
AVDD AGND
DVDD
DGND
CLKIN
CONVS
BUSY
SLEEP
CAL
CREF2
CREF1
REFIN/REFOUT
AIN8
AIN1
DIN DOUT SCLKSYNC
SERIAL INTERFACE/CONTROL REGISTER
BUF
CHARGEREDISTRIBUTION
DAC
AD7858/AD7858L..
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COMP
CALIBRATIONMEMORY ANDCONTROLLER
SAR + ADCCONTROL
T/HI/P
MUX
REV. 0
Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
a 3 V to 5 V Single Supply, 200 kSPS8-Channel, 12-Bit Sampling ADCAD7858/AD7858L*
Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A
Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
Specified for VDDof 3 V to 5.5 VAD7858200 kSPS; AD7858L100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power
AD7858: 15 mW (VDD= 3 V)
AD7858L: 5.5 mW (VDD= 3 V)
Automatic Power Down After Conversion (25W)
Flexible Serial Interface:
8051/SPI/QSPI/P Compatible
24-Pin DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTION
The AD7858/AD7858L are high speed, low power, 12-bitADCs that operate from a single 3 V or 5 V power supply, theAD7858 being optimized for speed and the AD7858L for lowpower. The ADC powers up with a set of default conditions atwhich time it can be operated as a read only ADC. The ADCcontains self-calibration and system calibration options to en-sure accurate operation over time and temperature and have anumber of power-down options for low power applications.
The part powers up with a set of default conditions and can op-erate as a read only ADC.
The AD7858 is capable of 200 kHz throughput rate while theAD7858L is capable of 100 kHz throughput rate. The inputtrack-and-hold acquires a signal in 500 ns and features apseudo-differential sampling scheme. The AD7858/AD7858Lvoltage range is 0 to VREFwith both straight binary and 2s comple-ment output coding. Input signal range is to the supply and thepart is capable of converting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically5.4 mW for normal operation and 3.6 W in power-downmode. The part is available in 24-pin, 0.3 inch-wide dual-in-linepackage (DIP), 24-lead small outline (SOIC) and 24-lead small
shrink outline (SSOP) packages.
**Patent pending.
**See page 33 for data sheet index.
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.3. Flexible power management options including automatic
powerdown after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input range from 0 V to VDD.
6. Eight single-ended or four pseudo-differential input channels.
7. Self- and system calibration.
8. Versatile serial I/O port (SPI/QSPI/8051/P).
9. Lower power version AD7858L.
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Parameter A Version1 B Version1 Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio3 70 71 dB min Typically SNR is 72 dB
(SNR) VIN= 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)
Total Harmonic Distortion (THD) 78 78 dB max VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (100 kHz)Peak Harmonic or Spurious Noise 78 78 dB max VIN= 10 kHz Sine Wave, fSAMPLE= 200 kHz (100 kHz)
Intermodulation Distortion (IMD)
Second Order Terms 78 80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f SAMPLE= 200 kHz (100 kHz)
Third Order Terms 78 80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f SAMPLE= 200 kHz (100 kHz)
Channel-to-Channel Isolation 90 90 dB typ VIN= 25 kHz
DC ACCURACY Any Channel
Resolution 12 12 Bits
Integral Nonlinearity 1 1 LSB max 2.5 V External Reference VDD= 3 V, VDD= 5 V (B Grade Only)1 0.5 LSB max 5 V External Reference VDD= 5 V
(1) LSB max (L Version, 5 V External Reference, VDD= 5 V)(1) LSB max (L Version)
Differential Nonlinearity 1 1 LSB max Guaranteed No Missed Codes to 12 Bits. 2.5 V ExternalReference VDD= 3 V, 5 V External Reference, VDD= 5 V
Total Unadjusted Error 1 1 LSB typ
Unipolar Offset Error 5 5 LSB max Typically 2 LSBs2.5 2.5 LSB max 5 V External Reference, VDD= 5 V(3) (3) LSB max (L Version)(1.5) (1.5) LSB max (L Version, 5 V External Reference, VDD= 5 V)
Unipolar Offset Error Match 1.5 1.5 LSB max
Positive Full-Scale Error 3 3 LSB max1.5 1.5 LSB max 5 V External Reference, VDD = 5 V
Positive Full-Scale Error Match 1 1 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to VREF 0 to VREF Volts i.e., AIN(+) AIN() = 0 to VREF, AIN() can be biased
up but AIN(+) cannot go below AIN()
Leakage Current 1 1 A maxInput Capacitance 20 20 pF typ
REFERENCE INPUT/OUTPUT
REFINInput Voltage Range 2.3/VDD 2.3/VDD V min/max Functional from 1.2 V
Input Impedance 150 150 ktypREFOUTOutput Voltage 2.3/2.7 2.3/2.7 V min/max
REFOUTTempco 20 20 ppm/C typ
LOGIC INPUTS
Input High Voltage, VINH 2.4 2.4 V min AVDD = DVDD= 4.5 V to 5.5 V
2.1 2.1 V min AVDD = DVDD= 3.0 V to 3.6 V
Input Low Voltage, VINL 0.8 0.8 V max AVDD = DVDD= 4.5 V to 5.5 V
0.6 0.6 V max AVDD = DVDD= 3.0 V to 3.6 V
Input Current, IIN 10 10 A max Typically 10 nA, VIN = 0 V or VDDInput Capacitance, CIN
4 10 10 pF max
LOGIC OUTPUTS
Output High Voltage, VOH ISOURCE= 200 A4 4 V min AVDD = DVDD= 4.5 V to 5.5 V
2.4 2.4 V min AVDD = DVDD= 3.0 V to 3.6 V
Output Low Voltage, VOL 0.4 0.4 V max ISINK= 0.8 mA
Floating-State Leakage Current 10 10 A maxFloating-State Output Capacitance4 10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 4.6 (18) 4.6 s max (L Versions Only, 40C to +85C, 1 MHz CLKIN)(10) s max (L Versions Only, 0C to +70C, 1.8 MHz CLKIN)
Track/Hold Acquisition Time 0.4 (1) 0.4 (1) s min (L Versions Only)
REV. 02
AD7858/AD7858LSPECIFICATIONS1, 2 (AVDD= DVDD= +3.0 V to +5.5 V, REFIN/REFOUT= 2.5 V ExternalReference unless otherwise noted, fCLKIN= 4 MHz (1.8 MHz B Grade (0C to +70C), 1 MHz A and B Grades (40C to +85C) for L Version); fSAMPLE=
200 kHz (AD7858), 100 kHz (AD7858L); SLEEP= Logic High; TA= TMINto TMAX, unless otherwise noted.) Specifications in ( ) apply to the AD7858L.
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Parameter A Version1 B Version1 Units Test Conditions/Comments
DYNAMIC PERFORMANCE
AVDD, DVDD +3.0/+5.5 +3.0/+5.5 V min/max
IDDNormal Mode5 6 (1.9) 6 (1.9) mA max AVDD = DVDD= 4.5 V to 5.5 V. Typically 4.5 mA (1.5)
5.5 (1.9) 5.5 (1.9) mA max AVDD = DVDD= 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Sleep Mode
6
With External Clock On 10 10 A typ Full Power Down. Power Management Bits in ControlRegister Set as PMGT1 = 1, PMGT0 = 0
400 400 A typ Partial Power Down. Power Management Bits inControl Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off 5 5 A max Typically 1 A. Full Power Down. Power Management Bitsin Control
Register Set as PMGT1 = 1, PMGT0 = 0
200 200 A typ Partial Power Down. Power Management Bits in ControlRegister Set as PMGT1 = 1, PMGT0 = 1
Normal Mode Power Dissipation 33 (10.5) 33 (10.5) mW max VDD= 5.5 V. Typically 25 mW (8); SLEEP= VDD20 (6.85) 20 (6.85) mW max VDD= 3.6 V. Typically 15 mW (5.4); SLEEP= VDD
Sleep Mode Power Dissipation
With External Clock On 55 55 W typ VDD= 5.5 V. SLEEP= 0 V36 36 W typ VDD= 3.6 V. SLEEP= 0 V
With External Clock Off 27.5 27.5 W max VDD= 5.5 V. Typically 5.5 W; SLEEP= 0 V18 18 W max VDD= 3.6 V. Typically 3.6 W; SLEEP= 0 V
SYSTEM CALIBRATION
Offset Calibration Span7 +0.05 VREF/0.05 VREF V max/min Allowable Offset Voltage Span for CalibrationGain Calibration Span7 +1.025 VREF/0.975 VREF V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES1Temperature ranges as follows: A, B Versions: 40C to +85C. For L Versions, A and B Versions fCLKIN= 1 MHz over 40C to +85C temperature range,B Version fCLKIN= 1.8 MHz over 0C to +70C temperature range.
2Specifications apply after calibration.3SNR calculation includes distortion and noise components.4Sample tested @ +25C to ensure compliance.5All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC@ DVDD. No load on the digital outputs. Analog inputs @ AGND.6CLKIN @ DGND when external clock off. All digital inputs @ DGND except forCONVST, SLEEP, CAL, and SYNC@ DVDD. No load on the digitaloutputs. Analog inputs @ AGND.
7The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltagespans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN()
0.05 VREF, and the allowable system full scale voltage applied between AIN(+) and AIN() for the system full-scale voltage error to be adjusted out will beVREF 0.025 VREF). This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
AD7858/AD7858L
REV. 0 3
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AD7858/AD7858L
Limit at TMIN, TMAX (A, B Versions)
Parameter 5 V 3 V Units Description
fCLKIN2 500 500 kHz min Master Clock Frequency
4 4 MHz max1.8 1.8 MHz max L Version, 0C to +70C, B Grade Only1 1 MHz max L Version, 40C to +85C
fSCLK 4 4 MHz maxt1
3 100 100 ns min CONVSTPulse Widtht2 50 90 ns max CONVSTto BUSYPropagation DelaytCONVERT 4.6 4.6 s max Conversion Time = 18 tCLKIN
10 (18) 10 (18) s max L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 tCLKINt3 0.4 tSCLK 0.4 tSCLK ns min SYNCto SCLKSetup Time (Noncontinuous SCLK Input)
0.4 tSCLK 0.4 tSCLK ns min/max SYNCto SCLKSetup Time (Continuous SCLK Input)t4
4 50 90 ns max Delay from SYNCUntil DOUT 3-State Disabledt5
4 50 90 ns max Delay from SYNCUntil DIN 3-State Disabledt6
4 75 115 ns max Data Access Time After SCLK t7 40 60 ns min Data Setup Time Prior to SCLK t8 20 30 ns min Data Valid to SCLK Hold Timet9 0.4 tSCLK 0.4 tSCLK ns min SCLK High Pulse Widtht10 0.4 tSCLK 0.4 tSCLK ns min SCLK Low Pulse Widtht11 30 50 ns min SCLK to SYNCHold Time (Noncontinuous SCLK)
30/0.4 tSCLK 50/0.4 tSCLK ns min/max (Continuous SCLK)t12
5 50 50 ns max Delay from SYNCUntil DOUT 3-State Enabledt13 90 130 ns max Delay from SCLK to DIN Being Configured as Outputt14
6 50 90 ns max Delay from SCLK to DIN Being Configured as Inputt15 2.5 tCLKIN 2.5 tCLKIN ns max CALto BUSYDelayt16 2.5 tCLKIN 2.5 tCLKIN ns max CONVSTto BUSYDelay in Calibration SequencetCAL
7 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent(125013 tCLKIN)
tCAL17 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111114 tCLKIN)tCAL2
7 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent(13899 tCLKIN)
NOTES1Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.See Table XI and timing diagrams for different interface modes and Calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.3The CONVSTpulse width will here only applies for normal operation. When the part is in power-down mode, a different CONVSTpulse width will apply
(see Power-Down section).4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.5t12is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true busrelinquish time of the part and is independent of the bus loading.
6t14is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is thetrue delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.7The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due tothe 1.8/1 MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1( AVDD = DVDD= +3.0 V to +5.5 V; fCLKIN= 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
TA= TMINto TMAX, unless otherwise noted)
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AD7858/AD7858L
REV. 0 5
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams forserial Interface Mode 2. The reading and writing occurs afterconversion in Figure 2, and during conversion in Figure 3. Toattain the maximum sample rate of 100 kHz (AD7858L) or200 kHz (AD7858), reading and writing must be performedduring conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSYto the next rising edge of CONVST) before the next conversionbegins to ensure that the part is settled to the 12-bit level. If theuser does not want to provide the CONVSTsignal, the conver-sion can be initiated in software by writing to the control register.
TO OUTPUTPIN
CL100pF
IOL1.6mA
IOH200A
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
tCONVERT= 4.6s MAX, 10s MAX FOR L VERSIONt1= 100ns MIN, t4= 50/90ns MAX 5V/3V, t7= 40/60ns MIN 5V/3V
DB15
SYNC (I/P)
SCLK (I/P)
t3
BUSY (O/P)
CONVST (I/P)
tCONVERT
1 5 6 16
DOUT (O/P) DB0DB11
DIN (I/P) DB15 DB0
3-STATE
DB11
3-STATE
t1
t2
t4t6 t6
t9
t11
t12
t8t7
t10
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
tCONVERT= 4.6s MAX, 10s MAX FOR L VERSION
t1= 100ns MIN, t4= 50/90ns MAX 5V/3V, t7= 40/60ns MIN 5V/3V
DB15
SYNC (I/P)
SCLK (I/P)
t3
BUSY (O/P)
CONVST (I/P)
tCONVERT
1 5 6 16
DOUT (O/P) DB0DB11
DIN (I/P) DB15 DB0
3-STATE
DB11
3-STATE
t1
t2
t4t6 t6
t9t11
t12
t8t7
t10
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
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6/36REV. 06
AD7858/AD7858L
ORDERING GUIDE
Linearity Power
Error Dissipation Package
Model (LSB)1 (mW) Option2
AD7858AN 1 20 N-24AD7858BN 1/2 20 N-24AD7858LAN3 1 6.85 N-24AD7858LBN3 1 6.85 N-24AD7858AR 1 20 R-24AD7858BR 1/2 20 R-24AD7858LAR3 1 6.85 R-24AD7858LBR3 1 6.85 R-24AD7858LARS3 1 6.85 RS-24EVAL-AD7858CB4
EVAL-CONTROL BOARD5
NOTES1Linearity error here refers to integral linearity error.2N = Plastic DIP; R = SOIC; RS = SSOP.3L signifies the low power version.4This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with allAnalog Devices evaluation boards ending in the CB designators.
ABSOLUTE MAXIMUM RATINGS1
(TA= +25C unless otherwise noted)
AVDDto AGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 VDVDDto DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 VAVDDto DVDD . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 VAnalog Input Voltage to AGND . . . . 0.3 V to AVDD+ 0.3 VDigital Input Voltage to DGND . . . . 0.3 V to DV
DD+ 0.3 V
Digital Output Voltage to DGND . . . 0.3 V to DVDD+ 0.3 VREFIN/REFOUTto AGND . . . . . . . . . 0.3 V to AVDD+ 0.3 VInput Current to Any Pin Except Supplies2 . . . . . . . .10 mAOperating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . . 40C to +85CStorage Temperature Range . . . . . . . . . . . . 65C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150CPlastic DIP Package, Power Dissipation . . . . . . . . . . .450 mWJAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 105C/WJCThermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7C/WLead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . . 450 mWJAThermal Impedance . . . 75C/W (SOIC) 115C/W (SSOP)JCThermal Impedance . . . . 25C/W (SOIC) 35C/W (SSOP)Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215CInfared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES1Stresses above those listed under Absolute Maximum Ratings may causepermanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in theoperational sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch up.
PINOUTS FOR DIP, SOIC AND SSOP
13
16
15
14
24
23
22
21
20
19
18
17
TOP VIEW(Not to Scale)
12
11
10
9
8
1
2
3
4
7
6
5AD7858/AD7858L
CONVST
DIN
CLKIN
SCLK
SYNC
BUSY
SLEEP
REFIN/REFOUT
DVDD
DGND
DOUTAVDD
AGND
CREF1
CREF2
AIN0
AIN1 AIN6
AIN7
CAL
AIN2
AIN3
AIN5
AIN4
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthese devices feature proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-mended to avoid performance degradation or loss of functionality.
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AD7858/AD7858L
REV. 0 7
TERMINOLOGY1
Integral Nonlinearity
This is the maximum deviation from a straight line passingthrough the endpoints of the ADC transfer function. The end-points of the transfer function are zero scale, a point 1/2 LSB be-low the first code transition, and full scale, a point 1/2 LSBabove the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSBchange between any two adjacent codes in the ADC.
Total Unadjusted Error
This is the deviation of the actual code from the ideal code tak-ing all errors into account (Gain, Offset, Integral Nonlinearity, andother errors) at any point along the transfer function.
Unipolar Offset Error
This is the deviation of the first code transition (00. . . 000 to00 . . . 001) from the ideal AIN(+) voltage (AIN() + 1/2 LSB).
Positive Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN() + Full Scale 1.5 LSB) after the offseterror has been adjusted out.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of crosstalk betweenthe channels. It is measured by applying a full-scale 25 kHz sig-nal to the other seven channels and determining how much thatsignal is attenuated in the channel of interest. The figure given isthe worst case for all channels.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end ofconversion. Track/Hold acquisition time is the time required forthe output of the track/hold amplifier to reach its final value,within 1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at theoutput of the A/D converter. The signal is the rms amplitude ofthe fundamental. Noise is the sum of all nonfundamental signalsup to half the sampling frequency (fS/2), excluding dc. The ratiois dependent on the number of quantization levels in the digitiza-tion process; the more levels, the smaller the quantization noise.The theoretical signal to (noise + distortion) ratio for an idealN-bit converter with a sine wave input is given by:
Signal to (Noise +Distortion) = (6.02N +1.76)dB
Thus for a 12-bit converter, this is 74 dB.
1AIN(+) refers to the positive input of the pseudo differential pair, and AIN()refers to the negative analog input of the pseudo differential pair or to AGND
depending on the channel configuration.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum ofharmonics to the fundamental. For the AD7858/AD7858L, it isdefined as:
THD dB( )=20 log (V22
+V32
+V42
+V52
+V62
)V1
where V1is the rms amplitude of the fundamental and V2, V3,V4, V5 and V6are the rms amplitudes of the second through thesixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of therms value of the next largest component in the ADC outputspectrum (up to fS/2 and excluding dc) to the rms value of thefundamental. Normally, the value of this specification is deter-mined by the largest harmonic in the spectrum, but for partswhere the harmonics are buried in the noise floor, it will be anoise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa andfb, any active device with nonlinearities will create distortionproducts at sum and difference frequencies of mfa nfb wherem, n = 0, 1, 2, 3, etc. Intermodulation distortion terms arethose for which neither m or n are equal to zero. For example,the second order terms include (fa + fb) and (fa fb), while thethird order terms include (2fa + fb), (2fa fb), (fa + 2fb) and(fa 2fb).
Testing is performed using the CCIF standard where two inputfrequencies near the top end of the input bandwidth are used. Inthis case, the second order terms are usually distanced in fre-quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As aresult, the second and third order terms are specified separately.The calculation of the intermodulation distortion is as per theTHD specification where it is the ratio of the rms sum of the in-dividual distortion products to the rms amplitude of the sum ofthe fundamentals expressed in dBs.
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AD7858/AD7858L
AD7858/AD7858L PIN FUNCTION DESCRIPTION
Pin Mnemonic Description
1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold modeand starts conversion. When this input is not used, it should be tied to DV DD.
2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVSTor rising edge of CAL,
and remains high until conversion is completed. BUSY is also used to indicate when the AD7858/AD7858L has completed its on-chip calibration sequence.
3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down including theinternal voltage reference provided there is no conversion or calibration being performed. Calibrationdata is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
4 REFIN/REFOUT Reference Input/Output. This pin is connected to the internal reference through a series resistor and isthe reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and thisappears at the pin. This pin can be overdriven by an external reference or can be taken as high as AV DD.When this pin is tied to AVDD,the CREF1pin should also be tied to AVDD.
5 AVDD Analog Positive Supply Voltage, +3.0 V to +5.5 V.
6 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
7 CREF1 Reference Capacitor (0.1 F Multilayer Ceramic). This external capacitor is used as a charge source forthe internal DAC. The capacitor should be tied between the pin and AGND.
8 CREF2 Reference Capacitor (0.01 F Ceramic Disc). This external capacitor is used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND.916 AIN1AIN8 Analog Inputs. Eight analog inputs that can be used as eight single ended inputs (referenced to AGND)
or four pseudo differential inputs. Channel configuration is selected by writing to the control register.Both the positive and negative inputs cannot go below AGND or above AVDDat any time. Also the posi-tive input cannot go below the negative input. See Table III for channel selection.
17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 A. A Logic 0 on this pin resetsall logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitorfrom this pin to AGND to allow for an automatic self-calibration on power-up. This input overrides allother internal operations.
18 DVDD Digital Supply Voltage, +3.0 V to +5.5 V.
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin canact as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table XI).
22 CLKIN Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and cali-bration times.
23 SCLK Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24 SYNC Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the readand write operations (see Table XI).
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AD7858/AD7858L ON-CHIP REGISTERS
The AD7858/AD7858L powers up with a set of default conditions. The only writing that is required is to select the channel configu-ration. Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down, and a full self-calibration.
Extra features and flexibility such as performing different power-down options, different types of calibrations including systemcalibration, and software conversion start can be selected by further writing to the part.
The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Registerand10 Calibration Registers. The control register is write only, the ADC output data register and the status register are read only, andthe test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determinewhich register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ-ten that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the overall write register hierarchy.
Table I. Write Register Addressing
ADDR1 ADDR0 Comment
0 0 This combination does not address any register so the subsequent 14 data bits are ignored.0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test
register.
1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are writtento the selected calibration register.
1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to thecontrol register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. Thesebits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read addressbits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will befrom the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-ter until the read selection bits are changed in the Control Register.
Table II. Read Register Addressing
RDSLT1 RDSLT0 Comment
0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER.This is the power updefault setting. There will always be 4 leading zeros when reading from the ADC Output Data Register.
0 1 All successive read operations will be from TEST REGISTER.
1 0 All successive read operations will be from CALIBRATION REGISTERS.
1 1 All successive read operations will be from STATUS REGISTER.
01 10 11
00 01 10 11
ADDR1, ADDR0DECODE
TESTREGISTER
CONTROLREGISTER
GAIN(1)OFFSET(1)
DAC(8)
GAIN(1)OFFSET(1) OFFSET(1) GAIN(1)
CALIBRATIONREGISTERS
CALSLT1, CALSLT0DECODE
Figure 4. Write Register Hierarchy/Address Decoding
01 10 11
00 01 10 11
TESTREGISTER
STATUSREGISTER
GAIN(1)OFFSET(1)
DAC(8)
GAIN(1)OFFSET(1) OFFSET(1) GAIN(1)
CALIBRATIONREGISTERS
CALSLT1, CALSLT0DECODE
00
ADC OUTPUTDATA REGISTER
RDSLT1, RDSLT0DECODE
Figure 5. Read Register Hierarchy/Address Decoding
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CONTROL REGISTER
The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de-scribed below. The power-up status of all bits is 0.
MSB
SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1
RDSLT0 2/3MODE CONVST CALMD CALSLT1 CALSLT0 STCAL
LSB
CONTROL REGISTER BIT FUNCTION DESCRIPTION
Bit Mnemonic Comment
13 SGL/DIFF A 0 in bit position configures the input channels in pseudo differential mode. A 1 in this bit positionconfigures the input channels in single ended mode (see Table III).
12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can11 CH1 be configured as eight single ended channels or four pseudo differential channels. The default selection10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).
9 PMGT1 Power Management Bits. These two bits are used with the SLEEPpin for putting the part into various8 PMGT0 Power-Down Modes (see Power-Down section for more details).
7 RDSLT1 Theses two bits determine which register is addressed for the read operations (see Table II).6 RDSLT0
5 2/3MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 bydefault after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to1 in every write cycle.
4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration(see Calibration section.)
3 CALMD Calibration Mode Bit. A 0 here selects self calibration, and a 1 selects a system calibration (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibrationregister for read/write of calibration coefficients (see section on the Calibration Registers for more details).
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Table III. Channel Selection
SGL/DIFF CH2 CH1 CH0 AIN(+)* AIN()*
0 0 0 0 AIN1 AIN20 0 0 1 AIN3 AIN40 0 1 0 AIN5 AIN60 0 1 1 AIN
7AIN
80 1 0 0 AIN2 AIN10 1 0 1 AIN4 AIN30 1 1 0 AIN6 AIN50 1 1 1 AIN8 AIN7
1 0 0 0 AIN1 AGND1 0 0 1 AIN3 AGND1 0 1 0 AIN5 AGND1 0 1 1 AIN7 AGND
1 1 0 0 AIN2 AGND1 1 0 1 AIN4 AGND1 1 1 0 AIN6 AGND1 1 1 1 AIN8 AGND
*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,*AIN() refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.
Table IV. Calibration Selection
CALMD CALSLT1 CALSLT0 Calibration Type
0 0 0 A Full Internal Calibrationis initiated where the Internal DAC is calibratedfollowed by the Internal Gain Error, and finally the Internal Offset Error iscalibrated out. This is the default setting.
0 0 1 Here the Internal Gain Erroris calibrated out followed by the Internal OffsetErroris calibrated out.
0 1 0 This calibrates out the Internal Offset Error only.
0 1 1 This calibrates out the Internal Gain Error only.1 0 0 A Full System Calibrationis initiated here where first the Internal DAC is
calibrated followed by the System Gain Error, and finally the System Offset Er-ror is calibrated out.
1 0 1 Here the System Gain Erroris calibrated out followed by the System OffsetError.
1 1 0 This calibrates out the System Offset Erroronly.
1 1 1 This calibrates out the System Gain Erroronly.
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MSB
ZERO BUSY SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0
RDSLT1 RDSLT0 2/3MODE X CALMD CALSLT1 CALSLT0 STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit Mnemonic Comment
15 ZERO This bit is always 0.
14 BUSY Conversion/Calibration Busy Bit. When this bit is 1 this indicates that there is a conversionor calibration in progress. When this bit is 0, there is no conversion or calibration in progress.
13 SGL/DIFF These four bits indicates the channel which is selected for conversion (see Table III).12 CH211 CH110 CH0
9 PMGT1 Power management bits. These bits along with the SLEEPpin will indicate if the part is in a8 PMGT0 power down mode or not. See Table VI for description.
7 ONE Both theses bits are always 1 indicating it is the status register which is being read (see Table II).6 ONE
5 2/3MODE Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1,the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.
4 X Dont care bit.
3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self calibration is selected, and a 1 in this bitindicates a system calibration is selected (see Table III).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a1 CALSLT0 calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and
0 STCAL CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing(see section on the Calibration Registers for more details).
STATUS REGISTER
The arrangement of the Status Register is shown below. The status register is a read only register and contains 16 bits of data. Thestatus register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bitsin the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTERSETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flow Chart for Reading the Status Register
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CALIBRATION REGISTERS
The AD7858/AD7858L has 10 calibration registers in all, 8 for the DAC, 1 for the offset and 1 for gain. Data can be written to orread from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only ifthe user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-dressed (see Table V). The addressing applies to both the read and write operations for the calibration registers. The user should notattempt to read from and write to the calibration registers at the same time.
Table V. Calibration Register Addressing
CALSLT1 CALSLT0 Comment
0 0 This combination addresses the Gain (1), Offset (1)and DAC Registers (8). Ten registers in total.0 1 This combination addresses the Gain (1)and Offset (1)Registers. Two registers in total.1 0 This combination addresses the Offset Register. One register in total.1 1 This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
For writing to the calibration registers a write to the control reg-ister is required to set the CALSLT0 and CALSLT1 bits. For
reading from the calibration registers a write to the control reg-ister is required to set the CALSLT0 and CALSLT1 bits, butalso to set the RDSLT1 and RDSLT0 bits to 10 (this addressesthe calibration registers for reading). The calibration registerpointer is reset on writing to the control register setting theCALSLT1 and CALSLT0 bits, or upon completion of all thecalibration register write/read operations. When reset it points tothe first calibration register in the selected write/read sequence.The calibration register pointer will point to the gain calibrationregister upon reset in all but one case, this case being where theoffset calibration register is selected on its own (CALSLT1 = 1,CALSLT0 = 0). Where more than one calibration register is be-ing accessed the calibration register pointer will be automaticallyincremented after each calibration register write/read operation.The order in which the 10 calibration registers are arranged isshown in Figure 7. The user may abort at any time before all thecalibration register write/read operations are completed, and thenext control register write operation will reset the calibrationregister pointer. The flow chart in Figure 8 shows the sequencefor writing to the calibration registers and Figure 9 for reading.
CAL REGISTERADDRESS POINTER GAIN REGISTER
OFFSET REGISTER
DAC 1ST MSB REGISTER
DAC 8TH MSB REGISTER
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
(1)
(2)
(3)
(10)
CALIBRATION REGISTERS
CALIBRATION REGISTERADDRESS POINTERPOSITION IS DETERMINEDBY THE NUMBER OF
CALIBRATION REGISTERSADDRESSED AND THENUMBER OF READ/WRITEOPERATIONS
Figure 7. Calibration Register Arrangements
When reading from the calibration registers there will always betwo leading zeros for each of the registers. When operating inSerial Interface Mode 1 the read operations to the calibration
registers cannot be aborted. The full number of read operationsmust be completed (see section on Serial Interface Mode 1Timing for more detail).
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER ISAUTOMATICALLY RESET
WRITE TO CAL REGISTER(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER ISAUTOMATICALLY INCREMENTED
LASTREGISTER
WRITEOPERATION
ORABORT
?
FINISHED
YES
NO
Figure 8. Flowchart for Writing to the Calibration Registers
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START
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER ISAUTOMATICALLY RESET
READ CAL REGISTER
CAL REGISTER POINTER ISAUTOMATICALLY INCREMENTED
LASTREGISTER
READOPERATION
ORABORT
?
FINISHED
YES
NO
Figure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zerosand 14 data bits. By changing the contents of the offset registerdifferent amounts of offset on the analog input signal can becompensated for. Increasing the number in the offset calibrationregister compensates for negative offset on the analog input sig-nal, and decreasing the number in the offset calibration registercompensates for positive offset on the analog input signal. The
default value of the offset calibration register is 0010 0000 00000000 approximately. This is not an exact value, but the value inthe offset register should be close to this value. Each of the 14data bits in the offset register is binary weighted; the MSB hasa weighting of 5% of the reference voltage, the MSB-1 has aweighting of 2.5%, the MSB-2 has a weighting of 1.25%, andso on down to the LSB which has a weighting of 0.0006%. Thisgives a resolution of 0.0006% of VREF approximately. Moreaccurately the resolution is (0.05 VREF)/213volts =0.015 mV, with a 2.5 V reference. The maximum offset thatcan be compensated for is 5% of the reference voltage, whichequates to 125 mV with a 2.5 V reference and 250 mV witha 5 V reference.
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V what code needs to be written to the off-
set register to compensate for the offset?
A. 2.5 V reference implies that the resolution in the offset regis-ter is 5% 2.5 V/213= 0.015 mV. +20 mV/0.015 mV =1310.72; rounding to the nearest number gives 1311. In bi-
nary terms this is 0101 0001 1111. Therefore, decrease theoffset register by 0101 0001 1111.
This method of compensating for offset in the analog input sig-nal allows for fine tuning the offset compensation. If the offseton the analog input signal is known, there will be no need to ap-ply the offset voltage to the analog input pins and do a systemcalibration. The offset compensation can take place in software.
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, two leading 0sand 14 data bits. The data bits are binary weighted as in the off-set calibration register. The gain register value is effectively mul-tiplied by the analog input to scale the conversion result over thefull range. Increasing the gain register compensates for a smalleranalog input range and decreasing the gain register compensatesfor a larger input range. The maximum analog input range thatthe gain register can compensate for is 1.025 times the referencevoltage, and the minimum input range is 0.975 times the refer-ence voltage.
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CIRCUIT INFORMATION
The AD7858/AD7858L is a fast, 12-bit single supply A/D con-verter. The part requires an external 4 MHz/1.8 MHz masterclock (CLKIN), two CREFcapacitors, a CONVSTsignal to startconversion and power supply decoupling capacitors. The partprovides the user with track/hold, on-chip reference, calibrationfeatures, A/D converter and serial interface logic functions on a
single chip. The A/D converter section of the AD7858/AD7858Lconsists of a conventional successive-approximation converterbased around a capacitor DAC. The AD7858/AD7858L acceptsan analog input range of 0 to +VDD where the reference can betied to VDD. The reference input to the part is buffered on-chip.
A major advantage of the AD7858/AD7858L is that a conversioncan be initiated in software as well as applying a signal to theCONVSTpin. Another innovative feature of the AD7858/AD7858L is self calibration on power-up, which is initiated hav-ing a 0.01 F capacitor from the CALpin to AGND, to give su-perior dc accuracy. The part should be allowed 150 ms afterpower up to perform this automatic calibration before any readingor writing takes place. The part is available in a 24-pin SSOPpackage and this offers the user considerable spacing saving ad-vantages over alternative solutions. The AD7858L version typi-cally consumes only 5.5 mW making it ideal for battery-poweredapplications.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKINpin. Conversion is initiated on the AD7858/AD7858L by pulsingthe CONVSTinput or by writing to the control register and set-ting the CONVST bit to 1. On the rising edge of CONVST(orat the end of the control register write operation), the on-chiptrack/hold goes from track to hold mode. The falling edge ofthe CLKIN signal that follows the rising edge of the CONVSTsignal initiates the conversion, provided the rising edge ofCONVST
occurs at least 10 ns typically before this CLKIN
edge. The conversion cycle will take 16.5 CLKIN periods fromthis CLKIN falling edge. If the 10 ns setup time is not met, theconversion will take 17.5 CLKIN periods. The maximum speci-fied conversion time is 4.6 s for the AD7858 (18tCLKIN,CLKIN = 4 MHz) and 10 s for the AD7858L (18tCLKIN,CLKIN = 1.8 MHz). When a conversion is completed, theBUSY output goes low, and then the result of the conversion
can be read by accessing the data through the serial interface.To obtain optimum performance from the part, the read opera-tion should not occur during the conversion or 400 ns prior tothe next CONVSTrising edge. However, the maximumthroughput rates are achieved by reading/writing during conver-sion, and reading/writing during conversion is likely to degradethe Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858can operate at throughput rates up to 200 kHz, 100 kHz for theAD7858L. For the AD7858 a conversion takes 18 CLKINperiods; 2 CLKIN periods are needed for the acquisition timegiving a full cycle time of 5 s (= 200 kHz, CLKIN = 4 MHz).For the AD7858L 100 kHz throughput can be obtained as fol-lows: the CLKIN and CONVSTsignals are arranged to give aconversion time of 16.5 CLKIN periods as described above,
1.5 CLKIN periods are allowed for the acquisition time. Thisgives a full cycle time of 10 s (=100 kHz, CLKIN = 1.8 MHz).When using the software conversion start for maximum through-put the user must ensure the control register write operation ex-tends beyond the falling edge of BUSY. The falling edge ofBUSY resets the CONVSTbit to 0 and allows it to be repro-grammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7858/AD7858L. The AGND and the DGND pins are connected to-gether at the device for good noise suppression. The CALpinhas a 0.01 F capacitor to enable an automatic self- calibrationon power-up. The conversion result is output in a 16-bit word
AUTO CAL ONPOWER-UP
AVDD DVDD
AIN(+)
AIN()
CREF1
CREF2
SLEEP DIN
DOUT
SYNC
CONVST
AGND
DGND
CLKIN
SCLK
REFIN/REFOUT
AD7858/AD7858L
ANALOGSUPPLY
+3V TO +5V 0.1F0.1F10F
DVDD
0.1F
0.01F
MASTER CLOCKINPUT
CONVERSIONSTART INPUT
FRAME SYNC INPUT
SERIAL DATAOUTPUT
0.01F
CAL0.01F
INTERNALREFERENCE
0V TO 2.5VINPUT
4 MHz/1.8MHz OSCILLATOR
SERIAL CLOCKINPUT
200kHz/100kHz PULSE GENERATOR
CH1
CH2
CH3
CH4
OSCILLOSCOPE
OPTIONALEXTERNALREFERENCE
AD780/REF-192
SERIAL DATA INPUT
CH5
PULSE GENERATOR
DATA GENERATOR4 LEADINGZEROS FORADC DATA
Figure 10. Typical Circuit
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with 4 leading zeros followed by the MSB of the 12-bit result.Note that after the AVDDand DVDD power-up the part willrequire 150 ms for the internal reference to settle and for the au-tomatic calibration on power-up to be completed.
For applications where power consumption is a major concernthen the SLEEPpin can be connected to DGND. See Power-Down section for more detail on low power applications.
ANALOG INPUT
The equivalent circuit of the analog input section is shown inFigure 11. During the acquisition interval the switches are bothin the track position and the AIN(+) charges the 20 pF capacitorthrough the 125 resistance. On the rising edge of CONVSTswitches SW1 and SW2 go into the hold position retainingcharge on the 20 pF capacitor as a sample of the signal onAIN(+). The AIN() is connected to the 20 pF capacitor, andthis unbalances the voltage at node A at the input of the com-parator. The capacitor DAC adjusts during the remainder of theconversion cycle to restore the voltage at node A to the correctvalue. This action transfers a charge, representing the analog in-
put signal, to the capacitor DAC which in turn forms a digitalrepresentation of the analog input signal. The voltage on theAIN() pin directly influences the charge transferred to the ca-pacitor DAC at the hold instant. If this voltage changes duringthe conversion period, the DAC representation of the analog in-put voltage will be altered. Therefore it is most important thatthe voltage on the AIN() pin remains constant during the con-version period. Furthermore it is recommended that the AIN()pin is always connected to AGND or to a fixed dc voltage.
Acquisition Time
The track and hold amplifier enters its tracking mode on thefalling edge of the BUSY signal. The time required for the trackand hold amplifier to acquire an input signal will depend onhow quickly the 20 pF input capacitance is charged. The acqui-
sition time is calculated using the formula:
tACQ = 9 ( RIN+ 125) 20 pF
where RIN is the source impedance of the input signal, and125 , 20 pF is the input R, C.
AIN(+)
AIN()
125
20pF
TRACK
HOLD
CAPACITORDAC
COMPARATORHOLDTRACK
AGND
125
SW1
SW2
NODE A
Figure 11. Analog Input Equivalent Circuit
DC/AC Applications
For dc applications high source impedances are acceptable pro-vided there is enough acquisition time between conversions tocharge the 20 pF capacitor. The acquisition time can be calcu-lated from the above formula for different source impedances.For example with RIN= 5 k, the required acquisition time willbe 922 ns.
For ac applications, removing high frequency components fromthe analog input signal is recommended by use of an RC low-pass filter on the AIN(+) pin as shown in Figure 13. In applica-tions where harmonic distortion and signal to noise ratio arecritical the analog input should be driven from a low impedancesource. Large source impedances will significantly affect the acperformance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a func-tion of the particular application.
When no amplifier is used to drive the analog input the sourceimpedance should be limited to low values. The maximumsource impedance will depend on the amount of total harmonicdistortion (THD) that can be tolerated. The THD will increaseas the source impedance increases and performance will de-grade. Figure 12 shows a graph of the total harmonic distortionversus analog input signal frequency for different source imped-ances. With the setup as in Figure 13, the THD is at the 90 dBlevel. With a source impedance of 1 kand no capacitor on theAIN(+) pin, the THD increases with frequency.
INPUT FREQUENCY kHz
76
920 10020
THD
dB
40 60
80
84
88
80
THD vs. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
RIN= 1k
RIN= 50, 10nF
AS IN FIGURE 13
Figure 12. THD vs. Analog Input Frequency
In a single supply application (both 3 V and 5 V), the V+ andV of the op amp can be taken directly from the supplies to theAD7858/AD7858L which eliminates the need for extra externalpower supplies. When operating with rail-to-rail inputs and out-puts, at frequencies greater than 10 kHz care must be taken inselecting the particular op amp for the application. In particularfor single supply applications the input amplifiers should beconnected in a gain of 1 arrangement to get the optimum per-formance. Figure 13 shows the arrangement for a single supplyapplication with a 50 and 10 nF low-pass filter (cutoff fre-quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a
capacitor with good linearity to ensure good ac performance.Recommended single supply op amps are the AD820 and theAD820-3 V.
IC1
AD820AD820-3V
0.1F10F
V+
V
10k
50
10nF(NPO)
TO AIN(+) OFAD7858/AD7858L
VIN(0 TO VREF)
VREF
10k
10k
10k
+3V TO +5V
Figure 13. Analog Input Buffering
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Input Range
The analog input range for the AD7858/AD7858L is 0 V toVREF. The AIN() pin on the AD7858/AD7858L can be biasedup above AGND, if required. The advantage of biasing thelower end of the analog input range away from AGND is thatthe user does not need to have the analog input swing all theway down to AGND. This has the advantage in true single sup-
ply applications that the input amplifier does not need to swingall the way down to AGND. The upper end of the analog inputrange is shifted up by the same amount. Care must be taken sothat the bias applied does not shift the upper end of the analoginput above the AVDDsupply. In the case where the reference isthe supply, AVDD, the AIN() must be tied to AGND.
AIN(+)
AIN()
AD7858/AD7858L
DOUT
TRACK AND HOLDAMPLIFIER STRAIGHT
BINARYFORMAT
VIN= 0 TO VREF
Figure 14. 0 to VREFInput Configuration
Transfer Function
For the AD7858/AD7858L input range the designed code tran-sitions occur midway between successive integer LSB values(i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS 3/2 LSBs). Theoutput coding is straight binary for the unipolar range with1 LSB = FS/4096 = 3.3 V/4096 = 0.8 mV when VREF= 3.3 V.The ideal input/output transfer characteristic is shown inFigure 15.
+FS 1LSB
1LSB =FS
4096
OUTPUTCODE
0V
111...111
111...110
111...101
111...100
000...011
000...001
000...000
000...010
VIN= (AIN(+) AIN()), INPUT VOLTAGE
1LSB
Figure 15. AD7858/AD7858L Transfer Characteristic
REFERENCE SECTION
For specified performance, it is recommended that when usingan external reference this reference should be between 2.3 Vand the analog supply AVDD. The connections for the relevant
reference pins are shown in the typical connection diagrams. Ifthe internal reference is being used, the REFIN/REFOUTpinshould have a 10 nF capacitor connected to AGND very closeto the REFIN/REFOUTpin. These connections are shown inFigure 16.
If the internal reference is required for use external to the ADC,it should be buffered at the REF
IN/REF
OUTpin and a 10 nF
connected from this pin to AGND. The typical noise performancefor the internal reference, with 5 V supplies is 150 nV/Hz@1 kHz and dc noise is 100 V p-p.
AVDD DVDD
CREF1
CREF2
REFIN/REFOUT
AD7858/AD7858L
ANALOG SUPPLY+3V TO +5V
0.1F0.1F10F
0.1F
0.01F
0.01F
Figure 16. Relevant Connections When Using Internal
Reference
The other option is that the REFIN/REFOUTpin be overdrivenby connecting it to an external reference. This is possible due tothe series resistance from the REFIN/REFOUTpin to the internalreference. This external reference can have a range that includesAVDD. When using AVDDas the reference source, the 10 nF ca-pacitor from the REFIN/REFOUTpin to AGND should be asclose as possible to the REFIN/REFOUTpin, and also the CREF1
pin should be connected to AVDDto keep this pin at the samelevel as the reference. The connections for this arrangement areshown in Figure 17. When using AVDDit may be necessary toadd a resistor in series with the AVDDsupply. This will have theeffect of filtering the noise associated with the AVDDsupply.
AVDD DVDD
CREF1
CREF2
REFIN/REFOUT
AD7858/AD7858L
ANALOG SUPPLY+3V TO +5V
0.1F0.1F10F
0.1F
0.01F
0.01F
Figure 17. Relevant Connections When Using AVDDas the
Reference
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AD7858/AD7858L PERFORMANCE CURVES
Figure 18 shows a typical FFT plot for the AD7858 at 200 kHzsample rate and 10 kHz input frequency.
FREQUENCY kHz
0
20
1200 10020
SNR
dB
40 60
40
60
80
80
100
AVDD= DVDD= 3.3V
FSAMPLE= 200kHz
FIN= 10kHz
SNR = 72.04dBTHD = 88.43dB
Figure 18. FFT Plot
Figure 19 shows the SNR versus Frequency for different sup-plies and different external references.
INPUT FREQUENCY kHz
74
73
690 10020
S(N+D)RATIO
dB
40 80
72
71
70
60
AVDD= DVDDWITH 2.5V REFERENCE
UNLESS STATED OTHERWISE
5.0V SUPPLIES, WITH 5V REFERENCE
5.0V SUPPLIES
5.0V SUPPLIES, L VERSION
3.3V SUPPLIES
Figure 19. SNR vs. Frequency
Figure 20 shows the Power Supply Rejection Ratio versus Fre-quency for the part. The Power Supply Rejection Ratio is de-fined as the ratio of the power in adc output at frequency f tothe power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in adc output, Pfs = power of a
full-scale sine wave. Here a 100 mV peak-to-peak sine wave iscoupled onto the AVDDsupply while the digital supply is left un-altered. Both the 3.3 V and 5.0 V supply performances areshown.
INPUT FREQUENCY kHz
80
900 10020
PSRR
dB
40 60
82
84
86
88
80
AVDD = DVDD= 3.3V/5.0V,
100mVpk-pk SINE WAVE ON AVDD
3.3V
5.0V
Figure 20. PSRR vs. Frequency
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POWER-DOWN OPTIONS
The AD7858/AD7858L should be left idle for 150 ms typicallyafter the AVDDand the DVDDpower-up to allow for the internalreference to settle and the automatic calibration on power up tobe completed. The SLEEPpin can be hardwired to DGNDbefore power-up as the part will disable the function of theSLEEPpin while the automatic calibration on power-up is be-
ing performed.
The AD7858/AD7858L provides a number of power-down op-tions. The two modes are the Full Power-Down and the PartialPower-Down. These options are controlled by the PMGT1 andPMGT0 bits in the Control Register. When both these bits are0 (default status on power-up), the SLEEPpin determineswhether the AD7858/AD7858L is in normal mode of operationor whether it enters Full Power-Down mode after every conver-sion. With these bits at 0, 1 the AD7858/AD7858L operates innormal mode regardless of the status of the SLEEP. With thesebits at 1, 0 the part enters a Full Power-Down mode, again in-dependent of the SLEEPpin. Finally, with these bits at 1, 1 the
Table VI. Power Management Options
PMGT1 PMGT0 SLEEP
Bit Bit Pin Comment
0 0 0 Full Power-Downif NotCalibrating or Converting(Default ConditionAfter Power On)
0 0 1 Normal Operation0 1 X Normal Operation
(Independent of the SLEEPPin)1 0 X Full Power-Down1 1 X Partial Power-Downif Not
Converting
part enters its Partial Power-Down. The advantage of the partialpower-down is that the part will require significantly less time topower-up than from the full power-down. In this partialpower-down the reference voltage stays powered up so if this isbeing used external to the AD7858/AD7858L it is still availableeven though the AD7858/AD7858L is effectively powereddown. Table VI summaries the power management options
while Table VII shows typical power-up times when using the2.5 V internal reference. The capacitor values between CREF1,CREF2, REFIN/REFOUTand AGND are also listed. The power-up time is defined as the time taken for the output code to settleto within 0.5 LSBs of its final value. If a power-up timeshorter than that quoted in Table VII is used, the error associ-ated with the output code will increase. For a power-up time of10 s from partial power-down mode the output code will besettled to within 3 LSBs typically of its final value. When usingAVDDas the reference, the power-up time required will be lessthan the figures quoted in Table VII.
Table VII. Power-Up Times
Reference Power-UpCREF1 CREF2 Capacitor Power-Down Delay
(nF) (nF) (nF) Mode (s)
100 10 0.1 Full 300100 10 0.1 Partial 5010 1 0.1 Full 30010 1 0.1 Partial 50
A typical connection diagram for a low power application isshown in Figure 21 (AD7858L is the low power version of theAD7858).
Figure 21. Typical Low Power Circuit
AUTO POWERDOWN AFTER
CONVERSION
AUTO CAL ONPOWER-UP
AVDD DVDD
AIN(+)
AIN()
CREF1
CREF2
SLEEP
DIN
DOUT
SYNC
CONVST
AGND
DGND
CLKIN
SCLK
REFIN/REFOUT
AD7858L
ANALOGSUPPLY
+3V0.1F0.1F10F
0.1F
0.01F
MASTER CLOCKINPUT
CONVERSIONSTART INPUT
SERIAL DATA OUTPUT
0.1nF
CAL0.01F
INTERNALREFERENCE
0V TO 2.5VINPUT
1.8MHz OSCILLATOR
SERIAL CLOCKINPUT
100kHz PULSE GENERATOR
OPTIONALEXTERNALREFERENCE
REF-192
SERIAL DATA INPUT
LOW POWERC/P
CURRENT, I = 1.5mA TYP
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POWER-UP/DOWN SEQUENCE
Power-up times and throughput rates quoted in this section arebased on using the 2.5 V internal reference. If an external refer-ence is used and is powered-on constantly, or if AVDDis used asthe reference, then the power-up times will be shorter and thethroughput rates higher.
When using the CONVSTpin, instead of the CONVST bit inthe control register, to start conversion care must be taken onthe CONVSTpulse width for bringing the part out of power-down. The CONVSTfalling edge will wake up the device andCONVSTmust remain low for at least the power-up timequoted in Table VII. This will allow the part to be settled beforethe start of the next conversion. Figure 22 shows the timing ofCONVSTfor bringing the part out of full power-down.
POWER-UPTIME
NORMALOPERATION
FULLPOWER-DOWN
CYCLE TIME
300sCONVST
BUSY
Figure 22. Power-Up Timing When Using CONVSTPin
Writing to AD7858/AD7858L
The sequence of events here use the CONVST bit in the controlregister to start the conversion. Alternatively the CONVSTpinmay be used as in Figure 22. When writing to the AD7858/AD7858L there are a number of different ways in utilizing thepower-down options. For applications which require throughputrates of less than 2 kHz a full/partial power-down mode combi-nation, or a full power-down mode on its own, may be used.For higher throughput rates the partial power-down mode
should be used. Table VIII shows the recommended power-down mode for lowest current at a given throughput rate. Notethat higher throughput rates will also be limited by the numberof channels converted and read while powered up.
Table VIII. Recommended Power-Down Mode for Lowest IDD
Power-Down Mode Maximum Throughput Range
Full/Partial Combination 2 kHzPartial 16 kHz (1 Channel)
7 kHz (8 Channels)
Using Full and Partial Power-Down Combination
Using a full and partial power-down mode combination has thebenefits of the low current associated with a full power-down
and the speed of powering up from a partial power-down. It willalso give the lowest current for a given throughput rate, onethird of the current when using the full power-down mode on itsown. Figure 23 and 24 show the recommended sequence andthe relevant timing signals where only one channel is convertedand read while powered-up. If required all 8 channels may beconverted and read while powered-up. For the all 0s write op-
eration described in the sequence only the two MSBs need to be0 to ensure that the rest of the data write is ignored, but it is justas easy to write all 0s. The Supply Current versus ThroughputRate for this power-up/power-down sequence is shown inFigure 25.
START
WRITE TO CONTROL REGISTER SETTING CHANNEL,AND BITS CONVST = 1, PMGT1 = PMGT0 = 0
POWER-ON, WAIT 150ms FORAUTOMATIC CALIBRATION
SLEEPPIN TIED TO DGND
CONVERSION PERFORMED AND PARTENTERS FULL POWER-DOWN
READ DATA FROM DEVICE AND WRITEALL 0s AT THE SAME TIME
360s BEFORE POWER-UP REQUIREDWRITE TO CONTROL REGISTERSETTING PMGT1 = PMGT0 = 1
WAIT FOR 300s POWER-UP TIME FROMFULL TO PARTIAL POWER-DOWN MODE
WRITE TO CONTROL REGISTER SETTINGNORMAL OPERATION, PMGT1 = 0, PMGT0 = 1
WAIT 50s POWER-UP TIME
Figure 24. Flowchart for Full and Partial Power-Down
Mode Combination
1000
100
1
10
THROUGHPUT Hz
AVERAGE
CURRENTA
0 200 400 600 800 1000 1200 1400 1600 1800 2000
AD7858L (1.8MHz EXTERNAL CLOCK)FULL/PARTIAL POWER-DOWN
8 CHANNELS
1 CHANNEL
Figure 25. Supply Current vs. Throughput Rate with Full
and Partial Power-Down Combination (Sequence as Illus-trated in Figures 23 and 24)
Figure 23. Timing Sequence for Full and Partial Power-Down Combination
READ
WRITE
READ
WRITE WRITE WRITEALL 0s ALL 0sDIN (I/P)
SYNC(I/P)
BUSY (O/P)
DOUT (O/P)
FULLPOWER-DOWN 300s 50s
NORMALOPERATION
FULLPOWER-DOWN
CONVERSIONTIME
PARTIALPOWER-DOWN
FULL CYCLE TIME
16 DATA BITSIGNORED
16 DATA BITREAD
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Full Power-Down or Partial Power-Down
In some applications it may not be feasible to use a combinationof full and partial power-down as shown in Figures 23 and 24.This may be for software overhead reasons or for applicationsrequiring throughput rates grater than 2 kHz.
Using full power-down only allows for a maximum throughputrate of 2 kHz but the supply current will be three times orgreater than for the full/partial power-down combination se-quence described in Figures 23 and 24.
START
WRITE TO CONTROL REGISTER SETTING CHANNEL,AND BITS CONVST = 1, PMGT1 = PMGT0 = 0
POWER-ON, WAIT 150ms FORAUTOMATIC CALIBRATION
SLEEPPIN TIED TO DVDD
CONVERSION PERFORMED AND PARTENTERS FULL POWER-DOWN
READ DATA FROM DEVICE AND WRITEALL 0s AT THE SAME TIME
60s BEFORE POWER-UP REQUIREDWRITE TO CONTROL REGISTER SETTING
NORMAL OPERATION, PMGT1 = PMGT0 = 1
WAIT 50s POWER-UP TIME
Figure 27. Flowchart for Partial Power-Down Only
Using partial power-down allows for throughput rates up to16 kHz (if AVDDis used as the reference the throughput rateswill be >16 kHz). Figures 26 and 27 show the timing/flowchartfor power-up/down when using the partial power-down modeonly. Figure 28 shows the Supply Current versus Throughput ratefor this sequence.
10000
1000
100
THROUGHPUT Hz
AVERAGE
CURRENTA
0 2000 4000 6000 8000 10000 12000 14000 16000 18000
AD7858L (1.8MHz EXTERNAL CLOCK)PARTIAL POWER-DOWN
8 CHANNELS
1 CHANNEL
Figure 28. Supply Current vs. Throughput Rate with
Partial Power-Down Only (Sequence as Illustrated in
Figures 26 and 27)
NOTE
When setting the power-down modes by writing to the part, it isrecommended to be operating in an interface mode other thaninterface Modes 4, and 5. This way the user has more controlwhen to initiate power-down, and power-up commands.
Figure 26. Timing Sequence for Partial Power-Down Only
READ
WRITE
READ
WRITE WRITEALL 0s ALL 0sDIN (I/P)
SYNC(I/P)
BUSY (O/P)
DOUT (O/P)
FULLPOWER-DOWN 50s
NORMALOPERATION
PARTIALPOWER-DOWN
CONVERSIONTIME
FULL CYCLE TIME
16 DATA BITSIGNORED
16 DATA BITREAD
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CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power up en-sures that the calibration options covered in this section will notbe required in a significant amount of applications. The userwill not have to initiate a calibration unless the operating condi-tions change (CLKIN frequency, analog input mode, reference
voltage, temperature, and supply voltages). The AD7858/AD7858L have a number of calibration features that may berequired in some applications and there are a number of advan-tages in performing these different types of calibration. First, theinternal errors in the ADC can be reduced significantly to givesuperior dc performance, and secondly, system offset and gainerrors can be removed. This allows the user to remove referenceerrors (whether it be internal or external reference) and to makeuse of the full dynamic range of the AD7858/AD7858L by ad-justing the analog input range of the part for a specific system.
There are two main calibration modes on the AD7858/AD7858L,self-calibration and system calibration. There are various op-tions in both self-calibration and system calibration as outlinedpreviously in Table IV. All the calibration functions can be initi-ated by pulsing the CALpin or by writing to the control registerand setting the STCAL bit to 1. The timing diagrams that fol-low involve using the CALpin.
The duration of each of the different types of calibrations isgiven in Table IX for the AD7858 with a 4 MHz master clock.These calibration times are master clock dependent. Therefore,the calibrating times for the AD7858L (CLKIN = 1.8 MHz)will be longer than those quoted in Table IX.
Table IX. Calibration Times (AD7858 with 4 MHz CLKIN)
Type of Self- or
System Calibration Time
Full 31.25 msOffset + Gain 6.94 msOffset 3.47 msGain 3.47 ms
Automatic Calibration on Power-On
The CALpin has a 0.15 A pull up current source connected toit internally to allow for an automatic full self-calibration onpower-on. A full self-calibration will be initiated on power-on ifa 10 nF capacitor is connected from the CALpin to AGND.The internal current source connected to the CALpin chargesup the external capacitor and the time required to charge the ex-ternal capacitor will be 100 ms approximately. This time is largeenough to ensure that the internal reference is settled before thecalibration is performed. However, if an external reference is be-ing used, this reference must have stabilized before the auto-matic calibration is initiated (if larger time than 100 ms isrequired then a larger capacitor on the CALpin should beused). After this 100 ms has elapsed the calibration will beperformed which will take 32 ms/72 ms (4 MHz/1.8 MHzCLKIN). Therefore, 132 ms/172 ms should be allowed beforeoperating the part. After calibration, the part is accurate to the12-bit level and the specifications quoted on the data sheet ap-ply. There will be no need to perform another calibration unlessthe operating conditions change or unless a system calibration isrequired.
Self-Calibration Description
There are a four different calibration options within the self-calibration mode. First, there is a full self-calibration where theDAC, internal gain, and internal offset errors are calibrated out.Then, there is the (Gain + Offset) self-calibration which cali-brates out the internal gain error and then the internal offset er-rors. The internal DAC is not calibrated here. Finally, there are
the self-offset and self-gain calibrations which calibrate out theinternal offset errors and the internal gain errors respectively.
The internal capacitor DAC is calibrated by trimming each ofthe capacitors in the DAC. It is the ratio of these capacitors toeach other that is critical, and so the calibration algorithm en-sures that this ratio is at a specific value by the end of the cali-bration routine. For the offset and gain there are two separatecapacitors, one of which is trimmed when an offset or gain cali-bration is performed. Again, it is the ratio of these capacitors tothe capacitors in the DAC that is critical and the calibration al-gorithm ensures that this ratio is at a specified value for both theoffset and gain calibrations.
The zero-scale error is adjusted for an offset calibration, and the
positive full-scale error is adjusted for a gain calibration.Self-Calibration Timing
The diagram of Figure 29 shows the timing for a full self-calibration. Here the BUSY line stays high for the full length ofthe self-calibration. A self-calibration is initiated by bringing theCALpin low (which initiates an internal reset) and then highagain or by writing to the control register and setting theSTCAL bit to 1 (note that if the part is in a power-down mode theCALpulse width must take account of the power-up time ). TheBUSY line is triggered high from the rising edge of CAL(or theend of the write to the control register if calibration is initiatedin software), and BUSY will go low when the full-self calibra-tion is complete after a time tCALas shown in Figure 29.
For the self- (gain + offset), self-offset and self-gain calibrationsthen the BUSY line will be triggered high by the rising edge ofthe CALsignal (or the end of the write to the control register ifcalibration is initiated in software) and will stay high for the fullduration of the self calibration. The length of time that theBUSY is high for will depend on the type of self calibration thatis initiated. Typical figures are given in Table IX. The timingdiagrams for the other self-calibration options will be similar tothat outlined in Figure 29.
t1= 100ns MIN,t15= 2.5 tCLKINMAX,tCAL= 125013 tCLKIN
CAL(I/P)
BUSY (O/P)
t1
t15
tCAL
Figure 29. Timing Diagram for Full-Self Calibration
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System Calibration Description
System calibration allows the user to take out system errors ex-ternal to the AD7858/AD7858L as well as calibrate the errors ofthe AD7858/AD7858L itself. The maximum calibration rangefor the system offset errors is 5% of VREFand for the systemgain errors is 2.5% of VREF. This means that the maximum al-lowable system offset voltage applied between the AIN(+) and
AIN() pins for the calibration to adjust out this error is 0.05 VREF (i.e., the AIN(+) can be 0.05 VREFabove AIN() or 0.05 VREFbelow AIN()). For the System gain error the maximum al-lowable system full-scale voltage that can be applied betweenAIN(+) and AIN() for the calibration to adjust out this error isVREF 0.025VREF (i.e. the AIN(+) can be VREF+ 0.025 VREFabove AIN() or VREF 0.025 VREFabove AIN()). If thesystem offset or system gain errors are outside the ranges men-tioned the system calibration algorithm will reduce the errors asmuch as the trim range allows.
Figures 30 through 32 illustrate why a specific type of systemcalibration might be used. Figure 30 shows a system offset cali-bration (assuming a positive offset) where the analog inputrange has been shifted upwards by the system offset after thesystem offset calibration is completed. A negative offset mayalso be accounted for by a system offset calibration.
MAX SYSTEM FULL SCALEIS 2.5% FROM VREF
ANALOGINPUTRANGE
VREF 1LSB
SYS OFFSET
AGND
VREF+ SYS OFFSET
MAX SYSTEM OFFSETIS 5% OF VREF
ANALOGINPUTRANGE
VREF 1LSB
SYS OFFSET
AGND
SYSTEM OFFSET
CALIBRATION
MAX SYSTEM OFFSETIS 5% OF VREF
Figure 30. System Offset Calibration
Figure 31 shows a system gain calibration (assuming a systemfull scale greater than the reference voltage) where the analoginput range has been increased after the system gain calibrationis completed. A system full-scale voltage less than the referencevoltage may also be accounted for by a system gain calibration.
MAX SYSTEM FULL SCALEIS 2.5% FROM VREF
ANALOGINPUTRANGE
VREF 1LSB
AGND
SYS F.S.
ANALOGINPUTRANGE
VREF 1LSB
SYS F.S.
AGND
SYSTEM GAIN
CALIBRATION
MAX SYSTEM FULL SCALEIS 2.5% FROM VREF
Figure 31. System Gain Calibration
Finally in Figure 32 both the system offset and gain are ac-counted for by the a system offset followed by a system gaincalibration. First the analog input range is shifted upwards bythe positive system offset and then the analog input range isadjusted at the top end to account for the system full scale.
ANALOGINPUTRANGE
SYS F.S.
SYS OFFSET
VREF+ SYS OFFSET
ANALOGINPUTRANGE
VREF 1LSB
SYS F.S.
AGND
SYSTEM OFFSETCALIBRATION
FOLLOWED BY
SYSTEM GAINCALIBRATION
MAX SYSTEM FULL SCALE
IS2.5% FROM VREF
SYS OFFSET
MAX SYSTEM OFFSETIS 5% OF VREF
MAX SYSTEM OFFSETIS 5% OF VREF
AGND
VREF 1LSB
MAX SYSTEM FULL SCALE
IS2.5% FROM VREF
Figure 32. System (Gain + Offset) Calibration
System Gain and Offset Interaction
The inherent architecture of the AD7858/AD7858L leads to aninteraction between the system offset and gain errors when asystem calibration is performed. Therefore, it is recommendedto perform the cycle of a system offset calibration followed by asystem gain calibration twice. Separate system offset and systemgain calibrations reduce the offset and gain errors to at least the12-bit level. By performing a system offset CALfirst and a sys-tem gain calibration second, priority is given to reducing thegain error to zero before reducing the offset error to zero. If thesystem errors are small, a system offset calibration would be performed, followed by a system gain calibration. If the systems er-rors are large (close to the specified limits of the calibrationrange), this cycle would be repeated twice to ensure that the off-set and gain errors were reduced to at least the 12-bit level. The
advantage of doing separate system offset and system gain cali-brations is that the user has more control over when the analoginputs need to be at the required levels, and the CONVSTsig-nal does not have to be used.
Alternatively, a system (gain + offset) calibration can beperformed. It is recommended to perform three system (gain +offset) calibrations to reduce the offset and gain errors to the12-bit level. For the system (gain + offset) calibration priority igiven to reducing the offset error to zero before reducing thegain error to zero. Thus if the system errors are small then twosystem (gain + offset) calibrations will be sufficient. If the sys-tem errors are large (close to the specified limits of the calibra-tion range) three system (gain + offset) calibrations may be
required to reduced the offset and gain errors to at least the 12-bit level. There will never be any need to perform more thanthree system (offset + gain) calibrations.
The zero scale error is adjusted for an offset calibration and thepositive full-scale error is adjusted for a gain calibration.
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System Calibration Timing
The calibration timing diagram in Figure 33 is for a full systemcalibration where the falling edge of CALinitiates an internalreset before starting a calibration (note that if the part is in power-down mode the CALpulse width must take account of the power-up
time). If a full system calibration is to be performed in softwareit is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to beprogrammed in the middle of the system calibration sequence.The rising edge of CALstarts calibration of the internal DACand causes the BUSY line to go high. If the control register isset for a full system calibration, the CONVSTmust be usedalso. The full-scale system voltage should be applied to the ana-log input pins from the start of calibration. The BUSY line willgo low once the DAC and System Gain Calibration are com-plete. Next the system offset voltage is applied to the AIN pinfor a minimum setup time (tSETUP) of 100 ns before the risingedge of the CONVSTand remain until the BUSY signal goeslow. The rising edge of the CONVSTstarts the system offsetcalibration section of the full system calibration and also causesthe BUSY signal to go high. The BUSY signal will go low after a
time tCAL2when the calibration sequence is complete. In someapplications not all the input channels may be used. In this caseit may be useful to dedicate two input channels for the systemcalibration, one which has the system offset voltage applied to it,and one which has the system full scale voltage applied to it.When a system offset or gain calibration is performed, the chan-nel selected should correspond to the system offset or systemfull-scale voltage channel.
The timing for a system (gain + offset) calibration is very similarto that of Figure 33 the only difference being that the time tCAL1will be replaced by a shorter time of the order of t CAL2as the in-ternal DAC will not be calibrated. The BUSY signal will signifywhen the gain calibration is finished and when the part is ready
for the offset calibration.
t1= 100ns MIN, t14= 50/90ns MIN 5V/3V,t15= 2.5 tCLKINMAX, tCAL1= 111114 tCLKIN,
tCAL2= 13899 tCLKIN
CAL(I/P)
BUSY (O/P)
CONVST(I/P)
t1
AIN (I/P)
t15
tCAL1 tCAL2t16
tSETUP
VSYSTEM FULL SCALE VOFFSET
Figure 33. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibra-tion is shown in Figure 34. Here again the CALis pulsed andthe rising edge of the CALinitiates the calibration sequence (orthe calibration can be initiated in software by writing to the con-trol register). The rising edge of the CALcauses the BUSY lineto go high and it will stay high until the calibration sequence isfinished. The analog input should be set at the correct level for a
minimum setup time (tSETUP) of 100 ns before the rising edge ofCALand stay at the correct level until the BUSY signal goes low.
CAL(I/P)
BUSY (O/P)
t1
AIN (I/P)
t15
tCAL2tSETUP
VSYSTEM FULL SCALEOR
VSYSTEM OFFSET
Figure 34. Timing Diagram for System Gain or System
Offset Calibration
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SERIAL INTERFACE SUMMARY
Table X details the two interface modes and the serial clockedges from which the data is clocked out by the AD7858/AD7858L (DOUT Edge) and that the data is latched in on(DIN Edge).
In both interface Modes 1, and 2 the SYNCis gated with theSCLK. Thus the SYNCmay clock out the MSB of data. Sub-sequent bits will be clocked out by the Serial Clock, SCLK. Thecondition for the SYNCclocking out the MSB of data is asfollows:
The falling edge of SYNCwill clock out the MSB if the serial clock
is low when the SYNCgoes low.
If this condition is not the case, the SCLK will clock out theMSB. If a noncontinuous SCLK is used, it should idle high.
Table X. SCLK Active Edges
Interface Mode DOUT Edge DIN
Edge
1, 2 SCLK SCLKResetting the Serial Interface
When writing to the part via the DIN line there is the possibilityof writing data into the incorrect registers, such as the test regis-ter for instance, or writing the incorrect data and corrupting theserial interface. The SYNCpin acts as a reset. Bringing theSYNCpin high resets the internal shift register. The first databit after the next SYNCfalling edge will now be the first bit of anew 16-bit transfer. It is also possible that the test register con-tents were altered when the interface was lost. Therefore, once
the serial interface is reset it may be necessary to write the 16-biword 0100 0000 0000 0000 to restore the test register to its de-fault value. Now the part and serial interface are completely re-set. It is always useful to retain the ability to program the SYNCline from a port of the Controller/DSP to have the ability to re-set the serial interface.
Table XI summarizes the interface modes provided by theAD7858/AD7858L. It also outlines the various P/C to whichthe particular interface is suited.
Interface Mode 1 may only be set by programming the controlregister ( See section on Control Register).
Some of the more popular Processors, Controllers, and theDSP machines that the AD7858/AD7858L will interface to di-rectly are mentioned here. This does not cover all Cs, Ps andDSPs. A more detailed timing description on each of the inter-face modes follows.
Table XI. Interface Mode Description
Interface Processor/
Mode Controller Comment
1 8XC51 (2-Wire)8XL51 (DIN Is an Input/PIC17C42 Output Pin)
2 68HC11 (3-Wire, SPI)68L11 (Default Mode)68HC16PIC16C64ADSP21XXDSP56000DSP56001DSP56002DSP56L002
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DETAILED TIMING SECTION
Mode 1 (2-Wire 8051 Interface)
The read and writing takes place on the DIN line and the con-version is initiated by pulsing the CONVSTpin (note that in ev-ery write cycle the 2/3MODE bit must be set to 1). Theconversion may be started by setting the CONVST bit in thecontrol register to 1 instead of using the CONVSTpin.
Below in Figure 35 and in Figure 36 are the timing diagrams forOperating Mode 1 in Table XI where we are in the 2-wire inter-face mode. Here the DIN pin is used for both input and outputas shown. The SYNCinput is level triggered active low and canbe pulsed (Figure 35) or can be constantly low (Figure 36).
In Figure 38 the part samples the input data on the rising edgeof SCLK. After the 16th rising edge of SCLK the DIN is con-figured as an output. When the SYNCis taken high the DIN is3-stated. Taking SYNClow disables the 3-state on the DIN pinand the first SCLK falling edge clocks out the first data bit.Once the 16 clocks have been provided the DIN pin will auto-matically revert back to an input after a time t14. Note that a
