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FEATURESFull-Featured Evaluation Board for the AD9831Various Linking OptionsPC Software for Control of AD9831

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices forits use; nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

One Technology Way; P.O.BOX 9106; Norwood , MA 02062-9106 U.S.A.Tel: 617/329-4700 Twx: 710/394-6577Telex: 174059 Cables: ANALOG NORWOOD MASS

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source via a B N C conn ector. L atches (74H C 57 4) are also onthe bo ard, these latches being u sed to hold the 16 -bit dataw ord b eing w ritten from the P C to the A D 9831 .

OPERATING THE AD9831 EVALUATION BOARDPower SuppliesT his evaluation bo ard has tw o an alog p ow er supp ly inp uts:A V D D an d A G N D . A V D D eq u als + 5 V o r + 3 .3 V a nd isused to provide the A V D D for the A D 9831. D G N D andD V D D connections are also available. T he D V D D is used toprovide the D V D D for the A D 983 1, the 25 M H z oscillatorand the D V D D for the logic chips. D G N D and A G N D are

conn ected at the A D 98 31. T herefore, it is recom m end ed no tto connect A G N D and D G N D elsewhere in the system .

A ll pow er sup plies are decoupled to ground. A V D D andD V D D are decoupled using 10 F tantalum capacitors and0.1 F ceram ic cap acitors at the input to the evaluation board.T he p ow er supplies are again d ecou pled u sing 0.1 F capaci-tors at the A D 98 31 , the crystal and the log ic.

Evaluation Board for the AD983Direct Digital Synthesizer

INTRODUCTIONT his A pplication N ote describes the evaluation bo ard for theA D 9831 D irect D igital Syn thesizer (D D S). T he A D 9831 is anum erically con trolled oscillator em ploy ing a ph ase accum ula-tor, a sine loo k-up table and a 10-bit D /A con verter. T hepart can b e op erated w ith clock frequen cies up to 25 M H z.B oth p hase m od ulation and frequen cy m od ulation can be p er-form ed w ith the A D 98 31. F ull data on the A D 983 1 is avail-

able in the A D 98 31 d atasheet available from A nalog D evicesand shou ld b e con sulted in co njunction w ith this A pplicationN ote w hen using the evaluation bo ard.

T he evaluation bo ard interfaces to the parallel port of an IB Mcom patible P C . Softw are is availab le w ith the evaluationbo ard w hich allow s the u ser to easily p rogram the A D 983 1.

C om pon ents on the A D 9831 E valuation B oard includ e a 25M H z oscillator w hich provides the M C L K for the A D 9831 .T he u ser can rem ove this oscillator, if required, and drive theA D 98 31 w ith a d ifferent clock oscillator or an ex ternal clock

Evaluation Board Setup

Parallel Port CentronicsPrinter Cable

IBM Compatible PC

AD9831.EXEAD9831 Evaluation

Board

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EVAL-AD9831EB

Link and Switch Options

T here are five link op tion s w hich m ust be set for the requ ired op erating setup b efore using the evaluation bo ard. T he fun ction sof these op tion s are ou tlined below .

Link No. FunctionL K 1 T he PSEL 1 input can be controlled by the user via a B N C connector or, alternatively, by sw itch SW .

W hen L K 1 is arranged so that P S E L 1 is connected to S W , the u ser can con trol the P S E L 1 signal using thedo ub le throw sw itch.

A lternatively, P S E L 1 can b e tied to a B N C conn ector by altering L K 1 so that the u ser can p rovide the P SE L 1con trol from a log ic sou rce.

L K 2 T he PSEL 0 input can be controlled by the user via a B N C connector or, alternatively, by sw itch SW .

W hen L K 2 is arranged so that P S E L 0 is connected to S W , the u ser can con trol the P S E L 0 signal using thedo ub le throw sw itch.

A lternatively, P S E L 0 can b e tied to a B N C conn ector by altering L K 2 so that the u ser can p rovide the P SE L 0con trol from a log ic sou rce.

L K 3 T he FSE L EC T input can be controlled by the user via a BN C connector or, alternatively, by sw itch SW .

W hen L K 3 is arranged so that F SE L E C T is conn ected to S W , the user can control the F SE L E C T signal usingthe d ou ble throw sw itch.

A lternatively, F S E L E C T can b e tied to a B N C conn ector by altering L K 3 so that the u ser can p rovide theF SE L E C T control from a logic source.

L K 4 L K 4 is used to p lace the A D 9831 in sleep m o de.

W hen L K 4 is conn ected so that SLEEP is tied to D G N D , the A D 9831 is placed in sleep m ode w hereby theA D 9831 's internal clocks, R E F O U T and the D A C are disabled.

W hen L K 4 is conn ected so that SLEEP is tied to D V D D , the A D 9831 is pow ered up.

L K 5 T he reference to the AD 9831 can be provided by the on-board reference, w hich is available at R EF O U T , or anexternal reference o f no m inal value 1 .21 V can b e used. W hen L K 5 is closed, the on-bo ard reference is used.W hen this link is op ened, R E F IN is discon nected from R E F O U T and the reference can be provided b y theuser via a B N C connector.

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Preliminary Technical Data AD7002 EVAL-AD9831EB36-Way Connector Pin DescriptionD G N D D igital G ro un d. T h ese lin es are co nn ected

to the digital grou nd p lane on the evaluationboard.

D B0 - D B7 D ata B it 0 to D ata B it 7. D ata transfersfrom the P C are 8 b its w ide. T herefore, the16 bit w ord is split into tw o 8 bit w ords.F or each w rite operation , there are 3 trans-fers of data from the P C : the 8 M SB s of the16 bit w ord, the 8 L S B s of the 1 6 b it w ordand the ad dress data to b its A 0, A 1 an d A 2.T he A D 9831 accepts C M O S logic.

L O A D W hen the 8 M SB s of the 16 bit w ord arew ritten to the evaluation bo ard from the P C ,the w ord is held in a latch, a 74H C 57 4 latch.T his latch latch es in the data on the risingedge of the C K signal. T he LO A D signalp rovides this rising ed ge.

L AT C H T he 8 L SB s of the 16 bit w o rd are held inthe latch U 3. T he rising C K edge to thispart is provided by L A T C H .

WR W rite. T his is an active low log ic inputw hich is used to w rite the d igital data to theA D 9831 . W hen the address bits A 0, A 1 andA 2 are being w ritten to, the WR signal isgen erated also. O n the rising ed ge of WR ,the A D 98 31 reads in the 16 b it w ord fromthe 7 4H C 574 latches alon g w ith the ad dressvalues.

RESET R eset. W hen RESET is taken low , theA D 98 31 is reset. O n reset, the ph ase accu-m ulator is reset to zero.

SET-UP CONDITIONSC are sho uld be taken before app lying pow er and sign als to theevaluation board to en sure that all link p osition s are as per therequired operating m od e. T able 1 sho w s the p osition in w hichall the links are set w hen the evaluation board is sent ou t.

Table 1. Ini tial Link and Switch Positions

Link No. FunctionL K 1 L K 1 is arranged so that P SE L 1 is tied to

S W .

L K 2 L K 2 is arranged so that P SE L 0 is tied toS W .

L K 3 L K 3 is arranged so that F SE L E C T is tied toS W .

L K 4 L K 4 is connected so that SLEEP is tied toD V D D and, hence, the A D 9831 is poweredup .

L K 5 R E F O U T is tied to R E F IN .

S W A ll the S W sw itches are arranged so thatD V D D is selected.

EVALUATION BOARD INTERFACINGInterfacing to the evaluation bo ard is via a 3 6-w ay cen tronicsfem ale con nector, J1. T he p inou t for the J1 connector isshow n in F igure 1 an d its pin designation s are given in T able2.

Figure 1. Pin Configuration for the 36-Way Connector, J1.

36 19

1 18

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EVAL-AD9831EBTable 2. 36-Way Connector Pin Funtions

PIN NO. MNEMONIC1 L A T C H

2 D 0

3 D 1

4 D 2

5 D 3

6 D 4

7 D 5

8 D 6

9 D 7

14 RESET

19 D G N D

20 D G N D21 D G N D

22 D G N D

23 D G N D

24 D G N D

25 D G N D

26 D G N D

27 D G N D

28 D G N D

29 D G N D

30 D G N D

31 L O A D

36 WR

N ote: T he rem aind er of the p ins on the 36 -way conn ector are no conn ects.

SOCKETST here are six sockets relevan t to the operation of the A D 98 31on this evaluation board. T he fun ction of these sockets is out-lined in T able 3.

Table 3. Socket FunctionsSocket FunctionR E F IN S ub-M iniature B N C S ocket for R E F IN .

IO U T S ub-M iniature B N C S ocket for IO U T .

M C L K Sub-M iniature B N C S ocket for the M C L Kinput.

F SE L S ub-M iniature B N C S ocket for F SE L EC T .

P SE L 0 S ub-M iniature B N C S ocket for P SE L 0.

P SE L 1 S ub-M iniature B N C S ocket for P SE L 1.

CONNECTORST here are three connectors on the A D 98 31 evaluation board

as ou tlined in T able 4.

Table 4. Connector Functions

C onnector FunctionsJ1 36-W ay C entronics C onnector.

J2 P C B M ounting T erm inal B lock. T h e D igitalP ow er Sup ply to the E valuation B oard isp rovided via this C on nector.

J3 P C B M ounting T erm inal B lock. T he A na-log P ow er Sup ply to the E valuation B oard isp rovided via this C on nector.

SWITCHEST here is on e sw itch on the A D 98 31 evaluation b oard. T hissw itch is a dou ble throw , end stackab le sw itch. T his sw itchcan be used to control the FSE L E C T , PS E L 0 and PS E L 1inputs.

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Preliminary Technical Data AD7002 EVAL-AD9831EBSOFTWARE DESCRIPTIONInclud ed in the E V A L -A D 98 31 E B evaluation b oard package is a PC -com patible disk w hich con tains softw are for controlling theA D 983 1 u sing the p rinter port of a PC . T he d isk contains the executable program w hich runs u nd er W ind ow s and it is advisedthat the user cop y this file to the system hard disk to ob tain op tim um perform ance from the softw are.

PC ConfigurationT he executable program contains tw o m enu s. T he first m enu gives option s on the type o f P C being used. T he p rinter portneeds to be con figu red correctly for on e of the three different P C -typ es for interfacing to the A D 98 31 . C hoo se the requ iredprinter typ e from the m enu . T he P C printer port is no w con figu red for op eration w ith the A D 98 31 evaluation b oard.

Figure 2. Parallel Port Selection

Running the AD9831 SoftwareT he second m enu gives option s for run ning the A D 98 31 . A ll registers of the A D 98 31 can b e w ritten to using this softw are.T he M C L K frequen cy is set to 25 M H z by default in the program . H ow ever, the user has the capability of changing the M C L Kfrequ ency. W hen the m aster clock has a frequ ency other than 2 5 M H z, the user can chang e the value of the M C L K frequen cyin the program so that the softw are can correctly calcu late the d igital w ords correspon ding to the d ifferent ou tput frequencies.

T he F requen cy R egisters are w ritten to b y w riting in the required frequen cy in M H z to the P C . T he A D 983 1 softw are w illcalculate the correspon ding w ord w hich w ill be w ritten to the A D 98 31 an d d isplay the w ord in h ex on the screen. T he P haseR egisters are w ritten to b y w riting in the requ ired value in decim al to the P C . T he softw are w ill then con trol the load ing o f thisinform ation into the A D 983 1.

T o w rite to a P hase R egister, three transfers of data from the P C are needed since the P C uses 8-bit transfers. T he 1 6 b it w ordalon g w ith the ad dress of the d estination register is transferred from the P C to the A D 98 31 . T he sixteen b it w ord is split intotw o 8-bit w ords (the 8 M SB s and the 8 L SB s). T he first transfer of data involves transferring the 8 M SB s of the 1 6-bit w ord.W hen these 8 b its are being transferred, a pulse is also gen erated o n the L O A D pin so that the 8 bits of data are latched into U 2on the rising edge of L O A D .

D uring the secon d transfer, the 8 L SB s are transferred to U 3, a pu lse being gen erated o n the L A T C H pin so that these 8 b its arelatched into U 3.

T he third transfer involves transferring the ad dress of the d estination register (A 0, A 1 an d A 2). W hen the P C ou tputs theadd ress inform ation (w hich is available on D 0, D 1 and D 2 respectively), the P C also gen erates the WR pu lse. O n the risingedge of WR , the 1 6 b its of data are read from the 74 H C 57 4 latches and the address of the d estination register is read from the

data bus.B ecau se the F requency R egisters are 32 bits w ide, there w ill be six transfers from the P C w hen these registers are being w rittento. W riting the 16 L SB s to the F requ ency R egister invo lves transferring the destination register add ress (00 0 o r 010 ) and the 16bits of data. S im ilarly, the destination address for the 1 6 M SB s (00 1 or 01 1) and 1 6 b its of data need to be transferred w henw riting to the 16 M S B s of the F requ ency R egister.

T he logic inp uts F S E L E C T , P S E L 0 and P S E L 1 are no t controlled by the P C . T hese inp uts can be con trolled using the sw itchS W or, alternatively, these inputs can be con trolled u sing an external source via the B N C con nectors.

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EVAL-AD9831EBT he A D 983 1 softw are also contains a dem on stration procedure w hereby the A D 983 1 can b e m ade to step through a series ofou tput frequ encies. T he u ser on ly n eeds to load the start frequen cy, the stop frequen cy an d the step size and , the A D 98 31

softw are w ill program the A D 98 31 app ropriately so that a frequ ency sw eep w ill be p erform ed at the A D 98 31 ou tpu t.

Figure 3. Main Menu

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