Date

Advanced Materials and Process

for High Power Flip Chip

By Nokibul Islam, and YongHyuk Jeong

STATS ChipPAC Inc

Thermal Management Conference Denver, CO, August 3rd-4th, 2016

STATS ChipPAC Confidential

• Flip Chip Market Overview

• Flip Chip Construction and Process Flow

• Thermal Measurement Process

• TIM1 Selection Method

• Thermal Measurement Data

• Parametric Study

• Conclusion

Contents

2

STATS ChipPAC Confidential

Flip Chip Markets & Applications

3

Computing

Network/Communication Mobile

Consumer

Automotive

Application Processor, Baseband processor, PM,

RF, Audio Codec, PA, Sensors

Ethernet Switch, Network Storage (RAID, etc.)

Network Processor, WLAN, ASIC, PHY, DSP,

EPON/GPON, xDSL, Small Cell, Router SoC

DTV SoC, STB SoC, Tablet SoC, GPS SoC,

Home WiFi, Game Console GPU

GPU, CPU, Chipsets, Memory Buffer, LAN

controller

Infotainment SoC

STATS ChipPAC Confidential

Typical High Performance Flip Chip Package Attributes by Market Segment

Market Schematic Package attributes

Consumer fcBGA/-H, upto 45X45mm body, 6 to 10L substrate

Network fcBGA/-H upto 70X70mm body, 6 to 16L substrate

Computing fcBGA/-H up to 27X27mm body, 4 to 6L substrate

Automotive fcBGA /-H upto 25X25mm body size, 4 to 6L substrate

4

STATS ChipPAC Confidential

High Power Flip Chip Package Construction

Description Symbol Nominal

(um)

Typical Package Stack Up

Die Thickness a ~780 Bump Height b 55~60 Ball stand Off A1 ~500

Substrate thickness A2 ~1600 Adhesive A3 ~70 Lid Depth A4 835~840

Lid thickness A5 1000 Solder Ball Siz - 635

Total package height A 4010

A1

A2 A A3

A5

A4

b

a

Lid or heatspreader TIM (thermal interface material)

Si die Cu Col bumps Capacitors

Adhesive

Substrate

Solder ball

Typical schematic of a flip chip package

5

HS type Description Feature Pros & Cons

One Piece Hat

type

4 sides foot print High adhesion, Lower Warpage than flat type or 2FP or 4 CP, can be used for GND Lid

Two Pieces Stiffener + Spreader High cost w/ 2 pieces HS and 2 layer adhesive, Large body Coreless (Warpage imp by pre stf attach)

Flat type

Flat HS on FC die or Memory package

Available for No lid seal, maximize die size w/o lid seal, risk of lid shfit/roation (slip), Curable TIM use

2 Bar (2Foot

Print)

2 Foot Prints. Good for design with lots of passives

Rectangular die (Die size increase) or passives on 2sides

4 Corners Foot

Print

4 Corner lid seal, small form

Maximize die size, Curable TIM use by low adhesion strength w/ corner foot print

HS on substrate

for MPM

GPU+DDR, FC die on BGA side, HS on Sub. top side (Cross shape)

Enhanced thermal performance for FC MPM

Strip type for

FBGA

Flat type HS attach on Exposed die of fcFBGA-ED

Applicable for Strip type and Thin profile

4 Corner

High Performance Flip Chip Package with Heatspreader

6

FlipChip Package Typical Assembly Process Flow

Wafer Mount Reflow

SBM/Reflow/De-flux

3rd Inspection

Chip Attach

Laser grooving / Dicing Saw

2nd Inspection

Plasma Clean

ICOS and EVI

Packing

Laser Marking

Substrate Pre-bake

Flux Cleaning

Wafer IQA

UF Prebake

Die Preparation FOL EOL

Solder Paste Printing

O/S Test

Underfill for Chips

Heat Spreader Attach

Passive Mounting

AOI for Chip Caps

Adhesive/TIM Dispense

7

STATS ChipPAC Confidential

Large Package Std Lid Attach Process

• B Stage Snap Cure Process

• Snap Cure Methodology: – Force control method:

weight on every unit – Heating method:

• Machine Capability: – Package Size:

very large package – Snap Cure Force:

– Snap Cure Temperature:

• Criteria

– TIM Coverage: Meet criteria of 100% coverage

– TIM BLT : Control very thin BLT

– Adhesive coverage : Meet criteria of minimum ½ heat spreader foot width

– Lid Placement: Meet criteria

8

Large Package Std Lid Attach Process

TIM

BLT

(u

m)

10

50

70

90

110

Low Limit

Upper Limit

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

EA6900 SE4450

Process within Adhesiv e Material

EA6900

SE4450

Adhesive

Material

Std

De

v

0

5

10

15

20

25

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

EA6900 SE4450

Process within Adhesiv e Material

Variability Chart for TIM BLT

Adhesive 1 Adhesive 2

Ad

he

siv

e B

LT

(u

m)

80

100

120

140

160

180

200

220

240

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

EA6900 SE4450

Process within Adhesiv e Material

EA6900

SE4450

Adhesive

Material

Std

De

v

0

10

20

30

40

50

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

0.5

Kg

Cla

mp

2m

in

Sn

ap

Cu

re

3m

in

Sn

ap

Cu

re

EA6900 SE4450

Process within Adhesiv e Material

Variability Chart for Adhesive BLT

Adhesive 1 Adhesive 2

Left Center Right

BLT Comparison between snap cure and clamp method with 2 adhesives.

Significantly lower TIM1, and adhesive BLT achieved with snap cure over std clamp cure Lid attach process

Process typically use for large die/ large body fcBGA-H for uniform TIM BLT

Body size: 52.5X52.5mm

Die size: 17.4X19.5mm

5-2-5L substrate

1 mm thick Ni Plated Cu Lid

9

Items Image Application

Software Data Analysis & Control parameter

Computer controlled box of electronics

Power, Measurement & Analysis of changing temperature of Test Vehicle

Extension Box

Further powering channels for multiple die measurements such as stacked die packages, MCMs & LED assemblies

Chiller Calibration tool for Diode sensitivity based on changing threshold voltage by temperature

Thermal Measurement tool

Thermal Measurement Setup

Wind Tunnel for forced air Test Vehicle inside of Wind Tunnel 10

• Thermal chip(Resistor &

Diode connection) • Test vehicle on board

-. Thermal Sensitivity check: Center Diode

-. Thermal Heating: Used all resister for uniform heating

Thermal

sensor(Diode)

Thermal test vehicle

Thermal Measurement Process

Thermal Test Procedure for Theta JC per JEDEC 51-14

Parameter Data Check

(Diode & Resistance Check) Wiring

Thermal Sensitivity

Test

Theta jc measurement

without TIM2

Theta jc measurement

with TIM2 Data Analysis

Heat Spreader Tj

Tc

Cold Plate

Die

Board

TIM 1

TIM 2

Heat Flow

11

STATS ChipPAC Confidential

19.0

20.0

21.0

22.0

23.0

24.0

NA 4 layer 4 layer 4 layer 4 layer 4 layer 2 RDL 4 RDL

64LD 256LD 256LD 256LD 256LD 256LD 256LD 256LD

QFN PBGA_WB fcBGA_baredie fcBGA_overmold fcBGA-H_hat type fcBGA-H_flat type eWLB_2RDL eWLB_4RDL

Rth-JA (C/W)

Comparison of Thermal performance for various package type

QFN PBGA_WB fcBGA_baredie fcBGA_overmold fcBGA-H_hat type fcBGA-H_flat type eWLB_2RDL eWLB_4RDL

Substrate NA 4 layer 4 layer 4 layer 4 layer 4 layer 2 RDL 4 RDL

Junction temp 90.81 98.89 99.73 97.81 94.55 97.00 100.55 97.85

Case temp 90.51 98.68 99.71 97.73 91.34 95.78 99.88 97.21

Board Temp 77.58 77.92 80.52 77.81 78.48 78.09 75.66 76.26

Rth-JA 20.2 22.5 22.8 22.2 21.3 22.0 23.0 22.2

Package size: 9x9mmx0.85T, Power: 3.5W, Die: 4x4mm, Ambient: 20’C, 2s2p high-K JEDEC board

12

STATS ChipPAC Confidential

• High bulk conductivity and low thermal resistance to convey maximum amount of heat from die to ambient

• Thin bond line thickness (BLT)

• Good adhesion between the mating surfaces at all times (both assembly and accelerated reliability test conditions)

• Moderate stiffness and low CTE to mitigate warpage and stress due to CTE mismatch between the die and lid during package assembly and reliability test

• Good workability and shelf life

• No pump out or dry out issues during assembly or test conditions

TIM1 Selection Criteria

13

TIM1 Selection Criteria

TIM Characterization Metrology

#1. Required Thermal Performance

(from Customer)

- Device Power Consumption - Required Thermal Resistance (Theta Ja/Jc) - Package Construction

#2. Thermal Simulation (CZ) - Package Construction Review - BOMs Review (TIM, Adhesive, UF) - Lid Design Review (Thickness, Width, Cavity depth)

#3. TIM / Process Characterization

- Tentatively design decision for CZ - Measurement of Thermal Resistance - TIM Cure Reaction Analysis - Package/Process performance Review - Preliminary Reliability Test

#4 POR & Process Target Decision

#5 Process Optimization/Verification - Dispensing pattern/Volume, force ; TIM Coverage / TIM Thickness / TIM Void - Cure Profile ; TIM void / Adhesion / Warpage - Reliability Test Confirmation

14

15

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 1 2 3 4 5 6 7 8

Bulk Thermal Conductivity (W/mK)

Mea

sure

d T

her

mal

Res

ista

nce

(C

/W)

Simulated

Thermal

Performance

C2

F1 NC2

C4

C1

C3

Test Leg Bulk Thermal

Conductivity(W/mK)

Measured Thermal

Resistance (C/W)

C2 6.4 0.058

NC2 3.8 0.062

F1 4.0 0.198

C3 2.0 0.27

C1 1.97 0.14

C4 0.6 1.029

fcBGA-H, 40x40, 18.9 x 19.2 mm die

TIM1 Material Thermal Measurement

TIM1 Material Characterization

fcBGA-H Thermal Measurement Data

fcBGA-H mounted on thermal board

TIM1 BLT data

Thermal data measurement set-up

TIM A: Bulk K = 4.0 W/mK

TIM B: Bulk K = 6.5 W/mK

Ni plated Cu thick lid (1 mm)

TIM A performs much better than TIM B

•TIM degradation mainly happen in HTS, and TCB •TIM A performs much better than TIM B

TIM A TIM B

16

17

TIM1 Void Analysis

After HTS (1500C) Test

Thermal Measurement Test

#2 #8

CSAM Void Calculation

(Area in red) % of Void

Rth JC (C/W)

CSAM Void Calculation

(Area in red) % of Void

Rth JC (C/W)

EOL NA NA 3.1% 0.089 HTS EOL

NA NA 1.4% 0.088

HTS 500hrs

14.6% .11 HTS

500hrs 8.5% 0.122

HTS 1000hrs

22.0% 0.135 HTS

1000hrs 22.0% 0.131

Rth

-JC

%

of V

oid

• Value of Rth-JC has increased a lot with TIM void increased HTS test due to dry up of TIM

• Rth-JC value of TC & THB has not much correlation with TIM Void coverage

Thermal Measurement Test

Rth-JC vs TIM1 Void after

Accelerated Reliability Tests

18

Package fcBGA-MP , 35 x 35mm & 1.0mm P

Device FC Die: 12.3 x 12.7mm

Substrate 8L( 2/4/2 ) Build-up

Memory 12mm size Pb-free DDR

Si - spacer

Leg 1

Cu - spacer

Leg 2

Heat Sink

Leg 3

Leg 3 has the best thermal performance due to heatsink attached package

High Power SiP Thermal Management (w/ and w/o Heatsink)

Leg Thermal

Medium Adhesive

1 Si - space A

2 Cu - space A

3 Cu - Heat sink A

Ref Si - space B

Model

Power

(GPU/

DDR)

External

Sink

@0.51m/s

Air Flow

(m/s)

GPU

Temp.

(C)

Leg 1 16W/ 0.5W

NA 0.0 289.10

0.51 270.70

2.8(C/W) 0.51 111.15

Leg 2

16W/ 0.5W

NA 0.0 288.52

0.51 270.13

2.8(C/W) 0.51 110.92

Leg 3 16W/ 0.5W

NA 0.0 227.11

0.51 204.19

2.8(C/W) 0.51 90.17

Ref. 16W/ 0.5W

NA 0.0 289.20

2.8(C/W) 0.51 115.50

19

Package fcBGA-MP , 31X31mm body size

Device FC die: 8.0x8.0mm

Substrate 6L( 2/2/2 ) Build-up

HSpreader 0.25mm thk

Top HSpreader

Leg 1 Leg 2

Heat Sink

Leg 3

Model

TIM

Conduct

ivity

No. of

PCB via

under

die

GPU

Temp.

(C)

DDR

Temp.

(C)

Leg 1 None None 140.57 92.73

Leg 2

2.8

0 146.02 119.78

25 140.43 118.62

Leg 3 2.8 0 115.72 109.04

Leg 4 50.6 49 137.55 117.85

Die bottom TIM btw die & PCB

Leg 4

Solder TIM

Assumptions

Ambient = 70C

Airflow = 0.0m/s

GPU Power = 5.0W

DDR Power = 0.50W

HSpreader Adhesive Thickness = 0.05mm

High Power SiP Thermal Management (w/ and w/o Heatsink)

Heatsink effect (leg 3) is much more than high conductive TIM1 (leg 4)

20

Theta JA

8.96

9.03

8.95

9.02

8.90

8.92

8.94

8.96

8.98

9.00

9.02

9.04

NC1-4mil BLT NC1-6mil BLT C1-4mil BLT C1-6mil BLT

• Package : 35x35mm, 1 piece lid

• Die Size : 10x10mm

• PCB : 3-2-3 8L BU/ 1.2mm

• Lid Thickness : 0.6mm

TIM1 and BLT

• Lid Thickness : 0.5mm

• TIM C1 Curable : 1.97W/mK

• TIM NC1 Non-curable : 2.3W/mK

• Better thermal performance w/ thinner TIM1 BLT

TIM1 and BLT Effect

21

• TIM C1 Curable : 1.97W/mK

• TIM NC2 Non-curable : 3.8W/mK

• Contact Resistance : 0.07cm2-c/W

TIM1 Material and Coverage

100% 90% 80%0.0

0.1

0.2

0.3

0.4

0.5

BLT

T

he

rma

l R

es

ista

nc

e (

c/w

)

TIM Coveragre

30um

100% 90% 80% 70% 60% 50% 0.0

0.1

0.2

0.3

0.4

0.5

BLT

Therm

al Resi

stance (

c/w

)

TIM Coverage

30um 40um 50um 60um 70um

TIM C1 TIM NC2

• Package : 35x35mm, 1 piece lid

• Die Size : 18x9mm

• PCB : 3-2-3 8L BU/ 1.2mm

• Lid Thickness : 1.0mm

• Better thermal performance w/ higher TIM coverage and Lower BLT

• Higher thermal resistance with lower TIM coverage

TIM1 Coverage & BLT Effect

22

Lid plating (Ni/Au)

Die Back-side Metallization

Solder TIM

Die

Lid

Challenges

Factor Assessment

Solder

Wettability

• Optimize the soldering process (Solder

Paste vs Solder Preforms, conventional

reflow vs Bake oven)

• Flux material selection

Delamination

• Die Back-side Metallization metallurgy &

Au thickness control (Ti/Ni/Au, Ti/Au)

• Solder material selection (Pure In, In alloy)

Reliability

• Flux material & reflow profile (IMC)

• Mechanical design (Lid dimension, die size,

stiffen area)

• Die Backside Metallization : Ti/Ni/Au or

Ti/Ni

• H/S Finish : Ni/Au

• Solder : Indium (Tm 150’C, TC 86W/mK)

• Expectation : High Thermal Performance

(>100W power devices)

High Performance TIM for Next Gen Package

Solder TIM and Silicon Backside Metallization

23

24

Parametric Study of Flip-chip

• Package size & H/S

• 9x9mm, 10x10mm, 11x11mm fcBGA fcBGA-H

Case# PKG size Heat

spreader Junction Temp Case Temp Board Temp

1 9x9x0.85mm

No H/S 99.7 99.7 80.5

2 with H/S 94.5 91.3 78.5

3 10x10x0.85mm

No H/S 99.0 99.0 76.8

4 with H/S 94.2 90.9 75.2

5 11x11x0.85mm

No H/S 98.4 98.4 73.7

6 with H/S 93.7 90.4 72.3

All parameter are same except for substrate & heat spreader size

Power: 3.5W, Die: 4x4x0.2mm, Ambient: 20’C, 2s2p high-K JEDEC board

• Heat spreader improves ~ 6.5%

thermal performance

6.5% decreased

20.0

21.0

22.0

23.0

No H/S with H/S No H/S with H/S No H/S with H/S

9x9x0.85mm 10x10x0.85mm 11x11x0.85mm

Rth-JA Rth…

25

• Die Size

• 11x11x0.85mm Package

Case# Die size Junction Temp Case Temp Board Temp Rth-JA

1 4x4x0.2mm 98.4 98.4 73.7 22.4

2 5x5x0.2mm 94.9 94.9 73.8 21.4

3 6x6x0.2mm 92.6 92.6 74.1 20.7

4 7x7x0.2mm 90.9 90.9 74.2 20.3

5 8x8x0.2mm 89.4 89.4 74.3 19.8

Power: 3.5W, Ambient: 20’C, 2s2p high-K JEDEC board

All parameter are same except for die size

Parametric Study of Flip-chip Die Size

18.0

19.0

20.0

21.0

22.0

23.0

4x4x0.2mm 5x5x0.2mm 6x6x0.2mm 7x7x0.2mm 8x8x0.2mm

Rth-JA Rth-JA

• Larger die sizes improve thermal

performance

26

• fcBGA-H

• Parametric study with various factors

fcBGA-H 40x40mm PKG, Power: 25W, 0.65mmBall, 1mm pitch, 1521LD, H/S: 39.4x39.4mm

Parametric study- TIM1 Voids and Locations

Die size Die thickness TIM material BLT thickness TIM coverage TIM void location

A A A A 100% No void

B B B B 90% Center

C C C C 70% Corner

• TIM Void location

Void

Die

TIM void at the center of

die

TIM void at the corner of

die

95%

0.2%

• fcBGA-H

• Parametric study with various factors

fcBGA-H 40x40mm PKG, Power: 25W, 0.65mmBall, 1mm pitch, 1521LD, H/S: 39.4x39.4mm

Parametric study- H/S Thickness

Die size Die thickness TIM material BLT thickness TIM coverage Heat spreader thickness

A A A A 100% 1 mm

B B B B 90% 0.5 mm

C C C C 70% 0.3 mm

• Heat spreader thickness

3% 5%

27

STATS ChipPAC Confidential

• Through comprehensive study and investigation design, process, and BOM (bill of materials) selection has been made for high power flip chip package

• Selection criteria for TIM1 has been verified and established for high power packages

• Extensive thermal data collected on various packages and data measurement will continue as technology evolve over time

• More work needs to be done for even higher power (>150W to 200W) high speed flip chip package

Conclusion

28