B CNG N THI THIT K TNG HP H THNG S C P NCu hi 1 : Trong lnh assign x = y, tn hiu x cn khai bo kiu d liu noA : Reg. B : Wire. C : Wire hoc reg. D : Khng cn Cu hi 2 : Phn mm tng hp chc chn khng tng hp c vng lp for trong iu kin :A : For l vng lp tnh v khng c iu khin thi gian bn trong vng lp.B : For l vng lp ng v khng c iu khin thi gian bn trong vng lp.C : For l vng lp tnh v c iu khin thi gian bn trong vng lp.D : For l vng lp ng v c iu khin thi gian bn trong vng lp.Cu hi 3 : Trong cc khai bo define, localparam v parameter, cc nhm no c cng 1 cchs dng :A : Define v localparam.B : Define v parameter.C : Define, localparam v parameter.D : Localparam v parameter.Cu hi 4 : nh dng mc nh ca mt con s trong VerilogA : H 8. B : Nh phn. C : H 16. D : Thp phn.Cu hi 5 : Ngn ng HDL ni chung v Verilog ni ring hot ngA : Tun t.B : Song song.C : Khng phng n no. D : C 2 phng n.Cu hi 6 : Khi so snh khi lnh begin. . . end v fork. . . join, phng n no ng :A : C hai u cng thc hin ni tip cc lnh.B : C hai cng thc hin song song cc lnh.C : begin. . . end ni tip, fork. . . join song song.D : begin. . . end song song, fork. . . join ni tipCu hi 7 : Cho chng trnh sau :integer a, b, c, d ;initial begina = 0 ; b = 1 ; c = 2 ; d = 0 ;#1 a = 1 ; #3 b = 2 ;#2 c = b ;endalways @(a, b, c)d Ti u.B : Chc nng -> Lut thit k -> Ti u.C : Chc nng -> Ti u -> Lut thit k.D : Khng phng n no ngKhi so snh define v parameter, m t no di y ng :A : Khng c s khc bit gia hai khai bo ny.B : Dng khai bo hng s v parameter dng cc b trong module, define dng ton cc bnngoi module.C : Dng khai bo hng s v c th s dng cc b trong module.D : Dng khai bo hng s v c th s dng ti v tr bt k trong chng trnh Verilogim bt u v kt thc vng lp c nh ngha bi A : Du ngoc n ().B : begin . . . end.C : Khng cu no ng.D : C haiS khc nhau gia $stop v $finish trong m phng :A : $stop tm dng chng trnh,$finish dng hon ton chng trnhB : $stop dng hon ton chng trnh, $finish tm dng chng trnhC : $stop dng hon ton chng trnh, $finish dng hon ton chng trnhD : Khng khc nhauTh t u tin thc hin cc php ton nh sau :A : Du m/ dng -> php tnh s hc -> php iu kin -> php dch -> php logic.B : Du m/ dng -> php tnh s hc -> php dch -> php logic -> php iu kin.C : Du m/ dng -> php dch -> php logic -> php tnh s hc -> php iu kin.D : Du m/ dng -> php tnh s hc -> php logic -> php dch -> php iu kin.Phn mm tng hp c kh nng tng hp c vng lp for trong iu kin (lachn nhiu p n) :A : For l vng lp tnh v c iu khin thi gian bn trong vng lp.B : For l vng lp ng v khng c iu khin thi gian bn trong vng lp.C : For l vng lp tnh v khng c iu khin thi gian bn trong vng lp.D : For l vng lp ng v c iu khin thi gian bn trong vng lp.on code sau y cho bit tn s m phng l :timescale 500ps / 20ps. . . . . . ..always#4 cl k > 1A : Ton t tng tc tng bit (bitwise).B : Ton t quan h (Relational).C : Ton t logic.D : Ton t dch (shift)on code sau m t m hnh no ca mch :1 module majority (Y, X1, X2, X3) ;2 output major ;3 input X1, X2, X3 ;4 wire N1, N2, N3;5 and A0 (N1, X1, X2),6 A1 (N2, X2, X3),7 A2 (N3, X3, X1);8 or Or0(Y, N1, N2, N3)A : M hnh cu trc.B : M hnh dng d liu.C : M hnh hnh vi.D : Khng m hnh no c.Created by Hong Minh Sn K54