Embed Size (px)
Citation preview
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 1/26
Sensor Network Pro ramminClass 2, Micaz
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 2/26
Review
Research methodology
HW system
Operation
SW s stem Machine language, Assembly language
C-language Data presentation
Compiling, linking, loading
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 3/26
Outline
Background Micaz overview
Cc2420
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 4/26
Protocol Stack
OSI (open systems interconnection) basicmodel
Late 1970s, by ISO
7 layers Concepts
Do not think lower layer
IEEE 802.3 (Ethernet), IEEE 802.11 (WLAN), IEEE 802.2token lin …
Practically
IP (network layer, layer 3) is connection point
5~7 layers are merged
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 5/26
Seven Layers
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 6/26
MAC
Data link layer Control point-to-point communication
Usually called as a MAC layer
LLC (Logical Link Control) Multiplexing/demultiplexing
ow con ro
MAC (Media Access Control), , ,
Power control
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 7/26
Sensor Network MAC
Huge number of MACs , , , , , , ….
Application specific
One sensing application a network
IEEE 802.15.4
Cover most of applications by changing parameters Low cost
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 8/26
IEEE 802.15.4 Platforms
Chipcon Ember Freescale CompXs xBow
Product CC2420DB EM2420DB SARD Glaramara MicaZ
Small/Eval Small Board
BoardSmall Board
BoardSmall Board
MCU Atmega128/ Atmega128
MC9S08GT PIC18LF452PT Atmega128
Prgm port JTAG/serial JTAG BDM, RS-232 ICD JTAG, RS-232
Transceiver /CC2430
EM2420/EM250 /MC12193
CS1540 CC2420
RemoteX
OX X
O
Power Adaptor Adaptor/POE Adaptor Adaptor Adaptor
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 9/26
Micaz
From Mica2
CrossBow Inc.
Most popular
tmega , cc z
MCU: Atmega128L
3 LEDs, 2 USARTs (51 pin connector)
JTAG $125
Micaz schematic is not opened
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 10/26
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 11/26
Mica2: CC1000 Part
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 12/26
CC2420DB: CC2420 Part
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 13/26
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 14/26
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 15/26
ATmega128 (1)
8Bit AVR Microcontroller + 128KB Flash memory AVR core
RISC/Harvard
,
Up to 16 MIPS at 16MHz (8MHz for ATmega128L)
On-chi 2-c cle multi lier
32*8 general purpose Regs, peripheral control Regs
Memory 128KB Flash; 10000 times rewritable
4KB EEPROM; 10000 times rewritable
4KB interna RAM
64KB external memory space
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 16/26
ATmega128 (2)
JTAG interface Peripherals
Two 8bit timer/counters
6 PWM channels
8 channel 10 bit ADC
Two USARTs
SPI interface Watchdog timer
Six sleep modes: idle, ADC noise reduction, power-save,- ,
Around $10 each
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 17/26
ATmega128 Pinout
64 Pins Shared pins
Use latches and Mux
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 18/26
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 19/26
AVR Core
Single Cycle Instructions:= .
Harvard Se arate 8bit data bus
16bit instruction Registers
arge reg ster e .
Every register an accumulator.
3 index re ister airs
Register & IO are mapped inSRAM space.
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 20/26
Memory Organization
Program memory n y o program
64K*16
Data 64K*8
Internal registers aremapped here
reg s ers aremapped here
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 21/26
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 22/26
UART (1)
Universal Asynchronous Receiver-Transmitter Usually used with RS-232, RS-422 and RS-485
Parallel-to-serial converter with extra features. s t reg ster: oa e n para e , an t en eac t s sequent a y
shifted out of the device on each pulse of the serial clock.
How to receive?
Difficulties arise in detecting boundaries between bits.
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 23/26
UART (2)
Do not share a common clock Each device has its own, local clock.
The devices must operate at exactly the samerequency.
Standard speeds are 110, 300, 1200, 2400, 4800, 9600,19200 28800 38400 57600 76800 115200 230400 460800, 921600, 1382400, 1843200 and 2764800 bit/s
Logic (within the UART) is required to detect thephase of the transmitted data and phase lock thereceiver’s clock to this.
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 24/26
UART(3)
Transmission format op : one or wo s op
Parity: No (or odd/even parity
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 25/26
RS-232
RS-232c, EIA standard, 1969
Originally intended for connecting computer equipment(computers or terminals, referred to as DTE) to communicationequipment (DCE).
the same protocol
RS232 Voltages are +5..+25V for a logic 0, and -5V..-25V for alogic 1 (Reverse polarity)
3 wires or 5 wires
8/13/2019 C2_MicaZ_1
http://slidepdf.com/reader/full/c2micaz1 26/26
RS-232 Implementation
Programming board
Mib510
