By :python

2007/01

Standard Verification Rule ManualCalibre LVS Option

OPTION目錄

一般設定LVS CHECK PORT NAMES {YES | NO}LVS RECOGNIZE GATE {ALL | SIMPLE | NONE}LVS REDUCE SPLIT GATES {YES/NO}LVS ABORT ON SUPPLY ERROR {YES | NO}LVS ALL CAPACITOR PINS SWAPPABLE {NO | YES}LVS CHECK PORT NAMES {NO | YES}VIRTUAL CONNECT COLON {NO|YES}LVS BOXLVS COMPARE CASE {NO / YES}LAYOUT DEPTH { ALL | PRIMARY}PORT DEPTH {ALL | PRIMARY |number}TEXT DEPTH {ALL | PRIMARY |number }LVS ABORT ON SOFTCHK {NO |YES}LVS REPORT OPTION V S A AV B C D F G P R RALVS SOFT SUBSTRATE PINS {NO | YES}LVS Filter Unused Option { B D E O }LVS Filter Unused Option {AB RC RE RG}LVS Filter Unused Bipolar { YES | NO }LVS Globals Are Ports {NO | YES}TEXT PRINT MAXIMUM {ALL | NUMBER}LVS Property Resolution Maximum {number | All}LVS Softchk Pwell_all contactTrace Property C1 C2 C3 trace_val

OPTION {紅色是建議值，底線是預設值}

precision 1000 //預設精密(度)為1000resolution 10 // layout grid size 0.01um(10/1000) ，如果沒有設這行，預設值是database unit。LAYOUT PATH "***" // layout database路徑LAYOUT PRIMARY "PA6368A1" // layout database top cellSOURCE PRIMARY "PA6368_TOP" // netlist 路徑SOURCE PATH "**" //與layout database top cell相對等的netlist top cellUNIT LENGTH u // 定義尺寸,距離的單位 u=1e-6 m ，預設值為u (u、mil、mm、cm、inch、m)UNIT CAPACITANCE fF // 定義電容的單位 f=1e-15，F=法拉，預設值為(aF、fF、pF、nF、uF、mF、F、kF、megF、gF、tF)UNIT RESISTANCE OHM //定義電阻的單位，預設值為ohm=1 (ohm、aohm、fohm、pohm、nohm、uohm、mohm、kohm、megohm、gohm、tohm)layout system gdsii // layout database 儲存格式source system spice // netlsit 格式erc results database “erc.db” ascii //記錄結果的資料以ascii碼儲存LVS REPORT “lvs.rep“ //lvs report 的檔名

OPTION {紅色是建議值，底線是預設值}

MASK SVDB DIRECTORY “svdb” QUERY XRC // lvs report格式如此才可以使用RVE看lvs report ；XRC for rc extraction LVS POWER NAME "VGH" "VCC" "VDDD" "VDDA" //定義layout power nameLVS GROUND NAME "VGL" "VSSD" "VSS" "VSSA" //定義layout ground nameLVS SPICE PREFER PINS NO //決定subcircuit的pin name 是否凌駕於globalLVS REDUCE PARALLEL BIPOLAR YES //把所有並聯的bipolar加在一起

LVS REPORT MAXIMUM ALL // show出所有lvs error report

XRC for rc extraction

OPTION {紅色是建議值，底線是預設值}

LVS REDUCE PARALLEL MOS YES //把所有並聯的mos加在一起LVS REDUCE PARALLEL DIODES YES //把所有並聯的diodes加在一起LVS REDUCE PARALLEL CAPACITORS YES //把所有並聯的電容加在一起LVS REDUCE PARALLEL RESISTORS YES //把所有並聯的電阻加在一起LVS REDUCE SERIES RESISTORS YES //把所有串聯的電阻加在一起LVS REDUCE SERIES CAPACITORS YES //把所有串聯的電容加在一起LVS SIGNATURE MAXIMUM ALL // 當layout架構相似,擴展比較net的節點數, 去看相鄰的元件大小, 來決定某個元件是位source的何處。

OPTION {紅色是建議值，底線是預設值}

LVS CHECK PORT NAMES YES // LVS是否要檢查 port nameLVS CHECK PORT NAMES YES // LVS是否要檢查 port nameLVS IGNORE PORTS NO //做LVS的比較時,是否要忽略掉layout 跟source 的 pin name

LVS RECOGNIZE GATE 決定是否要從電晶體辨認出邏輯閘

LVS RECOGNIZE GATE

ALL Specifies that all gates are recognized. 全部分辨SIMPLE Specifies that simple gates are recognized.

分辨簡單的邏輯定義NONE Specifies that no gates are recognized.

不分辨邏輯閘 (類比電路使用)

LVS REDUCE SPLIT GATESYES LVS to reduce split gates. 允許gate可以分開

NO LVS not to reduce split gates. 不允許gate分開

LVS ABORT ON SUPPLY ERROR {YES | NO}

NODefine 為No 若在執行lvs時即使有short ,也會等整個驗證完畢後才會跳出

YES

在執行lvs時一有short 馬上停止後續驗證並寫report告知哪些電位short(lvs.report.short)

LVS ALL CAPACITOR PINS SWAPPABLE {NO | YES}

YES 宣告所有電容器的兩pin腳可互換

NO 宣告所有電容器的兩pin腳不能夠互換

LVS CHECK PORT NAMES {NO | YES}

若在執行lvs時紀錄Layout 與netlist的port name有沒有相同可在lvs.rep中可看到結果

NO

YES

為NO時，當netlist與layout不同名稱時lvs抓不出名稱錯誤

VIRTUAL CONNECTVIRTUAL CONNECT COLON {NO|YES}

VIRTUAL CONNECT NAME PIN_NAME當上面表格Incorrect 的選項，在這個功能開啟下會認為Correct。當有二個以上同名PIN_NAME時會認為接在一起。

Correct Pin_NAME1 Pin_NAME2 Pin_NAME3 Note

X VDDA VDDA: 二個都是VDDA，但是是各自獨立的VDDA

V VCI: VCI: 均視為VCI

V VDDA: VDDA:EFG VDDA:ABC 均視為VDDA

X VCI: VCI VCI:ABC VCI:和VCI:ABC視為同一個VCI，但是和另一個VCI是不同net

V VCI: VCI VCI:ABC If pin_name3&pin_name2打在同一net上，會視為接在VCI

LVS BOX

LVS BOX LAYOUT CELL_NAMELVS BOX SOURCE CELL_NAME當二個人以以上合作時，在TOP CELL需要MAPPING 另一個還未完成的CELL時，可讓command file 設定為這個CELL已經OK，忽略這

個CELL的錯誤。

LVS COMPARE CASE NO / YES

LVS COMPARE CASE: 設定是否開啓大小寫的比較當設為YES時： SOURCE CASE & LAYOUT

CASE才起作用

SOURCE CASE NO / YES :是否區分source netlist (device & pin name)的大小寫

LAYOUT CASE NO / YES :是否區分layout netlist (device & pin name)的大小寫

LAYOUT CASE YES

Layout device type是由lvs command file決定的

決定device的layer都改為大寫后，lvs correct

LAYOUT DEPTH ALL | PRIMARY

.when option set ALL, shapes are read from the top-level cell to the bottom of the hierarchy.（可識別底層到頂層的所有圖）

.when option set PRIMARY, shapes are read from the top-level cellonly.（只識別top層的圖）

當LAYOUT DEPTH 設為PRIMARY時

NOT COMPAREDNothing in layout

Lvs.rep

PORT DEPTH ALL | PRIMARY |number

.when option set PRIMARY, the tool to use free-standing port objects from only the top-level cell. （只識別top層cell的ports). when option set ALL, the tool to use free-standing port objects from throughout the hierarchy. （識別所有層cell的ports)when option set number, from number levels below the top-level cell. Specifying zero is equivalent to PRIMARY. （可識別所設定的層到top層的所有ports,若number設為0時，即top層）

Used only in Calibre LVS/LVS-H

PORT DEPTH ALL时,lvs有错

Lvs. rep

Missing port

TEXT DEPTH ALL | PRIMARY |number

.when option set PRIMARY, only text objects from the top-level cell are selected. （只識別top層cell的texts)

.when option set ALL, text objects from throughout the hierarchy are used as top-level text. （識別所有層cell的texts)

.when option set number, text objects from number levels below the top-level cell. Specifying zero is equivalent to PRIMARY. （可識別所設定的層到top層的所有texts,若number設為0時，即top層）

TEXT DEPTH ALL 时,lvs Correct

Naming or swap-override errors

Lvs.rep如下:

Lvs. rep

LVS ABORT ON SOFTCHK NO |YES

.when option set NO, tool not to abort processing when a violation is detected. （ tool在發現有錯時還繼續執行直到執行完畢）

.when option set YES, tool to abort processing when a violation is detected. （tool在發現任何錯誤（LVS SOFTCHK & SCONNECT錯誤)時就立即停止執行）

遇到SCONNECT錯誤時就停止執行

LVS REPORT OPTION V.在 Virtual Connect Colon YES & Virtual Connect Name ?情况下

Virtual connections are reported as notes in the Extraction report and Warnings section of the LVS report.

LAYOUT出同樣的port ”VDDA” ,but實際未

用MT連線

LVS REPORT OPTION S.that enables the detailed reporting of Sconnect conflicts in the

transcript and the LVS Report.（由SCONNECT 引起的 short)

沒有加S的情況

A

B

A:MT2 VIA1 MT1 DC OD p+ HVPW

B:MT2 VIA1 MT1 DC OD P+ HVPW

LVS REPORT OPTION (A AV)A 確認是否 在 DETAIL INSTANCE CONNECTION中詳細的 REPORT出CONECTION的詳細錯誤（除了SHORT和OPEN）包括兩個部分, Incorrect Devices On This Net 和 correct Devices On This Net 如下圖。

AV 和A的REPORT基本相同，只有在POWER GND錯誤的時候不顯示correct Devices On This Net 圖中流程就是 從不加A到加A，再到加AV的情況。

LVS REPORT OPTION (B C D)

B 確認是否 在 DETAIL INSTANCE CONNECTION中詳細的REPORT出SHORT 和OPEN的錯誤。

C和 D 分別確認Missing Net NOT Similar Net Missing Instance Missing Gate 的詳細訊息的 REPORT在 detailed instance connections 中顯示。B C D 在RULE FILE中不定義就默認的詳細的形式。

LVS REPORT OPTION ( B C D)

如圖所示：

右邊就是詳細的

REPORT形式下面就是簡略的

REPORT形式

Net 8(800,500) DOG---------------- ----------------** unmatched connection * * X1/M5:D53(530,500):D * * unmatched connection

LVS REPORT OPTION (F)

F 主要用來確定是否顯示 unbalanced smashed MOSFET summary warning ,(如W=10,M=1可lay成W=5 ,M=2); 同時respective warnings 會顯示在Information and Warnings section 默認是顯示,不加F

不同之處

LVS REPORT OPTION ( G )G 主要用來確定是否顯示 detailed instance connections in Property Error discrepancies.默認是不顯示詳細的信息，即右下圖所示。

LVS REPORT OPTION ( P )

P An optional argument that disables the reporting of “Direct connections between different ports” warnings in the connectivity extractor.主要是確定是否在REPORT中顯示WARNING ：

“Direct connections between differentports” 即不同PORT 的鏈接錯誤。

不同之處

LVS REPORT OPTION ( P )此圖就是上一頁的LAYOUT中的情況。

LVS REPORT OPTION ( R RA )R An optional argument that disables

reporting of ambiguity resolution points in LVS when the overall comparison result is CORRECT. This option controls reporting of ambiguity resolution points in the Information and Warnings section of the LVS report as well as reporting of ambiguity resolution status messages in the Overall Comparison Results and Cell Comparison Results sections of the LVS report. When the overall comparison result is other than CORRECT, ambiguity resolution points are reported as usual, regardless of this option.

主要用來確認是否在overall comparison result is CORRECT的 時候 顯示ambiguity resolution points的錯誤。當INCORRECT的 時候OPTION 無效，將顯示ambiguity resolution points 。同時在INFORMATION AND WARNINGS 中也有同樣的信息。如下一頁的 圖所示：

不同之處

LVS SOFT SUBSTRATE PINS {NO | YES}

LVS SOFT SUBSTRATE PINS {NO | YES}YES indicates that substrate and bulk pins should be treated with less importance in circuit comparison.

如果選擇了YES，那麼substrate和bulk的pins將不會視為在電路中有作用。

NO indicates that substrate and bulk pins should be treated like any other pins.

如果選擇NO，那麼substrate和bulk的pins將會視為在電路中有作用.

LVS Filter Unused Option { B D E O }

B Filters MOS devices if the following conditions are both satisfied:(a) the gate is floating or has no path to any pad, and(b) either the source or drain is floating.過濾同時符合下面兩組條件的MOS：

（a）Gate是floating，或者沒有路徑連接到任何PAD，而且（b) MOS的source或者drain有一端是floating的

D Filters MOS devices if the gate is floating, either source or drain have a path to power, and neither source nor drain have paths tonon-power pads.過濾符合下面條件的MOS：

（a）Gate是floating，或者沒有路徑連接到任何PAD，而且（b) MOS的source或者drain有一端是連接到power，另外一端連接到信號線

LVS Filter Unused Option { B D E O }

LVS Filter Unused Option { B D E O }

E Filters MOS devices if the gate is floating, either source or drain have a path to ground, and neither source nor drain have paths to non-ground pads.

過濾符合下面條件的MOS：（a）Gate是floating，或者沒有路徑連接到任何PAD，而且（b) MOS的source或者drain有一端是連接到power，另外一端連接

到信號線

O Repeats all unused device filtering until no more devices can be filtered. Also repeats series and parallel reduction of capacitor, resistor, diode, and MOS devices, split gate reduction, and semi-series MOS reduction.不斷過濾，直至沒有符合參數的device。

LVS Filter Unused { B D E O }

power

Not powerD

B

ground

Not groundE

O 重復過濾沒有用到的符合參數的 電容，電阻，DIODE，以及gate端沒有連接的MOS。

Gate & Source Floating

Or

Gate & Drain Floating

Gate Floating

And

S 或者D有一端接Power

Gate Floating

And

S 或者D有一端接Gnd

LVS Filter Unused Option {AB RC RE RG}

LVS Filter Unused Option {AB RC RE RG}

AB Filters MOS devices with source, drain, and gate pins tied together.

過濾掉Gate，Source，Drain都聯接在一起的MOS

RC Filters resistors with POS and NEG pins tied together.

過濾掉兩端連接在一起的電阻

RE Filters capacitors with POS and NEG pins tied together.

過濾掉兩端連接在一起的電容

RF Filters diodes with POS or NEG pin floating.

過濾掉兩端Floating的Diode

RG Filters diodes with POS and NEG pins tied together.

過濾掉兩端連接在一起的Diode

LVS Filter Unused Option {AB RC RE RG}

AB

RC

RFRG

RE

LVS Filter Unused Option Example

RFRG

RC

ABE

B D

符合參数的

layout其中

B,D,E,AB,R

C,RG,RF都

是有進一步

參數說明的。

LVS Filter Unused Option Example

圖左邊，紅色區域為lvs commandfile中屏蔽掉的參數。

圖右邊，lvs驗證中提示7處沒有match

LVS Filter Unused Option Example

LVS Filter Unused Option Example

D

E

參數D,E的device過濾不掉，不知道為什么？其他的都過濾掉了！

LVS Filter Unused Bipolar { YES | NO }

LVS Filter Unused Bipolar { YES | NO }NO 不過濾沒有用到的 Bipolar

YES 過濾沒有用到的 Bipolar

LVS Filter Unused Bipolar Option Example

LVS Filter Unused Bipolar Option Example

Lvs Globals Are Ports {NO | YES}

LVS GLOBALS ARE PORTS {NO | YES}

YES 將NETLIST 所宣告的*.GLOBAL 視為出PORT。

NO不將 NETLIST 所宣告的*.GLOBAL 視為出PORT 。

Lvs Globals Are Ports Option Example

Lvs Globals Are Ports Option Example

TEXT PRINT MAXIMUM {ALL | NUMBER}

TEXT PRINT MAXIMUM { ALL | NUMBER }

ALL 將top cell中的所有text對象和port寫入到report中

NUMBER 將top cell中的number個text對象和port寫入到report中

Lvs Property Resolution Maximum Option

Lvs Property Resolution Maximum {number | All}Number 如果電路中包含的不確定元件個數大于number值，LVS將自動任意匹配他們。

ALL LVS不限制不確定元件個數

Lvs Softchk Pwell_all contact

Lvs Softchk Pwell_all contact

Reports regions on a pwell layer that connect to more than one node.

檢查 pwell是否都聯接在一起

Trace Property C1 C2 C3 trace_val

Trace Property C1 C2 C3 trace_val

Trace Property C1 C2 C3 trace_val

將要Trace的Device

格式：A（B）

A：Device種類

B：Device的類型

eg.

R(NI) NI 型的電阻

R(LR) LR型的電阻

Netlist中的device的屬性

eg..SUBCKT TOP

C01 A1 B1 C=100C02 A2 B2 C=100

.ENDS

Layout中device的屬性

eg..SUBCKT TOP

C01 A1 B1 C=101C02 A2 B2 C=105

.ENDS

允許的誤差：數值為百分比

eg.

2

Trace Property C1 C2 C3 trace_val

將要Trace的Device類型：

M MOS transistorC CapacitorR ResistorD Diode Q Bipolar transistor

將要Trace的Device屬性：

W MOS width C CapacitanceL MOS lengthA Diode areaM Multiplier factorP Diode perimeterR Resistance

Trace Property C1 C2 C3 trace_val Example

1168

Trace Property C1 C2 C3trace_val Example

1168.29

Trace Property C1 C2 C3trace_val Example

1168.29

OPTION目錄OPTION {紅色是建議值，底線是預設值}OPTION {紅色是建議值，底線是預設值}XRC for rc extractionOPTION {紅色是建議值，底線是預設值}OPTION {紅色是建議值，底線是預設值}LVS RECOGNIZE GATE 決定是否要從電晶體辨認出邏輯閘VIRTUAL CONNECTLVS BOXLVS COMPARE CASE NO / YESLAYOUT CASE YESLAYOUT DEPTH ALL | PRIMARY�當LAYOUT DEPTH 設為PRIMARY時PORT DEPTH ALL | PRIMARY |numberPORT DEPTH ALL时,lvs有错TEXT DEPTH ALL | PRIMARY |numberTEXT DEPTH ALL 时,lvs CorrectLvs.rep如下:LVS ABORT ON SOFTCHK NO |YES LVS REPORT OPTION VLVS REPORT OPTION S LVS REPORT OPTION (A AV)LVS REPORT OPTION (B C D)LVS REPORT OPTION ( B C D)LVS REPORT OPTION (F)LVS REPORT OPTION ( G )LVS REPORT OPTION ( P )LVS REPORT OPTION ( P )LVS REPORT OPTION ( R RA )LVS SOFT SUBSTRATE PINS {NO | YES} LVS Filter Unused Option { B D E O }LVS Filter Unused Option { B D E O } LVS Filter Unused { B D E O } LVS Filter Unused Option {AB RC RE RG} LVS Filter Unused Option {AB RC RE RG}LVS Filter Unused Option ExampleLVS Filter Unused Option ExampleLVS Filter Unused Option ExampleLVS Filter Unused Option Example LVS Filter Unused Bipolar { YES | NO }LVS Filter Unused Bipolar Option ExampleLVS Filter Unused Bipolar Option Example Lvs Globals Are Ports {NO | YES}Lvs Globals Are Ports Option ExampleLvs Globals Are Ports Option ExampleTEXT PRINT MAXIMUM {ALL | NUMBER}Lvs Property Resolution Maximum Option Lvs Softchk Pwell_all contact� Trace Property C1 C2 C3 trace_val Trace Property C1 C2 C3 trace_valTrace Property C1 C2 C3 trace_val ExampleTrace Property C1 C2 C3 trace_val ExampleTrace Property C1 C2 C3 trace_val Example