Case Study: Implementing the MPEG-4 AS Profile on a

Multi-core System on Chip ArchitectureR92921054 楊峰偉R92942035 張哲瑜R92942081 陳 宸

Outline

• Introduction• Comparison of MPEG-4 SP & ASP• HiBRID-Soc Multi-core Architecture

– HiPAR-DSP– Macroblock processor– Stream processor

• Conclusion

Introduction

• Dedicated Architecture– Single-purpose– Lower flexibility higher performance

• Hybrid Architecture– Programmable CPU + dedicated hardware

accelerator– Higher flexibility lower performance

• FPGA or DSP– Fully programmable – Slow and only for evaluation

Comparison of MPEG-4 SP & ASP

HiBRID-SoC Multi-core Architecture

HiPAR-DSP• 16 parallel data paths steered by a single RISC controller

in SIMD style• Each data path consists of three VLIW controlled

arithmetical units: 16 bit MAC, 32bit ALU, and shift & round units.

• External connection can be provided via a modular DMA controller.

• A GNU based c/c++ complier is available.

Architecture: HiPAR-DSP

Architecture: Matrix Memory

Macroblock processor• Shift with round to 0 / ∞ unsigned, signed

– Transform, filter (QMC, deblocking)

• Average value with rounding control

– Sub-pel motion compensation

• Addition of absolute value

• Controlled Addition/Subtraction

– Dequantization

• Permute instruction

– Motion compensation, deblocking

• Branch on vector status registers

– Deblocking mode selection

Macroblock processor

Stream processor

• ApplicationAudio/Video stream generation and separatio

n

• Characteristics in MPEG encoding Multiplexing of different parts of bitstream Run-Length coding of DCT coefficients Variable length coding of coded DCT coeffici

ents (using Huffman table)

Software development environment

• Optimizing assemblers are available

• Data parallelism via SIMD or subword parallelism

• Instruction parallelism via VLIW

• Special instruction optimized for video and image processing algorithm

Simulation Result

Implementation Result

PSoC Architecture

Array of Analog PSoC Blocks

SRAMMemory

I/O Ports

Global I/OProgrammable Interconnect

Array of Digital PSoC Blocks

Analog InputMuxing

DBA00

ACA00

DBA03

DBA02

DBA01

DCA04

DCA07

DCA06

DCA05

Analog OutputDrivers

P1

P0

ComparatorOutputs

Clocks toAnalog

P3

P2

P4

P5

ASA10

ASB20

ACA01

ASB11

ASA21

ACA02

ASA12

ASB22

ACA03

ASB13

ASA23

Internal System Bus

M8C CPUCore

Flash ProgramMemory

MACMultiply

Accumulate

DecimatorWatchdog/

Sleep TimerLVD/POR

InterruptController

Oscillatorand PLL

Comparison Between PSoC and HiBRID

• PSoC ( Programmable SoC )Array of Analog BlocksArray of Digital BlocksGeneral Purpose Architecture

• HiBRIDMore suitable for Multimedia ApplicationThree cores for different class of functionality

Conclusion

• Use the appropriate DSP architecture for different applications.

• Multiple codecs can be efficiently implemented on a single platform

• Hybrid SoC architecture is the optimal solution for various kinds of video and image applications.

• “The M-PIRE MPEG-4 codec DSP and its macroblock engine,” in Proc. 2000 IEEE Int. Symp. Circuits Syst., pp. II 192-195.

• “HIPAR-DSP 16, A Scalable Highly Parallel DSP Core For System On A Chip Video And Image Processing Applications,” in Proc. 2002 IEEE Int. Conf. Acoust. Speech Signal Processing, May 2002.

• ARM Ltd. (1999, May). AMBA Specification Rev. 2.0. [Online]. Available: www.arm.com

• “Instruction set extensions for MPEG-4 video” J. VLSI Signal Processing Syst., vol. 23, pp. 27-50,Oct. 1999.

• “VLSI Architecture for Mpeg-4” Peter Pirsch, Mladen Berekovic, Hans-Joachim Stolberg, and Jom Jachalsky.

• “Open multimedia application platform: enabling multimedia applications in third generation wireless terminals through a combined RISC/DSP architecture” Jamil Chaoui, Ken Cyr, Sebastien de Gregorio, Jean-Pierre Giacalone, Lennifer Webb, Yves Masse.

• “HIBRID-SOC: A multi-core architecture for image and video applications” M. Berekovic, S. flugel, H-J. stolberg, L. Friebe, S. Moch, M. B. Kulaczewski, P. pirsch

Reference