Upload
tung-la
View
54
Download
6
Embed Size (px)
DESCRIPTION
Cấu trúc PIC
Citation preview
TRƯỜNG ðẠI HỌC KHOA HỌC TỰ NHIÊNTRƯỜNG ðẠI HỌC KHOA HỌC TỰ NHIÊNKHOA ðIỆN TỬ KHOA ðIỆN TỬ -- VIỄN THÔNGVIỄN THÔNG
VI ðIỀU KHIỂN PICVI ðIỀU KHIỂN PICVI ðIỀU KHIỂN PICVI ðIỀU KHIỂN PIC
1
ðặngðặng LêLê KhoaKhoa
TàiTài li ệuliệu thamtham kh ảokhảo•• SáchSách::
Designing Embedded Systems with PIC Microcontrollers Designing Embedded Systems with PIC Microcontrollers (principles and applications), 1st Ed, Tim (principles and applications), 1st Ed, Tim WilmshurstWilmshurst, , published by published by NewnesNewnes, 2007, 2007
•• BàiBài giảnggiảng•• BàiBài giảnggiảng•• Link Link thamtham khảokhảo: : http://psut.edu.jo/sites/qarallehhttp://psut.edu.jo/sites/qaralleh
2
CHƯƠNG 1: GIỚI THIỆU
• Hệ thống nhúng• Vi ñiều khiển• Các họ vi ñiều khiển
3
Hệ thống nhúng
• “A system whose principal function is not computational, but which is controlled by a computer embedded within it”within it”
• Ứng dụng rất phổ biến trong các thi ết bị trong nhà, v ăn phòng, ñiều khi ển xe hơi
• Thường sử dụng 1 vi ñiều khi ển
4
Một số ứng dụng hệ thống nhúng
5
Vi ñiều khiển là gì?
• Mini-Computer– Microprocessor
• The Brains• Arithmetic Logic Unit
(ALU)• Control Unit• Control Unit
• Program/ Data Storage
• Peripherals (Input/Output)
• Low-Cost
6
Kiến trúc Vi ñiều khiển
CPUMemory I/O
(Ports A, B & C)
7
A Computer on a chip
Timer
0
Timer
1
Timer
2
PWM
1
PWM
2
10-bit
A/DUSART
Microcontroller Families
8
9
PIC12F508/509 block diagram
10
CHƯƠNG 2: CẤU TRÚC HỌ PIC 18F452
• Sơ ñồ khối• Các giao tiếp• Bộ ALU• Mạch reset• Mạch reset• Các thanh ghi
11
PIC 18F452 General Architecture
12
PIC 18F452 : Peripherals
• The PIC 18F452 has the following peripherals:– Data ports:
• A (6-Bits)• B, C and D (8-Bits)• E (3- bits)• E (3- bits)
– Counter/Timer modules.• Modules 0,2 (8-Bits)• Modules 1,3 (16-Bits)
– I2C/SPI serial port.– USART port.– ADC 10-bits with 8-way input
multiplexer.– EEPROM 256 Bytes
13
Microprocessor Unit
• Includes Arithmetic Logic Unit (ALU), Registers, and Control Unit
14
Arithmetic Logic Unit (ALU)
• CPU dẫn nạp lệnh từ bộ nhớ, giải mã, và gửichúng ñến bộ ALU ñể thực thi
• ALU thực thi các lệnh cộng, trừ, dịch và cácphép toán logic.phép toán logic.
• ALU hoạt ñộng kết hợp với:– Một thanh ghi ña dụng gọi là thanh ghi W– Và thanh ghi f có thể ñịnh vị trong vùng nhớ dữ
liệu– Giá trị cố ñịnh (Literal) nhúng trong chương trình
15
Arithmetic Logic Unit
16
ExampleADDWF F, d, a ;Add WREG to File (Data) Reg.
;Save result in W if d =0;Save result in F if d = 1
Reset
• Reset sẽ ñặt vi ñiều khiển về trạng thái ban ñầu mà bộ vi xử lý sẽ thực thi lệnh ñầu tiên
• Reset có thể từ các yếu tố sau:– Reset ngoài bằng cách kéo MCLR xuống thấp.– Reset ngoài bằng cách kéo MCLR xuống thấp.– Reset khi mở nguồn– Reset khi bộ watchdog timer bị tràn
• Reset sẽ làm mất dữ liệu
17
18
Registers– Bank Select Register (BSR)
• Thanh ghi 4 bit dùng ñể ñịnh ñịa chỉ trực tiếp trong bộ nhớ dữ liệu– File Select Registers (FSRs)
• Thanh ghi 16-bit ñược dùng như là con trỏ trong ñịnh ñịa chỉ gián tiếp trong bộ nhớ
– Program Counter (PC)• Thanh ghi 21-bit lưu trữ ñịa chỉ chương trình khi chương trình
thực thithực thi
19
CHƯƠNG 3: BỘ NHỚ
• Bus ñịa chỉ• Các tín hiệu ñiều khiển• Bộ nhớ PIC18F452• Bộ nhớ chương trình• Bộ nhớ chương trình• Bộ nhớ dữ liệu• ðịnh vị ñịa chỉ
20
PIC18F - Address Buses• BUS ñịa chỉ
– Bus ñịa chỉ có 21-bit: có bộ nhớ 2MB – Bus ñịa chỉ 12-bit: có khả năng quản lý bộ nhớ 4KB
21
Data Bus and Control Signals• Bus dữ liệu
– 16-bit instruction/data bus for program memory– 8-bit data bus for data memory
• Các tín hiệu ñiều khiển– Read và Write
22
PIC18F452/4520 Memory
• Bộ nhớ chương trình (Flash)
• Bộ nhớ dữ liệu
23
FFF=212=16x256=4096=4K
Program Memory
Bộ ñếm chương trình 21-bit có khả năngñịnh vị bộ nhớ
chương trình2-Mbyte.
Vector RESET ở ñịa chỉ0000h và vector ngắt ở ñịa chỉ 0008h và 0018h.
24
Truy xuất vùng nhớvới nội dụng là các số
’0 (là một lệnh).
PIC18F452 có 32 Kbytes bộ nhớ FLASH. ðiều này có nghĩa làchúng có thể lưu trữ 16K lệnhñơn.
Access RAM
Data Memory Organization
• Bộ nhớ dữ liệu lên ñến 4k bytes
• Chia thành các băng 256 byte
• Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter
PIC16F8F2520/4520
Register File Map
000h
07Fh
Bank 0 GPR
Bank 1GPR
Bank 2GPR
080h
0FFh
100h
1FFh
200h
2FFh00h
Access Bank
that is accessible no matter which bank is selected
25
256 BytesBank 13
GPR
Bank 14GPR
Bank 15 GPR
Access SFR
Access RAM
Access SFRD00h
DFFh
E00h
EFFh
F00h
FFFh
F7Fh
F80h
00h
7Fh
80h
FFh
Data Memory with Access Banks
GPR=General Purpose Reg.
SFR=Special Function Reg.
These registers are always
accessible regardless which
bank is selected – acting as a
virtual memory -
26
FFF=212=16x256=4096=4K
Data Memory also known as
“Register File”We will discuss the access to
every region later, while talking
about PIC18 instructions
Accessing Data Memory
• The machine code for a PIC18 instruction has only 8 bits for a data memory address which needs 12 bits. The Bank Select Register (BSR) supplies the other 4 bits.
27
Data Memory Addressing�Direct Addressing - Operand address(es)
embedded in the opcode� 8 bits of the 16-bit instruction specify any one of 256
locations
� The 9th bit specifies either the Access Bank (=0) or one
28
� The 9 bit specifies either the Access Bank (=0) or one of the banks (=1)
Data Memory Addressing�Direct Addressing Examples
�Direct addressing (banked)
movlb 02 ;set BSR to Bank 2 addwf 0x55, W, BANKED ; add WREG with the content of
; addr. 55 (f=55) in bank 2 (a=1),
29
; addr. 55 (f=55) in bank 2 (a=1), ; save the result to WREG (d=0)
Operand is the content of data memory at add. 0x255
Mnemonic in MPASM:A (a=0) - the access bank; BANKED (a=1) - bankedW (d=0) - the WREG register; F (d=1) - the data register
Data Memory Addressing�Direct Addressing Examples
�Direct addressing (using access bank)
;movlb not required addwf 0x55, F, A ; add WREG to content of
30
addwf 0x55, F, A ; add WREG to content of ; addr. 55 (f=55) in access ; bank (a=0), save the result; in the data memory at the ;address 0x55 (d=0)
Operand is the content of data memory add. 0x055
� Indirect Addressing� 3 File Select Registers (FSR) as a pointer to
the data memory location that is to be read or written.
Data Memory Addressing
31
� Each FSR has an INDF register associated with it
� The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register.
� Indirect Addressing
Data Memory Addressing
32
LFSR 02, num1 ;load FSR2 with the add. of num1 MOVWF INDF2, W ; move WREG to the register
; pointed by FSR2
� Indirect Addressing Operations
Data Memory Addressing
33
� Indirect Addressing Examplecount set 0x02lfsr 0, num1lfsr 1, num2movlw 3movwf count, A
Data Memory Addressing
34
movwf count, Abcf STATUS, c
addwfc POSTINC0, F
decfsz count, 1
bra Again
Again: movf POSTINC1, W
SFRs Examples
35
CHƯƠNG 4: CÁC CỔNG I/OCHƯƠNG 4: CÁC CỔNG I/O
36
PIC18F452 I/O Ports
• Five I/O ports– PORT A through PORT E
– Most I/O pins are multiplexed
– Generally have eight I/O pins with a few exceptions
– Addresses already assigned to these ports in the design stage
– Each port is identified by its assigned SFR – Each port is identified by its assigned SFR
37
Parallel I/O Combined I/O Structure
38
Parallel I/O ports Main Features
• Simple memory mapped access
• Can be configured through software as either input or output
• Ability to set or reset individual bits• Ability to set or reset individual bits
• Can have internal pull-ups
• Can drive small loads like LEDs
• Can be multifunction
• Different capability for pins (i.e. larger current)
39
Parallel I/O ports
• For most ports, the I/O pin’s direction (input or output) is controlled by the data direction register TRISx (x=A,B,C,D,E): a ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’ corresponds to that pin being an output
• The PORTx register is the latch for the data to be output. Reading PORTx register read the status of the pins, whereas writing to it will write to the port latch.
• Example: Initializing PORTB (PORTB is an 8-bit port. Each pin is individually configurable as an input or output).
• Example: Initializing PORTB (PORTB is an 8-bit port. Each pin is individually configurable as an input or output).
bcf STATUS, RP0 ; select bank0
bcf STATUS, RP1
clrf PORTB ; clear PORTB output data latches
bsf STATUS, RP0 ; select bank1
movlw 0xCF ; value used to initialize data direction
movwf TRISB ; PORTB<7:6>=inputs, PORTB<5:4>=outputs,
; PORTB<3:0>=inputs
40
Relationship between TRIS and PORT
Registers
41
Illustration: Displaying a Byte
at an I/O Port (1 of 5)
• Problem statement:
– Write instructions to light up alternate LEDs at
PORTC.
• Hardware: • Hardware:
– PORTC
• bidirectional (input or output) port; should be setup as
output port for display
– Logic 1 will turn on an LED in Figure 2.10.
42
Illustration (2 of 5)
• Interfacing LEDs to
PORTC
• Port C is F82H
TRISC=0
• Port C is F82H
• Note that PORT C is
set to be an output!
• Hence, TRISC
(address 94H) has to
be set to 0
43
Illustration (3 of 5)
• Program (software)
– Logic 0 to TRISC sets up PORTC as an output port
– Byte 55H turns on alternate LEDs • MOVLW 00 ;Load W register with 0• MOVLW 00 ;Load W register with 0
• MOVWF TRISC, 0 ;Set up PORTC as output
• MOVLW 0x55 ;Byte 55H to turn on LEDS
• MOVWF PORTC,0 ;Turn on LEDs
• SLEEP ;Power down
44
PIC18F Programming Model and
Its Instruction Set Its Instruction Set
PIC18F Programming Model
• The representation of the internal architecture of a microprocessor, necessary to write assembly language programs programs
• Divided into two groups– ALU Arithmetic Logic
Unit (ALU)
– Special Function Registers (SFRs) from data memory
Registers
• WREG
– 8-bit Working Register (equivalent to
an accumulator)
• BSR: Bank Select Register• BSR: Bank Select Register
– 4-bit Register (0 to F)
• Only low-order four bits are used to
provide MSB four bits of a12-bit
address of data memory.
• STATUS: Flag Register
• C (Carry/Borrow Flag):
Example: 9F+52 =F11001 11110101 0010-------------1111 0001 N=1,OV=0, Z=0, C=0, DC=1
Flags in Status Register
• C (Carry/Borrow Flag): – set when an addition generates a carry and a subtraction generates a borrow
• DC (Digit Carry Flag): – also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an arithmetic
operation
• Z (Zero Flag): – set when result of an operation is zero
• OV (Overflow Flag): – set when result of an operation of signed numbers goes beyond seven bits
• N (Negative Flag): – set when bit B7 is one of the result of an arithmetic /logic operation
File Select Registers (FSR)
• There are three registers:
• FSR0, FSR1, and FSR2
• Each register composed of two 8-bit
registers (FSRH and FSRL)
• Used as pointers for data
registers
• Holds 12-bit address of data
register
Other Registers
• Program Counter (PC)
– 21-bit register functions as a pointer to program memory during program execution
• Table Pointer
– 21-bit register used as a
• Stack
– 31 word-sized registers used for temporary storage of memory addresses during execution of a program
• Special Function Registers – 21-bit register used as a
memory pointer to copy bytes between program memory and data registers
• Stack Pointer (SP)
– Register used to point to the stack
• Special Function Registers (SFRs):
– Data registers associated with I/O ports, support devices, and processes of data transfer