cerlog programs

7/30/2019 cerlog programs

1/60

KCG COLLEGE OF TECHNOLOGY

KARAPAKKAM

CHENNAI-600097

LABORATORY RECORD

REG NO: 1072064 NAME: VENISHKUMAR.T

M.E.VLSI DESIGN

II-SEMISTER

252252 VLSI LAB-II

DEPARTMENT OF VLSI DESIGN ENGINEERING


2/60

KCG COLLEGE OF TECHNOLOGY

KARAPAKKAM

CHENNAI-6000097

RECORD CERTIFICATE

Registerno. : 1072064

Name of The Lab : VLSI DESIGN LABORATORY II

Department : VLSI DESIGN ENGINEERING

Name of The Examination : M.E DEGREE

Certified that this Bonafied record Of The work done in the VLSI

DESIGN LABORATORY By Mr.T.Venishkumar Of Master Of

Engineering (M.E.VLSI DESIGN) II Semester During The Year 2010-

2011.

(T.THOMAS LEONID) (Dr.V.RANGANATHAN)Faculty in Charge Head of the VLSI Department

Internal Examiner External Examiner


3/60

INDEX

Exp no Date Title Page no Signature

1 Implementation of 4bit ALUin VHDL and Verilog

2Implementation of 4 bit Sliced

processor in VHDL

3

Implementation of elevator

controller using Embedded

micro controller

4Implementation of Alarm

clock controller using

Embedded micro controller

5Implementation of Model

Train controller using

Embedded micro controller

6 System Design using PLL


4/60

LIST OF FIGURES:

Exp No Figure No Figure name Page No

1

1.1 Block diagram

1.2 RTL Schematic

1.3 Schematic Diagram

1.4 Output Waveform

2

2.1 Block Diagram

2.2 RTL Schematic

2.3 Output Waveform

3

3.1 Block Diagram

3.2 Flow Chart

3.3 Logic Of The Program

3.4 Observation

3.5 Output

3.6 PIC SimulationOutput

4

4.1 Front Panel Display

4.2 Seven Segment

Display

4.3 Observation

4.4 Output

4.5 PIC Simulation Output

5

5.1 Model Train

Controller

5.2 Flow Chart

5.3 Logic of the Program

5.4 Observation

5.5 Output

5.6 PIC Simulation Output

6

6.1 Block Diagram

6.2 RTL Schematic

6.3 Schematic Diagram

(Id_counter)6.4 Output Waveform


5/60

Exp: 1Date:

IMPLEMENTATION OF 8 BIT ALU USING VHDL/VERILOG

AIM:

To design and implement a 8 bit ALU in both VHDL and Verilog.

TOOL REQUIRED:

Xilinx ISE 9.1i

THEORY:

An arithmetic and logic unit is a combinational circuit that performs

arithmetic and logic operations on a pair of n bit operands. The operationsperformed by an ALU are controlled by a set of function select inputs. An ALU

combines addition, subtraction with operations such as shifting and bitwise logic

operations.ALU consists of arithmetic unit, multiplexers and logic unit. The core of the

microprocessor or microcontroller is the arithmetic and logic unit.

PROCEDURE:

Create a new project in Xilinx 9.1i and give the inputs and outputs

variables through VHDL/ Verilog module.

Program has to be entered into the body of Architecture and have to

check the syntax.

To give inputs have to create a new source to the test bench waveform.

By changing the synthesis implementation model have to execute and

simulate the output waveform.


6/60

VHDL PROGRAM FOR ALU

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity aluvhdl2 is

port ( a,b :in std_logic_vector(7 downto 0);

clk :in std_logic;

rst :in std_logic;

s :in std_logic_vector(3 downto 0);c :out std_logic_vector(7 downto 0));

end aluvhdl2;

architecture Behavioral of aluvhdl2 is

beginprocess(clk,rst,s,a,b)

begin

if (rst='1')thenc


7/60


8/60

process

begin

for i in 0 to 255 loopfor j in 0 to 255 loop

for k in 0 to 15 loop

wait for 10 ns;s


9/60

reg [7:0] a;

reg [7:0] b;

reg [3:0] s;

wire [15:0] c;integer i,j,k;

aluu uut (

.clk(clk),

.a(a),

.b(b),

.s(s),

.c(c));

initial begin

clk = 0;a = 0;

b = 0;s = 0;

for(k=0;k


10/60

BLOCK DIAGRAM:

Figure 1.1

FUNCTIONAL TABLE:

S(3) S[2 downto 0] Operation

0

000 a - b

001 a + 1010 a - 1

011 b - a

100 b + 1

101 a / b

110 a + b

111 a * b

1

000 a nand b

001 a or b

010 a nor b

011 not a

100 a xor b101 a xnor b

110 a and b

111 a and b


11/60

RTL SCHEMATIC:

Figure1.2

SCHEMATIC DIAGRAM:

Figure 1.3


12/60

OUTPUT WAVEFORM:

OUTPUT 1:

a = 11011101 (input 1, 8 bit)

b = 00000011 (input 2, 8 bit)

s = 0000 (addition selected, 4bit)c = 0000000011100000 (result, 16 bit )

OUTPUT 2:

a = 10100000 (input 1, 8 bit)

b = 00000001 (input 2, 8 bit)s = 0111 (a AND b, 4bit)

c = 0000000000000000 (result, 16 bit )

Fig. 1.4


13/60

Exp: 2Date:

IMPLEMENTATION OF 4 BIT SLICE PROCESSOR USING

VHDL

AIM:

To implement 4 bit slice processor in VHDL

TOOL REQUIRED:

Xilinx ISE 9.1i

THEORY:

A 4-bit sliced processor which can perform various arithmetic and logical

functions. It has two ALU units.Each ALU has a accumulator and a register. The two inputs are sliced in

to two parts. The lower nibbles are given to accum1 and Breg1 and higher

nibbles are given to accum2 and Breg2. the operations are performed and theoutputs are appended to get the final result.

PROCEDURE:

Create a new project in Xilinx 9.1i

Create a VHDL/ Verilog module and enter the code for 4 bit sliceprocessor.

Synthesis the program and generate the RTL schematic.

Add a test bench module to the project.

Write test bench code to test various combinations of the inputs in theprogram.

Simulate the testbench and view the output waveform.


14/60

VHDL CODE (4 BIT SLICE processor)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity slice isport(x,y : in std_logic_vector(7 downto 0);

start : in std_logic;

result : out std_logic_vector(7 downto 0);mulout : out std_logic_vector(15 downto 0);

operation : in std_logic_vector(3 downto 0);

functionload : in std_logic_vector(3 downto 0));

end slice;

Architecture Behavioral of slice is

signal carry1,carry2,borrow1,borrow2 : std_logic;signal accum1,accum2 : std_logic_vector(3 downto 0);

signal Breg1,Breg2 : std_logic_vector(3 downto 0);

signal m1,m2 : std_logic_vector(7 downto 0);signal sum1,sum2 : std_logic_vector(4 downto 0):="00000";

signal control1,control2 : std_logic_vector(3 downto 0);

signal exe1,exe2,add,sub:bit : ='0';

signal zout1 : std_logic_vector(3 downto 0):="0000";signal zout2 : std_logic_vector(3 downto 0):="0000";

begin

p1:process(x,y,operation,functionload,start)

beginif(start='1') then

exe1


15/60

result


16/60

borrow1


17/60

elsif(accum2'0');

--Outputs

SIGNAL result : std_logic_vector(7 downto 0);


18/60

SIGNAL mulout : std_logic_vector(15 downto 0);

begin

-- Instantiate the Unit Under Test (UUT)

uut: slice PORT MAP(

x => x,y => y,

start => start,

result => result,mulout => mulout,

operation => operation,

functionload => functionload

);

tb1 : process

begin

wait for 100 ns;start


19/60

The design and implementation of 4 bit slice processor has done in

VHDL.

BLOCK DIAGRAM

Fig.2.1

FUNCTIONAL TABLE

Function Load Operation

0000 OR

0001 AND

0010 NOR

0011 NAND

0100 XOR

0101 NOT x

0110 NOT y

0111 shift right x

1000 shift right y

1001 shift left x1010 shift left y

1011 rotate left x

1100 rotate right y

1101 Add x and y

1110 Subtract y from x

1111 Multiply x and y


20/60

Table 2.1

RTL SCHEMATIC

Fig.2.2

OUTPUT WAVEFORM

OUTPUT 1:

x = 00000001(input 1, 8 bit)

y = 00001111(input 2, 8 bit)Function load = 0000(x OR y)

Result = 00001111(8 bit)

OUTPUT 2:

x = 00000001(input 1, 8 bit)y = 00000100(input 2, 8 bit)


21/60

Function load = 0110(NOT y)

Result = 11111011(8 bit)

OUTPUT 3:

Start = 1

x[7:0] = 8b00000001

y[7:0] = 8b00000010function load[3:0] = 4b0110

result[7:0] = 8b11111110

Fig 2.3


22/60

Exp: 3Date:

IMPLEMEMTATION OF ELEVATOR CONTROLLER

USING PIC MICROCONTROLLER (PIC16F8778)

AIM:

To implement elevator controller using embedded microcontroller

PIC16F8778.

TOOLS:

MPLAB.IDE package

PIC Simulator

THEORY:

The elevator uses the principles of distributed system designing thecomponents are physically distributed among the elevator and flows of the

building. The elevator car is the unit that runs up and down in the host way can

stop at only floor every elevator car has a control panel that allow the passengerto select the floor to stop at each floor has a single control panel at calls for an

elevator. Each floor has a set of displays to show the current position of the

elevator car. The user interface consists of elevator floor control panel anddisplays. There is one display per host way always shows the some state.

PROCEDURE:

Select the MPLAB icon from the desktop.

Select the FILE menu from the menu bar and then select NEW.

Enter the program and save it with .ASM extension.

Select the project from menu bar and then select project wizard, then

select the device PIC16F877A and click next and next.

Enter the project name and enter the project directory.

Now add the saved program to project as source files.

Select project and click BUILDALL, if coding is switch out Build

succeeded will appear on the screen. Select the PIC simulator IDE from the desktop.

The file select menu from the menu bar and load the hexafile.

Select the tools from menu bar and select corresponding hardwaredisplays.

Select the simulation to start the program.

The output is displayed on LEDS.


23/60

PROGRAM

LIST P= PIC16F877A

INCLUDE "P16F877A.INC"ORG 0X00

BSF STATUS,RP0

BCF STATUS,RP1MOVLW 0X00

MOVWF TRISB

BCF STATUS,RP0LOOP:MOVLW 0X80

MOVWF PORTB

CALL DELAY

MOVLW 0X90

MOVWF PORTBCALL DELAY

MOVLW 0X40MOVLW PORTB

CALL DELAY

MOVLW 0X48MOVWF PORTB

CALL DELAY

MOVLW 0X80MOVWF PORTB

CALL DELAY

MOVLW 0XA0MOVWF PORTBCALL DELAY

MOVLW 0X84


MOVLW 0X40


GOTO LOOP

DELAY: MOVLW 0X80

MOVWF 0X20WAIT: DECFSZ 0X20,F

GOTO WAIT

RETURNEND


24/60

RESULT:


25/60

Thus the elevator controller using embedded controller PIC 16F877A is

implemented

BLOCK DIAGRAM

Fig 3.1


26/60

FLOW CHART

Fig 3.2


27/60

LED POSITION

G0 : Lift available at ground floor

F0 : Lift available at first floorG1 : Switch outside the lift at ground floor

F1 : Switch outside the lift at first floor

G2 : Switch inside the lift at ground floor

F2 : Switch inside the lift at first floor

G3 : unused switch for ground floor

F3 : unused switch for first floor

LOGIC OF THE PROGRAM

Fig 3.3

Step 1: Lift is at ground floor.

1 0 0 0 0 0 0 0 - 80HStep 2: Outside switch at first floor is pressed.

1 0 0 1 0 0 0 0 - 90HStep 3: Now lift is at first floor.

0 1 0 0 0 0 0 0- 40HStep 4: Inside switch for ground floor is pressed.

0 1 0 0 1 0 0 0 - 48HStep 5: Now lift is at ground floor.

1 0 0 0 0 0 0 0 - 80HStep 6: Outside switch at ground floor is pressed.

1 0 1 0 0 0 0 0 - A0HStep 7: Inside switch for first floor is pressed.


28/60

1 0 0 0 0 1 0 0 - 84HStep 8: Now lift is at first floor.

0 1 0 0 0 0 0 0 - 40H

OBSERVATION


29/60

Fig 3.4


30/60

OUTPUT

Fig 3.5

.


31/60

PROGRAM

#INCLUDE"P16F877A.INC"

M EQU 0X20H EQU 0X21

LSD EQU 0X22

MSD EQU 0X23L_MIN EQU 0X24

M_MIN EQU 0X25

L_HOUR EQU 0X26M_HOUR EQU 0X27

D1 EQU 0X28

D2 EQU 0X29MIN EQU 0X2A

HOUR EQU 0X2BA_MIN EQU 0X2C

A_HOUR EQU 0X2DORG 0X00

GOTO MAIN

ORG 0X04RETFIE

MAINCLRF M

CLRF H

CLRF MSDCLRF LSD

MOVLW 0X25

MOVWF A_MIN

MOVLW 0X05MOVWF A_HOUR

BANKSEL TRISBCLRF TRISB

banksel TRISD

clrf TRISD

banksel TRISCCLRF TRISC

BANKSEL PORTB

BSF PORTB,6CLRF STATUS

L1INCF M: INCREMENT MINUT


32/60

MOVF M,W

CALL HDMOVF LSD,W

MOVWF L_MIN

MOVF MSD,WMOVWF M_MIN

SWAPF M_MIN,WIORWF L_MIN,W

MOVWF MIN

CALL ALARMMOVLW 0X01

MOVWF PORTC

MOVF L_MIN,W

CALL ASSIGNMOVWF PORTD

CALL DELAY

MOVLW 0X02

MOVWF PORTCMOVF M_MIN,W

CALL ASSIGN

MOVWF PORTD

CALL DELAY

MOVF M,WSUBLW 0X3C

BTFSS STATUS,2

GOTO L1

INCF H ;INCREMENT HOUR

MOVF H,W

CALL HDMOVF LSD,W

MOVWF L_HOUR

MOVF MSD,WMOVWF M_HOUR

MOVLW 0X04MOVWF PORTC

MOVF L_HOUR,W

CALL ASSIGN

MOVWF PORTD


33/60

CALL DELAY

MOVLW 0X08MOVWF PORTC

MOVF M_HOUR,W

CALL ASSIGNMOVWF PORTD

CALL DELAY

SWAPF M_HOUR,W

IORWF L_HOUR,W

MOVWF HOUR

CLRF M

MOVF H,WSUBLW 0X17

BTFSS STATUS,2GOTO L1

GOTO MAIN

HD

CLRF MSD

MOVWF LSD

MOVLW 0X0A

LOOP

INCF MSDSUBWF LSD,F

BTFSC STATUS,0

GOTO LOOPDECF MSD,F

ADDWF LSD,F

RETURN

ALARM

SUBWF A_MIN,WBTFSS STATUS,2

RETURN

MOVF HOUR,WSUBWF A_HOUR,W

BTFSS STATUS,2

RETURN

BANKSEL PORTB


34/60

BSF PORTB,7

RETURN

ASSIGNADDWF PCL,1

RETLW 0X3F

RETLW 0X06RETLW 0X5B

RETLW 0X4F

RETLW 0X64RETLW 0X6D

RETLW 0X7D

RETLW 0X07

RETLW 0X7FRETLW 0X6F

DELAY

MOVLW 0X01

MOVWF D1L3

MOVLW 0X02

MOVWF D2L4

DECFSZ D2,1

GOTO L4

DECFSZ D1,1GOTO L3

RETURNEND

RESULT:


35/60

Thus the alarm clock using embedded controller PIC 16F877A is

implemented.

FRONT PANEL DISPLAY:

Fig 4.1

SEVEN SEGMENT DISPLAY:

Fig 4.2


36/60

OBSERVATION

Fig 4.3


37/60

OUTPUT

Exp: 5Date:

IMPLEMENTATION OF MODEL TRAIN CONTROLLERUSING EMBEDDED MICROCONTROLLER (PIC16F877A)

AIM:

To implement model train controller using embedded microcontroller

PIC18F877A.

TOOLS:

MPLAB.IDE package PIC Simulator

THEORY:

The signal message to the train is given with a help of a control attached to

the tracks, the control such as Throttle, Emergency stop button and so on. Thetrain receives electrical power from the two rails and the tracks. The control boxes


38/60

can senses signal to the train over the tracks by modulating the power supply

voltage.

The control panel sense packet over the tracks to the receiver on the train.

The train includes analog electro routes to the packets being transmitted under

control system to act the train motor speeds and direction based on thosecommand.

Each packet involves so that the console can control several train on thesame tracks. The packet has a error correction code to guard against transmission

errors. The model train can not send commands and back to the user.

PROCEDURE:

Select the MPLAB icon from the desktop.

Select the FILE menu from the menu bar and then select NEW.

Enter the program and save it with .ASM extension. Select the project from menu bar and then select project wizard, then

select the device PIC16F877A and click next and next.

Enter the project name and enter the project directory.

Now add the saved program to project as source files.

Select project and click BUILDALL, if coding is switch out Build

succeeded will appear on the screen.

Select the PIC simulator IDE from the desktop.

The file select menu from the menu bar and load the hexafile.

Select the tools from menu bar and select corresponding hardware

displays.

Select the simulation to start the program.

The output is displayed on LEDS.

PROGRAM:

LIST P= PIC16F877A

INCLUDE "P16F877A.INC"ORG 0X00

BSF STATUS,RP0

BCF STATUS,RP1

MOVLW 0X00MOVWF TRISB

BCF STATUS,RP0

LOOP: MOVLW 0XA0;0X80MOVWF PORTB

CALL DELAY

MOVLW 0XB0;0X90MOVWF PORTB


39/60

CALL DELAY

MOVLW 0X40

MOVLW PORTBCALL DELAY

MOVLW 0X90;0X48MOVWF PORTB

CALL DELAY

MOVLW 0X94;0X80MOVWF PORTB

CALL DELAY

MOVLW 0X40;0XA0


MOVLW 0X84

MOVWF PORTB

CALL DELAYMOVLW 0X85;0X40


MOVLW 0X40


MOVLW 0X81

MOVWF PORTB

CALL DELAYMOVLW 0XA1

MOVWF PORTB

CALL DELAYMOVLW 0X40

MOVWF PORTB

CALL DELAYMOVLW 0XA0

MOVLW PORTB

CALL DELAY

GOTO LOOP

DELAY: MOVLW 0X80MOVWF 0X20

WAIT: DECFSZ 0X20,F

GOTO WAITRETURN

END


40/60

RESULT:

Thus the model train controller using embedded microcontroller with

PIC16F877A is implemented

MODEL TRAIN CONTROLLER:


41/60

Fig 5.1

FLOW CHART:


42/60

Fig 5.2


43/60

Fig 5.3

Step 1: Train stops at station 1.

1 0 1 0 0 0 0 0 - A0HStep 2: Train has to go to station 2.

1 0 1 1 0 0 0 0 - B0HStep 3: Train is moving.

0 1 0 0 0 0 0 0 - 40HStep 4: Train reaches and stops at station 2.

1 0 0 1 0 0 0 0 - 90HStep 5: Train has to go to station 4.

1 0 0 1 0 1 0 0 - 94HStep 6: Train is moving.

0 1 0 0 0 0 0 0 - 40HStep 7: Train reaches station 4 and stops.

1 0 0 0 0 1 0 0 - 84HStep 8: Train has to go to station 6.1 0 0 0 0 1 0 1 - 85H

Step 9: Train is moving.

0 1 0 0 0 0 0 0 - 40H

Step 10: Train reaches station 6 and stop.

0 0 0 0 0 0 0 0 - 81HStep 11: Train has to go to station 1.

1 0 1 0 0 0 1 0 - A1HStep 12: Train is moving.

0 1 0 0 0 0 0 0 - 40HStep 13: Train reaches station 1 and stops.

1 0 1 0 0 0 0 0 - A0H


44/60

OBSERVATION


45/60


46/60


47/60

Fig 5.4


48/60

OUTPUT:

Fig 5.5


49/60

PIC SIMULATION OUTPUT

Fig 5.6


50/60

Exp: 6

Date:

SYSTEM DESIGN USING PHASED LOCKED LOOP (PLL)

AIM:

To implement system design using pll

TOOL REQUIRED:

Xilinx ISE 9.1i,

FPGA Kit

THEORY:

A Phase locked loop is a control system that tries to generate an outputsignal whose phase is related to phase of the input reference signal.It is an

electronic circuit consisting of variable frequency oscillator and a phase detector.This circuit compares the phase of the input signal with the phase of the signal

derived from its output oscillator and adjusts the circuit of its oscillator to keepthe phase match. The signal from phase detector is used to control the oscillator in

a feed back loop,

PROCEDURE:

Create a new project in Xilinx.

Create a verilog module in it and enter the coding for pll.

Synthesize the program and create the RTL schematic.

Add a test bench module to the project.

Write a test bench to test various combinations of the input in the

program.

Simulate the test bench and view the output waveform.


51/60

VERILOG PROGRAM:

module DPLL(sys_clock,

reset,

enable,Fin,

Fout,

Kmode);

input sys_clock,

reset,enable,

Fin;

input[2:0] Kmode;

output Fout;

wire se,

carry,borrow,IDclock,

IDout;

reg[2:0] cnt_H; // H =8reg[5:0] cnt_N; // N =32

/*********** Phrase Detector ***********/

xor cmp(se, Fin, Fout);

/*********** DLF ***********/k_counter k_counter(.Kclock(sys_clock),.reset(reset),

.dnup(se),

.enable(enable),

.Kmode(Kmode),

.carry(carry),

.borrow(borrow));

reg q1,q2,

carry_out;wire clr = carry_out;

always @(posedge carry or negedge reset)

if(~reset|clr)q1


52/60

if(~reset)

q2


53/60

endmodule

K_COUNTER:

module k_counter(Kclock,

reset,dnup,enable,

Kmode,

carry,borrow

);

input Kclock,

reset,dnup,

enable;

input[2:0] Kmode;

output carry,borrow;

reg[8:0] count;

reg[8:0] Ktop;

always @(Kmode)

begin

case(Kmode)

3'b001: Ktop = 7;3'b010: Ktop = 15;

3'b011: Ktop = 31;

3'b100: Ktop = 63;3'b101: Ktop = 127;

3'b110: Ktop = 255;

3'b111: Ktop = 511;default:Ktop = 15;

endcase

end

always @(posedge Kclock or negedge reset)

begin

if(~reset)count


54/60

else

count


55/60

);

FFD FFD3(.clock(IDclock),

.reset(reset),

.D(Q1),

.Q(Q3),

.Q_not(Qn3));


.reset(reset),

.D(Q2),

.Q(Q4),

.Q_not(Qn4)

);FFD FFD5(.clock(IDclock),

.reset(reset),

.D(Q3),

.Q(Q5),.Q_not(Qn5)

);FFD FFD6(.clock(IDclock),

.reset(reset),

.D(Q4),

.Q(Q6),

.Q_not(Qn6)

);

assign D7=((Q9 & Qn1 & Q3) | (Q9 & Q5 & Qn3));

assign D8=((Qn9 & Qn2 & Q4) | (Qn9 & Q6 & Qn4));


.reset(reset),

.D(D7),

.Q(Q7),

.Q_not(Qn7)

);

FFD FFD8(.clock(IDclock),.reset(reset),

.D(D8),

.Q(Q8),

.Q_not(Qn8)

);

JK FFJK(.clock(IDclock),.reset(reset),

.J(Qn7),

.K(Qn8),

.Q(Q9),


56/60

.Q_not(Qn9)

);

assign IDout = ~((IDclock)|Q9);

endmodule

D_FLIPFLOP:

module FFD(clock,

reset,

D,Q,Q_not

);

input clock,

reset,D;

output Q,Q_not;

reg Q;

always @(posedge clock or negedge reset)

if(~reset)

Q


57/60

always @(posedge clock or negedge reset)

if(~reset)

Q


58/60

RESULT:


59/60

System design using PLL is done using verilog and output verified.

BLOCK DIAGRAM:

Fig 6.1

RTL SCHEMATIC:

Fig 6.2


60/60

SCHEMATIC DIAGRAM (ID_COUNTER)

Fig 6.3OUTPUT WAVEFORM:

Fig 6.4

Documents

cerlog programs