CH14 Derivation of State Graphs and Tablesaccess.ee.ntu.edu.tw/course/logic_design_95first/lecture... · 2010-07-14 · Derivation of State Graphs and Tables ... 13.2 Analysis by

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CH14 CH14 Derivation of State Graphs and TablesDerivation of State Graphs and Tables

Lecturer：吳安宇教授

Date：2006/12/22Ver. 3.0


pp. 2台灣大學吳安宇教授

Outline (Back to Chap.13.1)Outline (Back to Chap.13.1)

13.1 A Sequential Parity Checker13.2 Analysis by Signal Tracing and Timing Charts13.3 State Tables and Graphs13.4 General Models for Sequential Circuits



Parity CheckParity Check

Data bits (7 bits for ASCII) ParityBit (1-bit)

Data for Transmission over the Keyboard-PC cable

7-bit data Number of 1sParity bit for

Odd Parity0000000 1

00

1

00000010101001

Transmitted data (8-bit)

1101001

EvenOdd

Odd

Even

000000010000001001010010

11010011



A Sequential Parity CheckerA Sequential Parity CheckerZ=1 if total no. of 1s is oddZ=0 if total no. of 1s is evenZ=0 indicates that an error in transmission has occurred (in odd-parity protocol). Initial Z = 0.

Timing diagram of the parity checker circuit (active-low)

Input

output



A Sequential Parity CheckerA Sequential Parity CheckerState Diagram Implementation

State Table

EVEN ODD

State assignmentS0 = 0 (EVEN state)S1 = 1 (ODD state)



OutlineOutline14.1 Design of a Sequence Detector14.2 More Complex Design Problems14.3 Guidelines for Construction of State Graphs14.4 Serial Data Code Conversion14.5 Alphanumeric State Graph Notation



14.3 Case Study I14.3 Case Study IExamines groups of 4 consecutive inputs and produce an

output.

The circuit resets after every 4 inputs.

01011001

Detector

X Z Z = 1 when X = 0101X = 1001

X = 0101 0010 1001 0100

Z = 0001 0000 0001 0000



A typical sequenceA typical sequencePartial State Graph

State Sequence receivedS0

S1

S2

S3

S4

Reset0101 or 10010 or 100

State Sequence received

S0

S1

S2

S3

S4

S5

S6

Reset0101 or 10010 or 100Two input received, no 1 output is possibleThree input received, no 1 output is possible

Complete State Graph

Input/Output

X = 0101X = 1001






Back to 14.1: Back to 14.1: ““101101”” DetectorDetector

““101101”” DetectorDetector

X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0

Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0(Time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)



““101101”” Detector (cont.)Detector (cont.)Corresponding state diagram (Mealy model)

State table of detector ( S0: Initial state, S1: 1 has been received, S2: sequence ending with 10 has been received )

11 xx xx x x



““101101”” Detector (cont.)Detector (cont.)Next state maps

Realization of detector

0 0 1 1 0 1 1 0

0 0 0 0 0 1 0 0 0



““101101”” Detector (Moore)Detector (Moore)Corresponding state diagram (Moore model)

State table of detector






Case ICase I

Detection circuit : Z = 1 when 0 1 0when 1 0 0 1

Design case study :

X = 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 1 0

a b c d e fZ = 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0



State DiagramState Diagram(1) State for “010”

State Sequence ends in

S0

S1

S2

S3

S4

S5

Reset0(but not 10)01101(but not 01)100

3) Complete State diagramState Sequence

received

S0

S1

S2

S3

Reset001010

State Sequence ends in

S0

S1

S2

S3

S4

S5

Reset0(but not 10)01101(but not 01)100

2) State for “1001”



Case II (Moore Sequential Circuit)Case II (Moore Sequential Circuit)Specifications:Z = 1 when Total no. of “1” is odd, “AND”

at least two consecutive “0” ’s have beenreceived.

Typical input/output sequence.X = 1 0 1 1 0 0 1 1

a b c d eZ =(0) 0 0 0 0 0 1 0 1



State DiagramState Diagram1) Initial state machine:

2) Consider “0” sequence:

State input sequences

S0

S1

S2

S3

S4

S5

Reset or even 1’sOdd 1’sEven 1’s and ends in 0Even 1’s and 00 has occurred00 has occurred and odd 1’sodd 1’s and ends in 0

3) Complete State diagram

State Sequence receivedS0

S1

S2

S3

S4

Reset or even 1’sOdd 1’sEven 1’s and ends in 0Even 1’s and 00 has occurred00 has occurred and odd 1’s






Guidelines for Construction of State Guidelines for Construction of State GraphsGraphs

1. Construct some sample sequences to make sure you understand the problem.

2. Determine under what conditions it should reset.

3. If only one or two sequences leads to a nonzero output, construct a partial state graph.

4. Another way, determine what sequences or groups of sequences must be remembered by the circuit and set up states accordingly.



Guidelines for Construction of State Guidelines for Construction of State Graphs (cont.)Graphs (cont.)

5. Each time you add an arrow to the state graph, determine whether it can go to one of the previously defined states or whether a new state must added.

6. Check your graph to make sure there is one and only one path leaving each state for each combination of values of the input variables.

7. When your graph is complete, test it by applying the input sequences formulated in part 1 and making sure the output sequences are correct.



Case Study II (Omitted)Case Study II (Omitted)More difficult case!

Z1=1: Complete input ”100” and “010” has never occurred beforeZ2=1: Complete input “010”

X = 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 0Z1 = 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Z2 = 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0

100/010Detector

XZ1

Z2



State DiagramState DiagramInitial state diagram

Complete state diagram



Corresponding State Table of Case IICorresponding State Table of Case II



Case Study III (Omitted)Case Study III (Omitted)

X1 Z

X2

“00” or “11”neither starts a sequence



Case Study IIICase Study IIIState Table

State diagram






Serial Data Code ConversionSerial Data Code ConversionSerial data transmission

Examples:



Case StudyCase Study

Glitch:False output

Mealy circuitOutput is depend on

Current state ( synchronous ) Input ( maybe asynchronous )

Fewer states



Case StudyCase StudyMoore circuit

Output only depends on current state (synchronous o/p)More states(in general)






Alphanumeric State Graph NotationAlphanumeric State Graph NotationExample

I/P: FFF..... Z1,Z2, Z3, Z1, Z2, Z3, I/P: RRR…. Z3.Z2, Z1, Z3, Z2, Z1

Under F>R, F’R for “Reverse”

F=R=0, State unchanged

Fig.(a) is not complete for input signals of F and R



Alphanumeric State Graph NotationAlphanumeric State Graph NotationState table

Check Input signals:1. F + F’R +F’R’ = F + F’ = 1

At least one valid input arc with a value of 1

2. F·F’R = 0 , F·F’R’ = 0 , F’R·F’R’ =0Only one valid input arc label can have a value of 1



Notation in State GraphNotation in State Graph

Xi.Xj,/Zp.Zq, Xi.Xj,=11, then Zp.Zq,= 11

X1X’4,/Z2.Z3, X1X2X3X4 / Z1Z2Z3Z4

= 1- - 0/0110

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CH14 Derivation of State Graphs and Tablesaccess.ee.ntu.edu.tw/course/logic_design_95first/lecture... · 2010-07-14 · Derivation of State Graphs and Tables ... 13.2 Analysis by