Ch4 Modeling MOS TransistorSPICE 2 17

8/13/2019 Ch4 Modeling MOS TransistorSPICE 2 17

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Chapter 4 Modeling of MOS

Transistors Using SPICE

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SPICE Modeling of MOSFETS

4.1 IntroductionUnderstand the element description for MOSFETs

Understand the meaning and significance of the variousparameters in SPICE model levels 1 through 3 forMOSFETs

Understand the basic capacitance models

Have a general notion of BSIM model parameters

Become award of some newer models

Understand the use and shortcomings of the models covered

Note: In the following, HSPICE = Star-HSPICE

References

Massobrio, G., and P. Antognetti, Semiconductor Device Modeling withSPICE, 2nd Edition, McGraw-Hill, 1993.

Foty, D., MOSFET Modeling with SPICE Principles and Practice,Prentice Hall PTR, 1997.

StarHspice Manual, Avant!


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MOSFET element description and .MODEL statements

M1 3 1 0 0 NMOD L=1U W=10U AD=120P PD=42U

MDEV32 14 9 12 5 PMOD L=1.2U W=20U

.MODEL NMOD NMOS (LEVEL=1 VTO=1.4

+ KP=4.5E-5 CBD=5PF CBS=2PF)

.MODEL PMOD PMOS (VTO=-2 KP=3.0E-5+ LAMBDA=0.02 GAMMA=0.4 CBD=4PF CBS=2PF

+ RD=5 RS=3 CGDO=1PF CGSO=1PF CGBO=1PF)

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1.2 micron CMOS model (Level 3) NMOS

.MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-

08 XJ=0.200000U +TPG=1 VTO=0.7860 DELTA=6.9670E-01

LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02

RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16

NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02

+KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10

+CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10

+MJSW=0.125195 PB=0.800000PMOS

.MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-

08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00

LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01

RSH=1.0470E+02 GAMMA=0.4863 +NSUB=1.8900E+16

NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01

+KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11

+CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10

+MJSW=0.217168 PB=0.850000


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4.2 Basic Concepts


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The MOSFET Description Lines

Model and Element (1/2)

What does SPICE stand for?Simulation Program with Integrated Circuit Emphasis

The MOSFET Model and Element Description Lines

Process and circuit parameters which apply to a particular class

of MOSFETS with varying dimensions are described for that

class of MOSFETS in a single .model line in which + is used to

denote line continuation.

The dimensions are given on the element description line. In

both, it is critical to watch the units; they are basically illogical!

The SPICE element description line for a MOSFET has the

following form: Mxxxxxxx nd ng ns mname

All parameter value pairs between are optional.

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The MOSFET Description Lines

Model and Element (2/2)

Additional optional HSPICE parameters:

TEMP=val is not used on element line in HSPICE

and not used for level 4 or 5 (BSIM) models.


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Equations

VT Equation as derived previously

ID Equations as derived previously with linear mode equationtimes (1+VDS) for continuity across linear-saturation boundary.Both use Leffin place of L where:

Leff= L 2 LD

Key Parameters: What do they represent? See Kang andLeblebici Table 4.1

NMOS, PMOS (obvious) MOSFET channel type

KP process transconductance k

VTO (note O, not 0!) zero substrate-bias threshold voltage VT0

GAMMA substrate-bias or body-effect coefficient

PHI twice the Fermi potential 2FLAMBDA channel length modulation

DC SPICE Models: Level 1 (Shichman-Hodges) DC Model (1/2)

4.3 The Level 1 Model Equations

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DC SPICE Models: Level 1 (2/2)

Additional Parameters: What do they represent?

LD Lateral diffusion (If not present, may need to find Leffmanually!)

TPG Type of gate material: 0 A1, +1 opposite to substrate, -1 same as substrate. Default +1. For the typical CMOS process, TPG = 1 for

NMOS and 1 for PMOS

NSUB substrate impurity concentration NA (NMOS) ND (PMOS)

NSS Surface state density Used to define surface component of VT0.

TOX Oxide thicknesstox

U0 (note 0, not O) Surface mobility 0

RD, RS Drain resistance, Source resistance

RSH Drain and Source sheet resistance (/) Derived Parameters.Note that if some parameters missing, others, if

present, can be used to derive them. E. g. NSUB to derive PHI, and TOXand U0 to derive KP. Question: What parameters to derive GAMMA? If thederivable parameters are present in the model, they will be used; if not,derived if possible from other parameters (and defaults), else, defined.


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DC SPICE Models: Level 2 (1/2)What about defaults and units? See Table 4.1. of Kang and

Leblebici

Other parameters in Level 1 are related to capacitance (later) orirrelevant to digital applications.

Level 2Analytical model that takes into account small geometry effects.

Equations that use most of the parameters are given in the text.

Parameters in addition to those for Level 1:

NFS - Fast surface state density Used in modeling subthreshold condition.

NEFF Total channel charge coefficient Empirical fitting factor multipliedtimes NSUB in the calculation of the short channel effect. Used onlyin Level 2.

XJ Junction depth of source and drain.

VMAX Maximum drift velocity for carriers use for modeling velocitysaturation.

DELTA Channel width effect on VT.

4.4 The Level 2 Model Equations

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XQC Coefficient of channel charge share. Used to specify

the portion of the channel charge attributed to the drain. Also,

more importantly causes the Ward capacitive model to

replace the Myer capacitance model. Both have their

disadvantages.

Next three parameters produce a multiplicative surface

mobility degradation factor to multiply times KP and appearin Level 2 only.

UCRIT Critical electric field for mobility degradation.

UEXP Exponent coefficient for mobility degradation.

UTRA Transverse field coefficient for mobility degradation.

Coefficient of VDS in denominator of the factor.

See Table 4.1. of Kang and Leblebici.


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Equations

VT Equation as derived previously

ID Equations as derived previously with linear mode equationtimes (1+VDS) for continuity across linear-saturation boundary.Both use Leffin place of L where:

Leff= L 2 LD

Key Parameters: What do they represent? See Kang andLeblebici Table 4.1

NMOS, PMOS (obvious) MOSFET channel type

KP process transconductance kVTO (note O, not 0!) zero substrate-bias threshold voltage VT0

GAMMA substrate-bias or body-effect coefficient

PHI twice the Fermi potential 2FLAMBDA channel length modulation

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4.5 T Level 3 Model Equations

DC SPICE Models: Level 3

More empirical and less analytical than Level 2; this permits

improved convergence and simpler computation while

sacrificing little accuracy.

The parameters have beyond those in Level 2 (Note that

the following Level 2 parameters are deleted: NEFF,

UCRIT, UEXP, and UTRA.)

KAPPASaturation field factor. An empirical factor in

the equation for the channel length in saturation.ETAstatic feedback on VT. Models effect of VDS on VT,

i.e., DIBL (Drain-Induce Barrier Lowering)

THETAMobility modulation. Models the effect of VGS

on surface mobility.

See Table 4.1 of Kang and Leblebici.

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4.6 State-of-the-Art MOSFET Models

BSIM- Berkeley Short-Channel IGFET Model

EKV(Enz-krummenacher-Vittoz) Transistor Model:

sub-threshold behavior of the transistor

1. A unified view of the transistor operation regions

2. Avoid the the use of disjoint equations in strong

and weak inversion

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4.7 Capacitance Models (1/2)

Level 1 through 3 use the Myer capacitance model (see Kang

and Leblebici Fig.3.32) as the default for the channel

capacitance with the option of the Ward model (see Kang and

Leblebici Fig.4.8) in Levels 2 and 3.

For the source and drain capacitances, note the junction

equation with reverse bias Vwith VT, the thermal voltage,

I=Is(eV/VT-1)=-Is for V-4VTand recall that

Cj =Cj0/(1-V/0)mwherem = 1/2 for an abrupt junction andm = 1/3 for a

graded junction. The parameters:

IS Bulk junction saturation current.

JS Bulk junction saturation current density (used with

junction areas)


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Capacitance Models (2/2)

PB - 0Bulk junction Potential (Built-in voltage)CJ Zero-bias bulk junction capacitance per m2

MJm Bulk junction grading coefficient

CJSW Zero-bias perimeter capacitance per m

MJSWm Perimeter capacitance grading coefficient

FC Bulk junction forward bias coefficient used in evaluating

capacitance under strong forward bias.

CGBO Gate-bulk overlap capacitance per meter of L; should

be set to 0 if modeled as interconnect instead.CGDO Gate-drain overlap capacitance per meter of W

GDSO Gate-source overlap capacitance per meter of W

See Table 4.1. of Kang and Leblebici

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More SPICE Models: BSIM (Level 4)

An empirical model that includes:

all of the typical small geometry effects

the nonuniform doping profile for ion-implanted devices

an automatic parameter extraction program which produces a

consistent set of parameters

L and W for the channelFor BSIM parameters, see Foty Table 8.1

We will not look at these parameters in detail, but it is quite

important to look at the form of the electrical parameters. Each

electrical parametersP is represented by three process parameters

P0, PL, and Pw associated withP

43421321

W

WLW

P

L

DLL

PPP

effeff

WL

+

+= 0


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SPICE Models: BSIM (Cont.)

L and W are drawn dimensions and DL and DW are the net size

changes in the drawn dimensions due to the entire sequence of

fabrication steps. The difference shown give Leffand Weff. The

equation forP allows for an adjustment of the electrical parameter as

a function of the effective length and width of the channel

Parameter extraction uses devices sizes. P0 is for long, wide

MOSFET.

BSIM also uses a new approach to capacitance modeling that avoids

the difficulties of errors and lack of charge conservation in the

Meyer model and the errors and convergence problems in the Ward

model.

See Massobrio and Antognetti p. 219 for trios of parameters.

Note that model file has only numerical values identified by position;

this is an alternate form of the model that cryptic.

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More SPICE Models

HSPICE Level 28, BSIM2, BSIM3

HSPICE Level 13 is BSIM

HSPICE Level 28 - a very popular modification of

BSIM, but can only be used in HSPICE

BSIM2 (HSPICE Level 39) typical model today

for those not using HSPICE BSIM3 Version 3.2 (HSPICE Level 49) a complex

new public domain model that is frequently used

today. This is our model unless otherwise specified.


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Which Model Should We Use?

Level 1: At best, for quick estimates not requiring accuracy. Verypoor for small geometry devices. Viewed as obsolete by some.

Level 2: Due to convergence problems and slow computation rate,abandoned in favor of Level 3 or higher.

Level 3: Good for MOSFET down to about 2 microns.

BSIM Level 4 (HSPICE Level 13): good for small geometryMOSFETS with L down to 1 micron and tox down to 150Angstroms. Problems near Vsat; negative output conductance;discontinuity in current at VT. For submicron dimensions,replaced by BSIM2 and HSPICE Level 28.

BSIM2 (HSPICE Level 39): Good for small geometry MOSFETswith L down to 0.2 micron and tox down to 36 Angstroms.

HSPICE Level 28: BSIM with its problems solved; good choicefor HSPICE users.

BSIM3 Version 3 (HSPICE Level 49): Most accurate, butcomplex.

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4.8 Comparison of the SPICE MOSFET Models


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Summary

Learned the element description line for MOSFET

Reviewed the first generation SPICE model

parameters, levels 1, 2, and 3

Reviewed the device capacitances and associated

parameters for the BSIM model

Obtained a sense of the form of the parameters for

the BSIM model

Obtained an awareness of some of the newer

models

Obtained a comparative viewpoint of the models

and their use.

Documents

Ch4 Modeling MOS TransistorSPICE 2 17