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Chapter 5: Combination Logic
Shi-Huang Chen
Fall 2010
樹德科技大學 資訊工程系
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Outline
Basic Combinational Logic CircuitImplementing Combinational LogicThe Universal Property of NAND and NOR GatesCombinational Logic Using NAND and NOR GatesLogic Circuit Operation with Pulse Waveforms
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Circuits (1)
In Sum-of-Products (SOP) form, basic combinational circuits can be directly implemented with AND-OR combinations if the necessary complement terms are available.
JKJ
K
A
BAB
Product terms
Sum-of-products
Product term
C
D
CD
AB + CD + + JK. . .
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Circuits (2)
An example of an SOP implementation is shown. The SOP expression is an AND-OR combination of the input variables and the appropriate complements.
SOP
DE
ABCABC
E
D
X = ABC + DE
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Circuits (3)
Level sensor
1: Empty
0: Normal
Ringing when the level in any two of the tanks empty
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Exclusive-OR logic
The truth table for an exclusive-OR gate is
A
B
OutputInputsA B X0011
0101
0110
Notice that the output is HIGH whenever A and B disagree.The Boolean expression is
The circuit can be drawn as
X = 1
Symbols:
Distinctive shape Rectangular outline
X = AB + AB
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Exclusive-NOR logic
The truth table for an exclusive-NOR gate is
A
B
Notice that the output is HIGH whenever A and B agree.The Boolean expression is
The circuit can be drawn as
XSymbols:
Distinctive shape Rectangular outline
OutputInputsA B X0011
0101
1001
= 1
X = AB + AB
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Example
For each circuit, determine if the LED should be on or off.+5.0 V
+5.0 V
330 Ω
LEDB
A
+5.0 V+5.0 V
330 Ω
LEDB
A
+5.0 V+5.0 V
330 Ω
LEDB
A
(a) (b) (c)
Circuit (a): XOR, inputs agree, output is LOW, LED is ON.Circuit (b): XNOR, inputs disagree, output is LOW, LED is ON.Circuit (c): XOR, inputs disagree, output is HIGH, LED is OFF.
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Implementing Combinational Logic (1)
Implementing a SOP expression is done by first forming the AND terms; then the terms are ORed together.
Show the circuit that will implement the Boolean expression X = ABC + ABD + BDE. (Assume that the variables and their complements are available.)
C
AB
EDB
ABD
Start by forming the terms using three 3-input AND gates.Then combine the three terms using a 3-input OR gate.
X = ABC + ABD + BDE
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Implementing Combinational Logic (2)
For basic combinational logic circuits, the Karnaugh map can be read and the circuit drawn as a minimum SOP.
A Karnaugh map is drawn from a truth table. Read the minimum SOP expression and draw the circuit.
1. Group the 1’s into two overlapping groups as indicated.
2. Read each group by eliminating any variable that changes across a boundary.
C C
AB
AB
AB
AB
1
1 1
C C
AB
AB
AB
AB
1
1 1B changes across this boundary
C changes across this boundary
3. The vertical group is read AC.
4. The horizontal group is read AB.
The circuit is on the next slide:
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Implementing Combinational Logic (3)
Circuit:CA
A
CA + A B
continued…
X =
The result is shown as a sum of products.
It is a simple matter to implement this form using only NAND gates as shown in the text and following example.
B
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
NAND Logic
Convert the circuit in the previous example to one that uses only NAND gates.
Recall from Boolean algebra that double inversion cancels. By adding inverting bubbles to above circuit, it is easily converted to NAND gates:
CA
B
A
CA + A BX =
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Universal Property of NAND and NOR Gates (1)
The NANDNAND and NORNOR gate are universal gates because they can produce ANDs ORs and NOTs.
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Universal Property of NAND and NOR Gates (2)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Universal Property of NAND and NOR Gates (3)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Universal Property of NAND and NOR Gates (4)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Why use universal gates?
IC are packaged with 4 gates per chip buy only NAND IC and save lots of money on inventory. One type of chip for all logic applications.
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NAND Gates (1)
Recall from DeMorgan’s theorem that AB = A + B. By using equivalent symbols, it is simpler to read the logic of SOP forms. The earlier example shows the idea:
CA
B
A
CA + A BX =
The logic is easy to read if you (mentally) cancel the two connected bubbles on a line.
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NAND Gates (2)
NAND logic for X = AB + CD.
CDABDCBADCBA
DCBACDABX
+=+=+++=
++==
)()(
))(())((
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NAND Gates (3)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NAND Gates (4)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NAND Gates (5)
)()( FDECABX =
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NOR Gates (1)
B
A
C
A
X =
Again, the logic is easy to read if you cancel the two connected bubbles on a line.
Alternatively, DeMorgan’s theorem can be written as A + B = AB. By using equivalent symbols, it is simpler to read the logic of POS forms. For example,
(A + B)(A + C)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NOR Gates (2)
NOR logic for X = (A + B)(C + D).
))(( ))((
DCBADCBA
DCBAX
++=++=
+++=
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NOR Gates (3)
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Combinational Logic Using NOR Gates (4)
)()( FEDCBAX +++++=
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Logic Circuit Operation with Pulse Waveforms (1)
For combinational circuits with pulsed inputs, the output can be predicted by developing intermediate outputs and combining the result. For example, the circuit shown can be analyzed at the outputs of the OR gates:
AB
C
D
A
B
C
D
G1
G2
G3
G1
G2G3
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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University
Logic Circuit Operation with Pulse Waveforms (2)
Alternatively, you can develop the truth table for the circuit and enter 0’s and 1’s on the waveforms. Then read the output from the table.
AB
C
D
A
B
C
D
G1
G2
G3
G3
InputsA B C D
Output
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 1 1 0 0 0
0 0 0 1 1 1 1 0 0 0
0 0 0 0 0 0 0 1 1 0
0 0 0 0 1 1 1 0 1 0
X 0111011100000111