Determination of electrically active traps at the

Determination of

electrically active traps at

the interface of SiC-MIS

capacitors

Den Naturwissenschaftlichen Fakultäten der Friedrich-Alexander-Universität

Erlangen-Nürnberg zur

Erlangung des Doktorgrades

vorgelegt von Florentin Ciobanu

aus Bukarest

Als Dissertation genehmigt von den Naturwissenschaftlichen Fakultäten

der Universität Erlangen-Nürnberg

Tag der mündlichen Prüfung: 13. Dezember 2005 Vorsitzender der Promotionskommission: Prof. Dr. D.-P. Häder Erstberichterstatter: Prof. Dr. M. Schulz Zweitberichterstatter: Prof. Dr. M. Hundhausen

Zusammenfassung Diese Arbeit befasst sich mit der Untersuchung von Störstellen von Metal –

Isolator - Semiconductor (MIS) Strukturen auf SiC Basis.

Die Rolle des Wasserstoffs H (Proton) im Oxid von MOS Kondensatoren

wurde systematisch untersucht. Thermische SiO2 Schichten auf Si, 4H- und 6H-

SiC wurden mit H implantiert (E ≤ 300 eV). Kapazität - Spannungskennlinien (C-

V) wurden gemessen, um das temperaturabhängige „de-trapping“ von Protonen

zu untersuchen. Der Einfluss der 4H- und 6H-SiC Kristallorientierung auf die

Grenzflächenzustandsdichte Dit wurde untersucht. Der Einfluss von Stickstoff N

auf Dit von 4H-, 6H- und 3C-SiC/SiO2 MOS Kondensatoren wurde untersucht. Die

Implantation von N-Atomen mit anschließender Überoxidation des implantierten

SiC-Bereiches wurde beschrieben und untersucht.

Dit von MIS Strukturen mit „high-κ“ Dielektrika wie HfO2 und Al2O3 auf SiC

wurde analysiert. Die Ergebnisse der vorliegenden Arbeit sind im Folgenden

zusammengefasst.

Oxidstörstellen

- Positiv geladene Oxidstörstellen werden von H-Atomen (Proton)

verursacht. Diese Arbeit demonstriert die Lokalisierung von getrappten

Protonen sowohl im Volumen des Oxids als auch an der SiC/SiO2

Grenzfläche.

- Die Ätzrate des Oxids in HF-Säure wird verstärkt auf Grund des von

positiv geladenen Protonen verursachten elektrisches Feldes;

retch = 0,75 nm/s.

- Die Bindungsenergie von Protonen im SiO2 ist:

Ea = 1,5 ± 0,2 eV

für thermische Oxide auf Si und 4H-/6H-SiC. Diese Bindungsenergie

entspricht der thermischen Aktivierungsenergie von im Oxid getrappten

Löchern, die vom Si-Substrat injiziert wurden [Fuj-01].

- Wasserstoff wurde von der Oxidschicht schnell und effektiv bei

Temperaturen größer als 450 K entfernt. Danach ist ein stabiler Betreib

des SiC-MOSFETs bei T > 450 K möglich.

I

II

- Dit bei 4H / 6H-SiC MOS Kondensatoren hängt ab von der Orientierung

des Substrates und steigt in der Folge:

Si-face < a-plane < C-face.

Schnelle Oxidation ruft die Bildung von Kohlenstoffpräzipitaten an der

Grenzfläche hervor.

- Die hohe Konzentration von „Near Interface Traps (NITs)“ nahe der

Leitungsbandkante EC von 4H-SiC erzeugt eine große Hysteresis von

C-V Kennlinien und eine starke Temperaturabhängigkeit der

Flachbandspannung, besonders bei T < 200 K.

Stickstoff an der 4H-SiC/SiO2 Grenzfläche

- Stickstoff, eingeführt an der 4H-SiC/SiO2 Grenzfläche durch

Behandlung des SiC Kristalls in NO oder N2O Atmosphäre bei hohen

Temperaturen, führt zu einer Reduzierung der NITs und

Kohlenstoffpräzipitate.

- NO-Oxidierung reduziert die NITs.

- N2O spaltet in NO und atomaren Sauerstoff bei hohen Temperaturen

auf. Ein Wettbewerb zwischen NO - induziertem Abbau von NITs und

Sauerstoff-Induziertem Aufbau von NITs findet statt. Der hochreaktive

Sauerstoff wirkt effektiv auf den Abbau der Kohlenstoffpräzipitate.

Stickstoff an der 3C-SiC/SiO2 Grenzfläche

- NO-Oxidation baut Dit in der ganzen 3C-SiC Bandlücke ab.

- UV Bestrahlung (hν = 10 eV) zusammen mit NO-Oxidation führt zur

Reduzierung von Dit um zwei Größenordnungen. Es wurde ein Wert

von:

Dit (3C-SiC) ≈ 1011 eV-1 cm-2

nahe der Leitungsbandkante erreicht. Dies macht den 3C-SiC Polytyp

geeignet für MOSFET Anwendungen.

Einfluss einer N-Implantation auf Dit von SiC MOS Kondensatoren

Eine alternative Methode zur Einführung von Stickstoffatomen an der

SiC/SiO2 Grenzfläche ist die Implantation eines N-Gaußprofils und die

III

Überoxidation der implantierten Schicht. Die Ergebnisse dieses Verfahrens für n-

/ p-typ 4H / 6H-SiC MOS Kondensatoren mit Si- oder C-face Orientierung sind:

- N-Implantation erzeugt bei implantierten N-Dosen größer als

DN = 2 x 1012 cm-2 eine positive Oxidladung QFC. Etwa zehn

implantierte N-Atome sind erforderlich um eine positive Oxidladung zu

erzeugen.

- Die Anwesenheit des Stickstoffes an der SiC/SiO2 Grenzfläche führt zu

einer Temperaturunabhängigkeit der Flachbandspannung UFB.

- N-Implantation ergibt:

Dit (3C-SiC) = (1010 - 1011) eV-1 cm-2

im oberen Energiebereich der Bandlücke

Eit – EV = (3,2 eV – 2,6 eV).

Dies weist auf eine komplette Eliminierung der NITs hin,

möglicherweise durch eine mehr kompakte Struktur des nitrierten

Oxids und durch eine reduzierte Fehlanpassung der Gitterkonstante zwischen SiC und SiO2.

- N-Implantation führt zum Anstieg von Dit nahe der Valenzbandkante EV.

- Es wurde ein mittlerer Abstand zwischen einem Elektronenzustand und

einem N-Donator von

de-N = (0,15 nm – 0,4 nm)

abgeschätzt. Dies deutet darauf hin, dass die positiv geladenen N -

Donatoren sich inerrhalb der Kohlenstoffpräzipitate befinden. Die

Coulombwechselwirkung schiebt die Elektronenzustände bedingt

durch die Kohlenstoffpräzipitate zu tieferen Energien und könnte als

Folge erklären, dass Dit nahe der Leitungsbandkante EC reduziert wird

und nahe der Valenzbandkante EV von SiC ansteigt.

High-κ Dielektrika: 4H-SiC/SiO2/HfO2 Stapel

- Stapel von 4H-SiC/NO-Oxynitride/HfO2 MIS Kondensatoren wurden

untersucht. Der Beitrag der Kohlenstoffpräzipitate zu Dit ist proportional

zur Dicke der Oxinitridschicht.

- Eine Oxinitridschicht von 4 nm Dicke ergibt

Dit ~ 1012 eV-1 cm-2

nahe an EC

IV

High-k Dielektrika: Al2O3

- Al2O3/SiC MIS Kondensatoren wurden optimiert durch

Wasserstoffsättigung der SiC - Grenzfläche vor der ALD - Züchtung

und durch Wasserstoffpassivierung der Al2O3/SiC Grenzfläche nach

der Züchtung. Dit nahe bei EC wurde zu

Dit (4H-SiC) ~ 7 x 1011 eV-1 cm-2

bzw.

Dit (6H-SiC) ~ 1 x 1011 eV-1 cm-2

bestimmt.

Contents

Zusammenfassung........................................................................................ I

1. Introduction ......................................................................................... 1

2. The effect of nitrogen on traps at the SiO2/SiC-interface .................... 4

3. Electrical measurements of MOS capacitors ...................................... 7

3.1. Admittance of capacitors.............................................................. 7

3.2. The MOS band-diagram .............................................................. 8

3.2.1. The band-diagram of an ideal MOS capacitor ........................ 10

3.2.2. The real MOS capacitor .......................................................... 12

3.2.3. MOS capacitor in accumulation .............................................. 14

3.2.4. MOS capacitor in depletion..................................................... 15

3.2.5. MOS capacitor in deep depletion / inversion........................... 17

3.3. C-V measurements .................................................................... 19

3.4. Conductance method................................................................. 21

3.4.1. Computation procedure .......................................................... 22

3.4.2. Oxide capacitance and series resistance................................ 24

3.4.3. Doping concentration and flatband bias shift .......................... 24

3.4.4. Density of interface traps and capture cross section .............. 25

3.4.5. Deduction of the trap energy position in the bandgap............. 26

3.4.6. Stretch out due to Dit............................................................... 27

3.5. Admittance spectroscopy........................................................... 27

4. Experimental ..................................................................................... 30

4.1. Sample surface preparation....................................................... 30

4.2. Standard oxidation ..................................................................... 31

4.3. Oxidation in nitrogen oxides....................................................... 32

4.4. Oxidation of N-implanted SiC layers .......................................... 32

4.5. Hydrogen plasma treatment of thermal oxide ............................ 36

4.6. High-k dielectric deposition ........................................................ 36

4.6.1. Stack of HfO2/SiO2/SiC ........................................................... 36

4.6.2. Deposition of Al2O3 ................................................................. 36

4.7. Admittance set-up ...................................................................... 39

i

ii

5. Experimental results ......................................................................... 40

5.1. Proton de-trapping in SiO2 layers .............................................. 40

5.2. CG-V characteristics of 4H- and 6H-SiC MOS capacitors

fabricated by standard process ................................................. 44

5.3. CG-V characteristics of 4H- and 6H-SiC capacitors with

different surface orientation ....................................................... 52

5.4. CG-V characteristics of 3C-SiC MOS capacitors....................... 53

5.5. Effect of N-implantation on the density of interface states......... 56

5.6. CG-V characteristics of high-k dielectric MIS capacitors ........... 67

5.6.1. 4H-SiC/SiO2 (with thin oxides)................................................ 67

5.6.2. 4H-SiC/SiO2/HfO2................................................................... 69

5.6.3. 4H- / 6H-SiC/Al2O3 ................................................................. 71

6. Discussion ........................................................................................ 73

6.1. Oxide traps ................................................................................ 73

6.1.1. Distribution of oxide traps in Si/SiO2 structure ........................ 73

6.1.2. Binding energy of protons trapped in SiO2 ............................. 76

6.1.3. Thermal stability of oxide traps............................................... 79

6.2. Interface state density Dit generated by standard

oxidation process (4H- / 6H-SiC)............................................... 79

6.3. Comparison of Dit in 4H- / 6H-SiC MOS capacitors with

different surface orientation ....................................................... 83

6.4. Process-induced effects on Dit of 3C-SiC MOS

capacitors .................................................................................. 91

6.5. Effect of N-implantation on Dit in n- / p-type 4H- / 6H-SiC

MOS capacitors......................................................................... 93

6.5.1. N-implantation and flatband voltage UFB................................. 94

6.5.2. N-implantation and the density of interface states Dit ............. 97

6.5.3. N-induced Coulomb-interaction ............................................ 102

6.5.4. Dit of C-face p-type SiC MOS capacitors; effect of N-

implantation .......................................................................... 104

6.6. Dit in high-k dielectric MOS capacitors..................................... 111

6.6.1. 4H-SiC/SiO2 (with thin oxides).............................................. 111

6.6.2. 4H-SiC/SiO2/HfO2................................................................. 113

6.6.3. 4H- / 6H-SiC/Al2O3 ............................................................... 114

iii

7. Summary......................................................................................... 117

8. Outlook............................................................................................ 120

Appendix .................................................................................................. 121

A. The solution of the one-dimensional Poisson equation............ 121

B. List of symbols ......................................................................... 124

C. List of used physical constants and material parameter .......... 128

D. Bibliography ............................................................................. 129

E. Publications list ........................................................................ 136

1. Introduction For electronic devices, SiC is an interesting material. Compared to the wide

spread silicon (Si), SiC features improved chemical and physical properties.

Resistance to acids, radiation hardness [MaT-89] and high thermal conductivity

recommends SiC for devices designed to operate in aggressive environments

such as flight engines and nuclear plants. The electrical breakdown field is higher

by a factor of 10 than in Si, which leads to a lower on-resistance in power

devices, reducing losses. The saturation drift velocity of electrons is higher by a

factor of two, which increases the operating frequency with respect to that one

achieved by Si-devices.

The Si processing technology can be applied with minor corrections to SiC

too. The native oxide of SiC is SiO2; at elevated temperatures and in the

presence of O2, SiC oxidizes at the surface resulting in SiO2. This gives

technological advantage compared to other wide bandgap semiconductors, such

as AlGaN or GaN, concerning lateral processing (photolithography, ion

implantation, etc.) and, in addition, for MOS (Metal Oxide Semiconductor) devices

SiO2 is a good insulator having 9 eV bandgap and a dielectric strength of more

than 10 MV/cm.

Thermal oxides of SiC and Si are of similar quality concerning oxide density,

oxide charge or dielectric strength. The density of interface traps Dit of Si/SiO2

and SiC/SiO2 interfaces are, however, strongly different. While the device-

grade Si/SiO2 interface results in Dit values as low as 1010 eV-1cm-2, for n-

type 4H-SiC MOS structures, trap density of 1014 eV-1cm-2 is observed

close to conduction band edge [Sak-02]. The presence of a large amount of

interface traps degrades the quality of MOSFET devices (MOS- field effect

transistor) by capturing charged carriers and by Coulomb scattering. The

reduction of Dit results in an increase of the channel mobility in SiC-MOSFETs.

This work deals with the electrical characterization of SiC-MIS (metal-

insulator-semiconductor) capacitors fabricated with optimized thermal oxidation

procedures and high−κ dielectrics.

In chapter 2 a review of the use of nitrogen in form of NO, N2O and NH3, is

given to improve the oxide properties. One direction of research is concentrated

1

1. Introduction 2

on the post-oxidation annealing (POA) in nitrogen ambient and the other one to

the direct oxidation in nitrogen oxides.

Chapter 3 describes the physics of MOS capacitors and the fundamental

principles to conduct the electrical characterization. The C (capacitance) and G

(conductance) components of the complex admittance Y (section 3.1) behave

differently upon the working regime of the MOS capacitor. The band-diagram

model of an ideal and a real MOS capacitor is presented in section 3.2. The

typical capacitance versus gate bias characteristics (C-V) of a MOS capacitor as

obtained from admittance measurement is described in section 3.3. The

Conductance Method (CM) used to determine the important parameters of the

MOS structure is presented in section 3.4. Finally the principle of Admittance

Spectroscopy (AS) is given in section 3.5.

Chapter 4 presents the experimental details. Firstly the preparation of SiC

crystal surface, prior to oxidation is described. The thermal oxidation procedures

are given in sections 4.2 to 4.4. The hydrogen plasma treatment of the thermal

oxide is described in section 4.5. The energy band off-sets of high−κ insulators

HfO2 and Al2O3 relative to SiO2 are presented in section 4.6. The deposition

details are also given here. Section 4.7 describes the admittance set-up available

at the Institute of Applied Physics in Erlangen.

Chapter 5 contains the experimental results and is divided in four parts. The

first part deals with the effect of protons (hydrogen) on the oxide charge and on

the C-V flatband voltage shift (section 5.1).

The second part is dedicated to the influence of different processing steps to

the C-V and G-V characteristics of thermally oxidized SiC MOS capacitors

(capacitance/conductance versus applied gate bias, CG-V). Polytype-dependent

CG-V characteristics (4H-, 6H- and 3C-SiC) are presented in section 5.2. The

effect of the crystal orientation of the sample and of nitridation process on the

admittance characteristics of the SiC MOS capacitor is presented in section 5.3.

The combined effect of a special surface treatment prior to the oxidation together

with a nitridation process and a proper polytype choice (3C-SiC) on the CG-V

characteristics is described in section 5.4.

The third part presents the admittance investigations (CG-V spectra) of N-

implanted and in-situ N-doped SiC-MOS capacitors (section 5.5).

3

The fourth part presents electrical measurements (CG-V and dc current-

voltage characteristics I-V) performed on SiC-MIS capacitors with the high−κ

dielectrics HfO2 and Al2O3 (section 5.6).

Chapter 6 contains the discussion of results, which are given in chapter 5.

The oxide charge generated by protons is compared with stress experiments

performed in Si-MOS capacitors (section 6.1). The distribution of Dit in the SiC

bandgap generated by standard thermal oxidation of 4H- and 6H-SiC is described

in section 6.2; it consists of dangling bonds, carbon-clusters (the CCM model)

and near-interface traps (NITs). In section 6.3, Dit of 4H- and 6H-SiC MOS

capacitors with different substrate orientation (Si-face, a-plane and C-face) is

compared. In this framework, the influence of a nitridation process using NO and

N2O on fast and slow interface traps is discussed. Process induced effects on Dit

of 3C-SiC MOS capacitors is presented in section 6.4. In section 6.5, the effect of

an N-implantation on Dit of n- / p-type 4H- and 6H-SiC/SiO2 interfaces is

discussed. Section 6.6 presents the properties of Dit in high-κ dielectric (HfO2 and

Al2O3) SiC-MIS capacitors.

Chapter 7 summarizes the experimental results of this work and chapter 8

gives an outlook.

Appendix A gives some mathematical background (Poisson equation),

Appendix B the list of used symbols and Appendix C the list of used physical

constants and SiC material parameters.

2. The effect of nitrogen on traps at the SiO2/SiC-interface

The heart of the modern metal-oxide-semiconductor field effect transistor

(MOSFET) is the Si/SiO2 interface, because of the outstanding intrinsic properties

of SiO2, which include high resistivity (~ 1015 Ω cm), a large bandgap (9 eV) and

high dielectric strength (~ 107 V/cm). Moreover, SiO2 forms a native

(stoichiometric stable) oxide phase with Si resulting in a low interface defect

density.

SiC is the only wide bandgap semiconductor having SiO2 as a native oxide.

The disadvantage of SiC/SiO2 interfaces with respect to the Si/SiO2 interfaces is

the high interface trap density.

The possible origin of the SiC/SiO2 interface traps are:

- dangling bonds, caused by structural misfit between the SiC and SiO2,

also present in Si/SiO2 interfaces,

- carbon clusters [Afa-97, Cha-00, Dha-04] and

- near interface traps (NITs) [Afa-97].

Passivation of the Si/SiO2 interface with hydrogen successfully reduces Dit

by up to two orders of magnitude. The attempt to passivate the SiC/SiO2 interface

using hydrogen does not result in significant improvements. Nitrogen is used in

the Si technology in order to reduce Dit. An increase in the dielectric strength or a

higher resistance to electronic stress is obtained by nitridation of the Si/SiO2

interface [Gre-01].

One of the most important developments in improving the SiC/SiO2 interface

properties is achieved by nitridation of the oxide; first experiments have been

reported by Li et al. [Lih-97]. Nitridation is carried out in NO, N2O or NH3 ambient

either directly during the oxidation process [Lih-00, Jam-01, Ja1-01, Sch-02,

Chu-04], at temperatures ranging from 1100ºC to 1400ºC, or as post-oxidation

annealing at temperatures above 800ºC by exposing the SiC/SiO2 interface to a

nitrogen containing atmosphere (N2, NO, N2O, NH3, etc) [Lih-97, Lih-99, Chu-00,

Jam-01, Ceo-03, Chu-04]. The nitrided oxides are referred to as oxynitrides Si-O-

N, consisting of essentially a SiO2 structure with an averaged concentration of N

4

5

not more than 1%. In a narrow area, e.g. at the interface, the N concentration can

rise up to a maximum of 5-10%.

The bulk phase diagram of the Si-O-N system predicts that N should not

incorporate into the SiO2 film (bulk) at chemical equilibrium as long as an O partial

pressure greater than 10-20 atm is present [Gre-01]. The N-incorporation

throughout the SiO2 bulk by exposing it to NH3 [Don-03, Ch1-00] and the absence

of N from the oxide bulk, when NO and N2O are used, confirm this prediction [Ell-

99, Chu-00, Ja1-01, Don-03, Do1-03, Dha-04].

To explain the N-incorporation at the Si- and SiC/SiO2 interface, at least two

reasons were suggested. One is that N-atoms can be kinetically trapped at the

reaction zone near the interface. In this case N is present in a nonequilibrium

state. Apparently, N reacts only with Si-Si bonds at the interface and not with Si-O

bonds in the SiO2 bulk [Gre-01]. XPS investigations indicate a three-fold

coordinated N≡Si bond at the Si/SiO2 interface [Car-93] and at the SiC/SiO2

interface [Jam-01]. Besides N≡Si, N bonds C atoms in carbon clusters at the

SiC/SiO2 interface [Chu-00, Dha-04].

Alternatively, N at the interface may thermodynamically be stable, due to the

presence of free energy terms not counted in the bulk phase diagram of the Si-O-

N [Gre-01]. N may lower the interface strain existing at the Si/SiO2 interface [Liu-

92]. The present work gives evidence that N reduces the interface strain of the

SiC/SiO2 interface.

A significant reduction of Dit can be achieved by nitridation compared to the

standard oxidation, both in the lower and in the upper part of the SiC bandgap

[Af1-03, Chu-04]. Apparently similar experimental treatment conditions was

reported to result in an increased Dit in the lower part of the SiC bandgap

[Chu-00, Don-03, Do1-03]. The role of nitrogen in reducing traps at the SiC/SiO2

interface is likely a complex one: electrical measurements reveal that nitrogen

affects traps in the SiC bandgap of different chemical origin at the same time.

McDonald et al. [Do1-03] reported a saturation of the passivation of interface

states at a surface nitrogen incorporation of 2.5 x 1014 cm-2. This N content is

comparable with the density of traps in the range of 1014 cm-2 deduced in the n-

channel of a SiC MOSFET [Sak-02]. The authors proposed a model of the

SiC/SiO2 interface in which a continuum of Dit in the SiC bandgap is due to

clusters of different size of excess interfacial carbon or silicon. The main idea of

2. The effect of nitrogen on traps at the SiOB2B/SiC-interface 6

the model is the direct relationship between cluster size and their energy level in

the SiC bandgap. Nitrogen is suggested to dissolve the clusters to a smaller size

(thus smaller trap energy [Afa-97]) by forming strong C≡N or Si≡N bonds. Both

effects lead to a decrease of Dit close to EC and increasing it close to EV.

The strong Si≡N bonds, evidenced by XPY [Jam-01], may relax the strain at

the interface leading to a decrease of NITs and remove open Si and C bonds at

the oxidizing surface. This may be the reason for the reduced oxidation rate

[Ell-99, Ja1-01]. The formation of compact C≡N molecules may hinder the lateral

transport of carbon atoms, necessary to form large carbon clusters [Afa-03].

A consequence of reducing DIT close to EC is the increase of the n-channel

mobility in lateral mode 4H-SiC MOSFETs. Chung et al. demonstrated one order

of magnitude increase of the electron mobility, when the trap density was

decreased by one order of magnitude after NO “re-oxidation” at 1175ºC [Chu-01].

However, the effect of nitridation on the effective electron mobility µeff.e in n-

channel MOSFETs is difficult to interpret due to the important influence of

experimental condition (e.g. composition of nitrogen in the ambient,

contamination induced during oxidation, temperature ramps). A scatter of values

for µeff.e ranging from 112 cm2 V-1 s-1 to 260 cm2 V-1 s-1 for 3C-SiC [Wan-02,

Lee-03] and from 10 cm2 V-1 s-1 to 150 cm2 V-1 s-1 for 4H-SiC MOSFET is

reported in the literature [Sch-02, Óla-04].

Alternatively, nitrogen was incorporated at SiC/SiO2 interfaces by exposing

the structure to plasma of N radicals at a temperature of 600 K [Mae-02]. The n-

channel electron mobility increased with 50% upon the formation of Si-N bonds at

the interface [Yan-03].

In addition to the above-mentioned topics, the oxynitride/SiC device

reliability is improved. For example, a dielectric strength of 12 MV/cm was

reported by NO- [Yan-05] and N2O-nitridated SiC/ SiO2 interfaces [Ól1-04].

All the proposed mechanisms for the passivation of traps at SiC-SiO2

interfaces by a nitridation process are speculative and have to be theoretically

and experimentally clarified. Starting from the early studies of the nitrogen dopant

redistribution during thermal oxidation of SiC, which showed that nitrogen atoms

piled-up at the SiC/SiO2 interface [Pal-89, Nak-96], this work proposes the study

of the redistribution of an implanted Gaussian N-profile of nitrogen in SiC upon

subsequent oxidation.

3. Electrical measurements of MOS capacitors

3.1. Admittance of capacitors

The admittance Y of an ac circuit is defined as the reciprocal value of the

impedance, Z=dU/dI:

dIYdU

= ( 3.1)

a) b)

Fig. 3.1. a) Parallel circuit composed of a capacitor and a resistor supplied with an ac current I and a voltage U. b) Phase-diagram of the current with respect to the applied voltage. IG and IC are the ohmic (real) and capacitive (imaginary) part of the complex I, respectively.

One can simplify the real capacitor as a parallel connection of an ideal

capacitor and an ideal resistor R=1/G (Fig. 3.1). In order to obtain the capacitance

C and the conductance G of the MOS capacitor, we apply a bias:

G acU(t) U U exp(i t)= + ω ( 3.2)

with a small ac amplitude Uac, superimposed to the dc component bias, UG. The

current through the capacitor IC (Fig. 3.1.a) is phase-shifted with π/2 relative to the

voltage U. The over-all circuit current is the vector addition of the capacitive

current IC and the ohmic component IG (see phase diagram of Fig. 3.1.b). The

current is phase-shifted relative to the applied voltage:

0 acI(t) I I exp(i t )= + ω + ϕ ( 3.3)

Using Eq. (3.1), we obtain the admittance, which is a complex quantity:

Y : G i C= + ω ( 3.4)

The real component G (reciprocal value of the device ohmic resistance R) is

determined by the current transport through the device and is due to the energy

losses. For the following, we assume that the conductance of the oxide is

negligible at room temperature (the leakage current through good insulators is

IGϕ

URe

R~

I U

IC IGIC I

C

Im

7

3. Electrical measurements of MOS capacitors 8

usually in the sub-pico Ampere range and can be ignored). Contacts, cables and

semiconductor imperfections contribute to the ohmic component of the

admittance. However, they are systematic and can be compensated. The

contribution of interface traps to G depends on the applied gate bias.

A detailed discussion of the energy loss due to interface traps is given in

section 3.4. In the following, a method is described to achieve the parameters of

MOS capacitors by means of various measurements techniques. Firstly, the

device behavior in different working regimes is depicted.

3.2. The MOS band-diagram

To explain the behavior of a MOS capacitor in an ac circuit, we make use of

an equivalent circuit. Fig. 3.2 shows the serial connection of the oxide dielectric

Cox with a parallel circuit formed by the space charge region capacitance Csc,

interface trap capacitance Cit and the conductance components Gn and Gp, which

take into account the charge exchange of interface traps with the conduction

band (CB) and with the valence band (VB).

Cox Csc

CitGn

Gp

CB

VB

Fig. 3.2. Equivalent circuit of a MOS capacitor. Only one energy level of the interface traps is considered.

For simplicity, Fig. 3.2 considers only one interface trap. In reality, there is a

continuum of states throughout the bandgap. The occupation of these states is

dictated by their relative position to the Fermi level. By applying a gate bias to the

MOS capacitor, the gate charge QG changes with dQG. Allowing the MOS

capacitor to reach the equilibrium, the overall charge neutrality requires that the

change in gate charge dQG to be balanced by a change in the SiC surface charge

QSC and in the interface trap charge Qit. That is:

3.2. The MOS band-diagram 9

G SCdQ dQ dQ .= + it ( 3.5)

The semiconductor band bending changes to compensate the gate bias change.

The relative position of the interface traps to the Fermi level changes and, as a

consequence, also their occupancy. Three distinct regimes can be established:

accumulation, depletion and inversion/deep depletion [Nic67, Sze-81, Bas-01].

The equivalent parallel capacitance Cp of the MOS structure is: 1

pox sc it

1 1CC C C

,−

⎛ ⎞= +⎜ +⎝ ⎠

⎟ ( 3.6)

where the space charge region capacitance Csc is defined as:

SCsc

s

QCψ

=δδ

( 3.7)

and the interface trap capacitance Cit is a function of the surface potential ψs:

itit

s

QCψ

= .δδ

( 3.8)

From the Shockley-Read-Hall statistics (SRH, [Sho-52]), we learn that the

charge exchange between a state located in the bandgap and the conduction or

valence band depends on the response time constant τn or τp. Let us focus on the

interaction with the conduction band. In a quasi-static approximation, the

emission and the capture time constant are equal; they have the form:

C itn

n t,n C

E E1 exp ,v N kT

−⎛τ = ⎜σ ⎝ ⎠⎞⎟ ( 3.9)

where σn is the energy-independent [Sze-81] electron capture cross section, vt,n is

the average thermal velocity of electrons, NC is the density of states in the

conduction band and Eit is the interface trap energy level in the SiC bandgap. The

equation for the time constant of holes is analogous, consisting of the thermal

velocity of holes vt,p, the density of states in valence band NV and the relative trap

energy level with respect to the valence band edge in the exponential (Eit-EV)

(see [Sze-81, or Bas-01]).

Fig. 3.3 plots Eq. (3.9) for an n-type 4H-SiC substrate for NC = 2.2 x 1015

cm-3 K-3/2 (x T3/2) and vt,n = 8.7 x 105 m/s K-1/2 (x T1/2) in a temperature range of

100 to 500 K. The capture cross section σn is assumed to be equal to 10-12 cm-2.

The horizontal dashed lines mark the experimental limitations. Considering the

highest probe frequency of 1 MHz, the fastest time constant, which can be


probed, is 1.6 x 10-7 s. The 20 kHz probing frequency corresponds to a low time

constant limitation of 8.0 x 10-2 s. The bias sweep (as is described in section 3.3)

is 0.1 V/s resulting in an uppermost limitation of 10 s.

n-type 4H-SiC

EC-Eit (eV)0.0 0.5 1.0 1.5 2.0

Tim

e co

nsta

nt (s

)

10-810-710-610-510-410-310-210-1100101102

100K 200K 300K 400K 500K 600K

high limit

low limit

bias sweep - limit

Fig. 3.3. Time constant as a function of the energy position of interface traps in the bandgap.

In the following, a brief discussion is conducted about the behavior of MOS

capacitors in the three working regimes, focusing on the interface trap

contribution to G. For a more detailed explanation, it is recommended to study

[Nic-76, Sze-81 (chapter 7)] or [Bas-01].

3.2.1. The band-diagram of an ideal MOS capacitor

Putting in contact the metal (M) with an insulator (oxide, O) and the

semiconductor (S), charge exchange takes place until thermal equilibrium occurs.

In Fig. 3.4, a one-dimension band-position diagram shows the energy-relevant

information concerning the ideal n-type MOS structure.


qΦM qΦB,M

qχS

EC

EV

EF

Metal Oxide SiC

Vacuum

qΦB

Ei

qΨ(x)

EC,insulator

EV,insulator

d

x

E

Fig. 3.4. Flatband energy diagram of an ideal MOS capacitor. The x-axis corresponds to the depth of the MOS structure; the y-axis represents the energy relative to vacuum energy. EC and EV are the conduction and valence band energy, Ei is the Fermi level of an intrinsic (undoped) semiconductor, Ψ(x) is the potential difference between EF /q and Ei /q (depends on x). χS is the semiconductor electron affinity and ΦB,M, ΦB are the metal-oxide and semiconductor-oxide barrier height, respectively.

When no gate bias is applied, the ideal MOS capacitor is supposed to

respect the following assumptions:

- The electron work-function of the metal (ΦM) and the semiconductor

( +(ESχ C-EF)/q) are equal. Under this condition, the Fermi levels of

the metal and the semiconductor are aligned at equilibrium.

- The semiconductor Fermi level EF is constant from the SiC-bulk

toward the interface. It is determined by the shallow doping (usually

nitrogen N).

- There are no traps at the metal-oxide and oxide-semiconductor

interface. The insulator is free of defects (structural defects,

impurities, vacancies, etc.). The only allowed charge in the structure

exists in the semiconductor and, with opposite sign, in the metal.

- The oxide (insulator) resistivity is infinity (i.e. the current through the

oxide under dc bias is zero).


In the absence of a gate bias the semiconductor band is flat from the bulk to

the interface (flatband situation). Applying a gate bias to the metal, the electric

field attracts charge of opposite sign at the other face of the insulator inducing

accumulation or depletion of semiconductor majority carriers. The Gauss’s law is

reduced in this case to the Poisson equation (see Appendix A). The solution of

the Poisson equation gives the electric field and the potential distribution over the

depth x in the structure (see Fig. 3.4). The electric field is constant in the insulator

and drops linearly in the semiconductor. This corresponds to a linear potential

drop in the oxide and a parabolic potential drop with respect to the depth x in the

semiconductor. The semiconductor bands bend toward, or away from the Fermi

level.

The local potential is defined as the difference between the Fermi level and

the intrinsic Fermi level Ei of the semiconductor at position x:

( ) ( )F ix E E xΨ = − ( 3.10)

Deep in the semiconductor the field is zero and the equilibrium is preserved. At

this point the local potential is called bulk potential, Ψ(bulk) = ΨB. Toward the

interface, it increases parabolically reaching the surface potential Ψ(0) = Ψs (see

e.g. Fig. 3.6). The surface potential influences the space charge in the

semiconductor QSC (see next section) and is determined by the applied gate bias.

Depending on the sign and strength of the gate bias, the MOS capacitor can be

brought in accumulation (section 3.2.3), depletion (section 3.2.4) and deep

depletion and/or inversion (depending on the properties of the semiconductor,

section 3.2.5). These three regimes are called “working regimes” or “situations” in

the following.

3.2.2. The real MOS capacitor

The oxide of a real MOS capacitor features a fixed and mobile oxide charge

Qox; the interface traps feature a fixed (slow) interface trap charge Qfit and a

potential-dependent (fast) trapped interface charge Qit(Ψs). There is also a non-

zero difference between the gate metal and semiconductor work function (Fig.

3.5). The electric fields produced are compensated by a corresponding charge of

the semiconductor. Since the ideal insulator does not conduct any current, the

semiconductor Fermi level remains flat; however, the bands are bending In


compliance with the applied and created fields. To compensate this band bending

and to reach the flatband situation (Ψs = 0), a gate bias has to be applied. This

bias will shift the C-V characteristic of the MOS capacitor. The flatband (Ψs = 0)

situation is reached, when the flatband bias UFB is applied:

( )s

ox fit it s 0FB ms

ox

Q Q QU

CΨ =

+ + Ψ= Φ − . ( 3.11)

The effective charge density at the interface Neff (the second term of Eq. (3.11)) is

obtained from a C-V measurement and has the form:

( ) ( )= ⋅ = − − Φ ⋅ = + + Ψ =eff eff OX FB ms OX ox fit it sN U C U C Q Q Q 0 ( 3.12)

When the interface trap density is high (> 1011 cm-2), the flatband biases for

the opposite sweep directions are different. This difference is called hysteresis:

( ) ( )H FB FBU U acc dep U dep acc .∆ = → − → ( 3.13)

The hysteresis is induced by a certain amount of surface charges ∆NH (density of

hysteresis charge), which change their charge state during the bias sweep:

H H OXN U C∆ = ⋅ .

s.

( 3.14)

The applied gate bias is the sum of the potential drop over the oxide Uox, the

flatband bias UFB and the potential at the SiC surface (surface potential) Ψs:

G ox FBU U U= + + Ψ ( 3.15)

The oxide capacitance corresponds to the accumulated charge at the gate

divided by the potential drop over the oxide: Cox = QG/Uox. In the ideal case, this

charge equals to the space charge of the semiconductor with negative sign

QG = -QSC(Ψs), whereas the space charge of the semiconductor is a function of

the surface potential. All these considerations lead to the following relationship

between the applied gate voltage and the surface potential:


( )SC sG FB

ox

QU U

CΨ

− = − + Ψs. ( 3.16)

The dependence of QSC on Ψs can be deduced by solving the one-

dimensional Poisson equation (see Eq. (A-11) in Appendix A and e.g. p. 367 in

[Sze-81], or [Bas-01]).

Fig. 3.5. Work function of various metals used as gate together with the energy position of the SiC valence and conduction band edge for 4H-, 6H-, 15R- and 3C-SiC.

3.2.3. MOS capacitor in accumulation

For n-type semiconductors, the accumulation can be achieved by applying a

positive bias to the gate. The bottom of the conduction band bends downwards

and approaches the Fermi level at the interface (see Fig. 3.6). The surface

potential ψs is now positive. The carrier density depends exponentially on the

energy difference (EF-EC); the accumulation of electrons (negative charge) at the

interface increases with the bending of the conduction band.

Shallow interface traps are now close to the Fermi level. Their response

time is much faster than the applied ac signal (typically 1 MHz, see Fig. 3.3).

They can follow the ac signal and cause no loss in the device.


The semiconductor space charge depends exponentially on ψs and Csc will

be infinity. Thus, the second term in Eq. (3.6) is negligible. For all practicable

probe frequencies (20 Hz to 1 MHz), the measured parallel capacitance returns

the oxide capacitance Cox:

oxox

ox

ACd

⋅= ,ε ( 3.17)

where dox is the oxide thickness, and A the contact area. This is illustrated in Fig.

3.10 for a bias higher than 1 V.

EC

EF

Ei

EV

-qΨs

EF,M

electronionized donor

Accumulation

oxidemetal n-type SiC (bulk)

(Ψs>0)

UG>0

Fig. 3.6. Band diagram of an n-type MOS capacitor in accumulation.

3.2.4. MOS capacitor in depletion

When the gate bias is pulled toward negative direction, ψs goes through

zero (flatband situation) and then becomes negative (Fig. 3.7).

The time constant of interface traps located close to the Fermi level is now

comparable to the probe frequency, and an energy loss occurs during the charge

exchange with the conduction band. The loss increases the conductance G; the

normalized conductance G/ω goes through a maximum and peaks at a surface

bias, where ωτ=1.98 (see section 3.4.1 and [Nic-67, Nic-82a, Bas-01]). It is worth


to mention that different frequencies will probe states at different energy positions

(see Fig. 3.3).

Once the semiconductor surface is depleted, the charge of the ionized

donors in the space charge region is given by:

SC D scQ qN d= ( 3.18)

and the surface potential results in: 2

D scs

s

qN d .2

ψ = −ε

( 3.19)

EC

EF

Ei

EV

-qΨs

electronionized donor

Depletion

oxide n-type SiC (bulk)

(Ψs<0)

metal

EF,M

UG<0

spacechargeregion

x

Fig. 3.7. Band diagram of an n-type MOS capacitor in depletion.

Eliminating dsc from the Eq. (3.19) and Eq. (3.18), the semiconductor space

charge QSC depends now on the square root of |ψs|:

SC s D sQ 2 qN= ε Ψ . ( 3.20)

The differential capacitance Csc (Eq. (3.7)) depends then on the reverse square

root of |ψs|: 1/ 2

sc SC −∝ Ψ . ( 3.21)

With increasing |ψs| the first term of Eq. (3.6) becomes negligible; the total device

capacitance decreases (see Fig. 3.10 in the bias range of 0 to -2 V).


3.2.5. MOS capacitor in deep depletion / inversion

When the intrinsic energy level at the surface moves over the Fermi level

(Fig. 3.8), the density of minority carriers (holes) at the interface becomes greater

than the density of majority carrier (electrons).

-qΨs

electron

ionized donor

oxide

(|Ψs|>|ΨB|)

spacechargeregion

Deep-depletion / inversion

n-type SiC (bulk)metal

-qΨB

EF,M

UG<0

holedsc

inversion layer

EC

EF

Ei

EV

Fig. 3.8. Band diagram of an n-type MOS capacitor in deep depletion / inversion.

In the case that either the hole generation rate is extremely small or the hole

recombination rate is very large, the density of minority carriers will not overcome

the density of majority carriers at the interface. The device is then in deep

depletion and the extent of the space charge region increases further with

increasing negative gate bias. Introducing Eq. (3.20) in Eq. (3.16), we obtain the

dependence of the applied gate bias on the surface potential:

G FB s s D sox

1U U 2 qNC

− = Ψ − Ψε . ( 3.22)

In contrast, when the hole generation and recombination rates are similar

large, the density of minority carriers (holes) at the interface overcomes the

density of majority carriers (electrons) at the interface. In this case, weak

inversion at the interface is reached. The semiconductor space charge still

depends on the square root of |ψs|, as deduced from Eq. (3.20).


Further increase of the negative gate bias ψs leads to a further increase of

the hole concentration at the interface until it equals the electron concentration in

the semiconductor bulk. At this point, we reach the strong inversion regime. The

strong inversion potential begins at:

Ds B

i

2kT N(inv) 2 ln .q n

⎛ ⎞ψ ≥ ψ = ⎜ ⎟

⎝ ⎠ ( 3.23)

An important parameter in the MOSFET design is the turn-on voltage,

named threshold voltage UT obtained from Eqs. (3.16), (3.20) and (3.23):

( )s D BT FB B

ox

2 qN 2U U 2

Cε ψ

− = + ψ . ( 3.24)

Above this bias, the overall semiconductor charge depends exponentially on

|ψs|, (see Appendix A and e.g. page 368 in [Sze-81]). The space charge region

will not further increase, because the increase in the electrical field is screened by

the large amount of holes attracted at the interface.

Slow alternating ac signals (low frequency) can be followed by the fast

generation and recombination of minority carriers (holes). Consequently the

charge at the interface is proportional to the applied ac bias. At low probe

frequencies, the device shows a capacitance, which is equal to the oxide

capacitance Cox (the solid curve in the negative bias range of Fig. 3.10).

Fast alternating ac signals (high frequency) cannot be followed by

generation and recombination of minority carriers. But the electrons at the end of

the space charge region will follow the ac signal, so Csc determines the total high

frequency capacitance in inversion. If the gate bias sweep is slower than the hole

generation time constant, then an equivalent density of minority carriers (holes) is

generated at the interface, which compensates the change of charge at the gate

contact. The space charge region depth remains consequently unchanged and

the total capacitance scarcely changes (dashed curve or dash-dot-dot curve in

Fig. 3.10).

When the gate bias sweep at high ac probe frequency is faster than the hole

generation and recombination time constant, no inversion charge appears at the

interface. The space charge region depth is then modulated by the gate bias and

the device is in deep depletion. The total device capacitance decreases as Csc

decreases (dotted curve in Fig. 3.10).

3.3. C-V measurements 19

The understanding of the above mentioned working regimes results in a

useful information about the electrical properties. From the capacitance in

accumulation, we obtain the oxide thickness dox. In depletion, we can determine

the density of interface traps Dit, and their energy position Eit. The inversion

regime is not so useful for the electrical investigation of MOS capacitors due to

the coupling of all the generation and recombination processes, which contribute

to only one time constant [Nic-67, Nic-82a].

3.3.

ω

C-V measurements

Equations

G,x ACU(t) U +U exp(i t)= (3.2)

and

)texp(i I I I(t) AC0 ϕ+ω+= (3.3)

describe the applied ac gate bias and the measured current, respectively. In order

to obtain complete C-V characteristics of a MOS capacitor, UG has to be swept in

a staircase fashion (see Fig. 3.9) from a sufficiently negative to a sufficiently

positive bias. In this way, the semiconductor moves from depletion to

accumulation or reverse. UG is swept much slower than the period of the applied

ac signal, T>>2π/ω.

UG(t)

t

UAC

2π/ωT

T >> 2π/ω

1 2 3 x-1 x x+1………

UG(t)

t

UAC

2π/ωT

T >> 2π/ω

1 2 3 x-1 x x+1……… Fig. 3.9. The time dependence of the applied gate bias. T is the integration time at one step x, and ω is the probe frequency.


A schematic plot of the capacitance as a function of the gate bias for an n-

type MOS capacitor is given in Fig. 3.10. For a more detailed description of the C-

V characteristics, it is recommended to study [Sze-81, cap. 7].

The interface trap density Dit can be extracted either from the capacitive

component or from the conductance component of the measured admittance.

Using only C-V measurements, three approaches have been proposed and

extensively reviewed in [Nic-82b]: high frequency method (Terman), low

frequency method and high-low method.

The high frequency method (or Terman method, [Ter-62]) proceeds by

comparing a measured high frequency C-V curve with an ideal C-V curve, where

no interface traps are present. To calculate the theoretical C-V curve, we need to

know the semiconductor doping profile, which is not always the case. For the

reasons explained in [Coo-97], this method is not suitable for wide band-gap

semiconductors. States deeper than 0.6 eV apart from the conduction band edge

(in the case of n-type SiC) can follow neither the probe frequency nor the bias

sweep rate (see Fig. 3.3).

The low frequency method compares the measured low frequency C-V

characteristics with a theoretical capacitance curve, calculated under neglecting

the interface traps [Ber-66]. Again, the calculation of Cs(ψs) is required. Both high-

and low-frequency methods suffer from inaccuracy of assigning the correct

energy position to the measured interface trap density [Nic-82b].

The high-low method [Cas-71] subtracts the contribution of the space

charge to the C-V characteristic at high probe frequency from the sum of both the

space charge contribution and the interface trap contribution at low probe

frequency to the C-V characteristic. It eliminates the need for a theoretical

computation of Csc and for measuring of the doping profile of the semiconductor.

It removes also the inaccuracy in assigning the correct energy position to the

determined Dit. Due to the fact that the subtracted quantities are nearly equal,

round-off errors appear. A complete discussion about errors is given in [Nic-82b].

Both the capacitance and the equivalent parallel conductance contain the

same interface trap information, because they are related to each other by the

Kramers-Kronig relation [Kra-27]. It is more sensitive and accurate to extract the

information related to interface traps (Dit, capture cross section σs and time

3.4. Conductance method 21

constant dispersion τ) by measuring the conductance. The conductance is

directly related to the energy loss provided by the charge exchange between

interface traps and the majority band.

n-type 3C-SiC MOS at 300 K, ND=2.8 x 1016 cm-3, dox=20 nm

U (V)-6 -5 -4 -3 -2 -1 0 1 2

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Cinv

20 Hz10kHz1MHzCS

CFB/Cox

(Ψs=0)

Fig. 3.10. C-V characteristics of an n-type 3C-SiC MOS capacitor. The equivalent ac circuit is described by Eq. (3.6). In accumulation, the infinite Csc (dotted line) cancels the second term of Eq. (3.6). The solid line corresponds to the C-V characteristic at a 20 Hz probing signal. In inversion region, Cinv (dash-dot line) dominates the second term in Eq. (3.6) and cancels it in deep depletion. At low frequencies dashed and dashed-dot-dot lines correspond to the 10 kHz and 1 MHz probing signal, respectively.

3.4. Conductance method

The conductance method was firstly proposed by Nicollian and Brews

[Nic-67]. It describes the relationship between measured admittance of the MOS

capacitor and the interface trap properties. Based on the theoretical introduction

in [Nic-67] and [Nic-82a], an iterative algorithm was developed at the Institute of

Applied Physics, to obtain information about interface traps in a MOS structure

[Bas-01]. The algorithm is described in the following.


3.4.1. Computation procedure

The contribution of interface traps distributed over the semiconductor

bandgap to the admittance is given by [Leh-66, Bas-01]:

( ) ( )2 22 2it it

it

ln 1 arctane D e DY i2 2

+= +

ω τ.

ωτω ωωτ ωτ

( 3.25)

The real part represents the conductance Git and the imaginary part

corresponds to the capacitance Cit:

( )

( )

2 22it it

2it

it

ln 1G e D ,2

arctane DC .2

+=

=

ω τ

ω ωτωτ

ωτ

( 3.26)

The real MOS capacitor features an inhomogeneous distribution of the

semiconductor and oxide charge, electrically active interface traps, together with

roughness and imperfections of the interface. All these facts lead to surface

potential fluctuations. Nicollian and Goetzberger [Nic-67] have considered a

statistical Gaussian fluctuation of the surface potential with standard deviation σs.

The convolution of the admittance (Eq. (3.25)) with this Gaussian distribution

transforms Eqs. (3.26) into:

( )( ) ( )( )

( )

( )( ) ( )( )

( )

222 2sit it2

s ss

2 2sit

it 2s ss

ln 1 exp 2xG e D 1 xexp dx,2 exp x 22

arctan exp xe D 1 xC exp dx,2 exp x 22

+∞

−∞

+∞

−∞

+ ω τ ψ − ⎛ ⎞= −⎜ ⎟

ω ⋅τ ψ − σπ ⋅σ ⎝ ⎠ωτ ψ − ⎛ ⎞

= −⎜ ⎟ωτ ψ − σπ ⋅σ ⎝ ⎠

∫

∫ ( 3.27)

where:

( ) ( )ss

n t ,n D

exp.

v N−βψ

τ ψ =σ

( 3.28)

The following factors contribute to the measured admittance: interface traps

(Git and Cit), the oxide capacitance Cox, the space charge region Csc and the bias-

dependent resistance Rs, which includes the distorting effects of substrate, ohmic

back-side contact, wiring etc.

The equivalent circuit depicted in Fig. 3.11 a) shows the series connection of

the oxide capacitance with the semiconductor. They are connected in series with


Rs. Considering separately the capacitance and conductance one obtains Fig.

3.11 b), where:

p sc it

p it

C C C

G G .

= +

=

, ( 3.29)

Fig. 3.11 c) shows the equivalent parallel circuit of the measured admittance

Ym providing the imaginary part Cm, and the real part Gm. These quantities

correspond to the experimentally measured quantities; they have the form: 2

p

OXpm 2

2p p2

sOXp p

C 1CY

CG C 1R

CY Y

+

=⎛ ⎞ ⎛

+ + +⎜ ⎟ ⎜⎜ ⎟ ⎜⎝ ⎠ ⎝

ω

ωω

2 ,⎞⎟⎟⎠

( 3.30)

p2s

pm 2

2p p2

sOXp p

GR

YG

G C 1RCY Y

⎛ ⎞+⎜ ⎟

⎜ ⎟⎝ ⎠=

⎛ ⎞ ⎛+ + +⎜ ⎟ ⎜

⎜ ⎟ ⎜⎝ ⎠ ⎝

ω

ωω

2 ,⎞⎟⎟⎠

( 3.31)

where 2 22p p pY G Cω= + .

Csc Cit

Cox

Git

Rs

Cp

Cox

Gp

Rs

Cm Gm

a) b) c) Fig. 3.11. Equivalent circuit of a MOS device. a) The capacitance of the insulator Cox is connected in series with the semiconductor and with Rs. The semiconductor consists of a parallel circuit of the interface trap capacitance Cit, the space charge region capacitance Csc and the interface trap conductance Git. b) Simplified circuit of Fig. 3.11 a), considering the transformations of Eq. (3.29). c) Scheme of measured admittance components, capacitance Cm (Eq. (3.30)) and conductance Gm (Eq. (3.31)).

The extraction of information from the measured admittance Ym is based on

a step-by-step procedure. The measured admittance is transformed into


capacitance and conductance components (C-V and G/ω-V plots). In the following

the steps are sketched how to acquire information about the electrical

characteristics of the MOS capacitor.

3.4.2. Oxide capacitance and series resistance

From the admittance behavior in accumulation one can estimate Cox and Rs.

For the reasons explained in section 3.2.1, the interface states do not change

their occupancy with the ac signal and consequently Cit and Git in Eq. (3.29) can

be cancelled. In the scheme of Fig. 3.11 a) only the series connection of Cox with

Csc and Rs remains.

In section 3.2.1, it was explained that Csc is infinity in accumulation.

Consequently the measured device impedance contains only the oxide

capacitance and the serial resistance.

Under this condition, the accumulation circuit impedance is

Zacc = Rs+1/iωCox and the measured admittance is Ym,acc = Gm,acc+iωCm,acc. As the

impedance is the inverse of the admittance, it follows:

m,acc

m,acc

m,accs 2 22

m,acc

2 2m,acc

ox 2m,acc

GR ,

G C

G CC .

C

=+ ω

+ ω=

ω

2 ( 3.32)

From Cox, we obtain the oxide thickness dox by using the handbook formula

for a plate capacitor with gate contact area A and the dielectric constant εox (see

section 3.2.3):

oxox

ox

AdCε

= . (3.17)

3.4.3. Doping concentration and flatband bias shift

MOS capacitors based on the wide band semiconductor SiC feature the

deep depletion regime by appropriate biasing. As in Appendix A deduced, the

space charge region capacitance in deep depletion has the form:


( )s

s

ssc s

d,n s

A eC sgn2 L e 1

βΨ

βΨ

ε= Ψ

⋅1−

− βΨ − ( 3.33)

and with Eq. (3.16), the relationship between applied gate bias and surface

potential, is as follows:

( ) ( )sG s s s

d,n ox

2U sgn exp 1L Cε

= ψ βψ − βψ − + ψβ s FBU ,+ ( 3.34)

where β = e/kT, LD,n is the extrinsic Debye length for electrons defined as:

sD,n

D

LqN

ε=

β ( 3.35)

and ND is the doping concentration of the SiC crystal. Via LD,n both the space

charge capacitance and the UG = f(Ψs) relationship depend on the ND.

Eq. (3.34) is calculated by using a nested interval procedure, which results

in the relationship between Ψs and UG. Inserting this result into Eqs. (3.33), (3.29)

and (3.30), the “theoretical” device capacitance Cth versus UG is obtained

(Cth = f(UG)).

The extraction of the information on ND and UFB is conducted by an

iteratively fitting procedure of the calculated C-V characteristics (Cth = f(UG)) to

the experimental one (Cm = f(UG)) (see [Bas-01]).

3.4.4. Density of interface traps and capture cross section

The density of interface traps Dit and the electron capture cross section σn

are extracted again by an the iterative process of fitting the theoretical G-V

characteristics (Gth = f(UG)) to the measured G-V curve (Gm = f(UG)). The

dependence of the surface potential upon gate bias (section 3.4.3) together with

Eqs. (3.27), (3.29) and (3.31) leads to the determination of Gth = f(Ψs).

Dit, the standard surface potential deviation σs and the electron capture

cross section σn are iteratively introduced in order to obtain the best fit of the

experimental curve. As explained in [Bas-01], Dit is proportional to the G-V peak

height. σs influences the peak width and the stretch-out of the C-V curve. σn shifts

the G-V curve on the x-axis (bias).

Each parameter mentioned above changes the value of Cit. Therefore Cit

has again to be calculated and Gth = f(UG) has also again to be fitted with Eqs.


(3.29) and (3.31). This procedure is repeated until the fitting of the experimental

C-V and G-V curves is optimized.

3.4.5. Deduction of the trap energy position in the bandgap

The Git/ω curve described analytically in the first line of Eq. (3.26) (see

section 3.4.1) has an asymmetric peak form. It peaks at ωτ ≈ 1.98. The G-V peak

maximum is obtained, when the traps with time constants in the range of the

probe frequency are located close to the Fermi level. The energy position of

interface traps is obtained from the following relationship (see Fig. 3.12):

( ) ( )C it C F sE surface E E bulk E q (peak max.).− = − − ⋅ ψ ( 3.36)

In section 3.4.4, the determination of Gth = f(Ψs) is described. Ψs at peak

maximum is introduced in Eq. (3.36), in order to extract the (EC(surface)-EF)

value.

EV

EC

EF

EF,M

Interface Traps

EC(bulk)-EF

EC(surface)-Eit

Eit

qψS

Fig. 3.12. Determination of the energy position of interface traps close to the Fermi level.

Finally the deduced interface trap density is assigned to the corresponding

energy position. To scan a larger energy range in the SiC bandgap, the

temperature has to be varied from 100 K to 650 K and probe frequencies from

100 Hz to 1 MHz are used.

3.5. Admittance spectroscopy 27

3.4.6. Stretch out due to Dit

Eq. (3.5) predicts that when a large amount of interface trap is present, the

dependence between UG and Ψs changes, inducing a stretch out of C-V and G-V

curves. Stretch out means that the same band bending is reached at a larger UG

than when no (or low density of) interface trap is present.

A quantitative treatment of stretch out follows from Eq. (3.5):

( ) ( ) ( )ox G s it s SC sC U Q Q− Ψ = Ψ + Ψ . ( 3.37)

Differentiating and using the Eqs. (3.7) and (3.8), results:

( ) ( )ox G ox it s SC s sC dU C C C d .⎡= + Ψ + Ψ Ψ⎣ ⎤⎦

3.5.

( 3.38)

A wide bandgap semiconductor like SiC does not present C-V and G-V

characteristics stretched out over the entire band bending from accumulation to

deep depletion. Interface states energetically located deeper than 0.7 eV in the

bandgap (see dotted curve of Fig. 3.3) cannot follow the gate bias sweep

irrespective of the probe frequency. Starting from this point toward deep depletion

the C-V curve resembles the one of an ideal MOS capacitor. The surface

potential (band bending) corresponding to this point is further called surface

potential limit for stretch out Ψst, max.

Admittance spectroscopy

Admittance spectroscopy (AS) is a temperature dependent small signal

method, where the dc gate bias component UG is kept constant during the

temperature scan. By means of UG, the MOS device can be biased in any of the

working regimes described in section 3.2. The method follows the emission and

capture of charge carriers induced by a small ac component Uac (Eq. (3.2)) with

angular frequency ω.

As mentioned in section 3.2 (Eq. (3.9)), the time constant of an interface trap

located at energy Eit is a temperature-dependent function. For the time constant

of traps with energy ET located in the semiconductor space charge region, a

similar relation is valid as for interface traps:

( ) C Tn

n t,n C

E EgT exp2 v N kT

± −⎛τ = ⎜⋅ σ ⎝ ⎠,⎞

⎟ ( 3.39)

where g± is the degeneracy of the ratio with regard to the occupancy of a positive

to a negative charge state.


Fig. 3.13 represents the temperature-dependent admittance spectra for

three probe frequencies, which are displayed for the real (normalized

conductance vs. T) and imaginary component (capacitance vs. T). With respect to

a certain probe frequency, the states are slow at low temperatures and fast at

high temperatures. The low temperature capacitance is called “high-frequency

capacitance” CHF, while the high temperature capacitance is the “low frequency

capacitance” CLF. The capacitance can be described by:

( ) ( )LF HFHF 2 2

C CC T C

1 ω τ−

= ++

( 3.40)

and the normalized conductance:

( ) ( )LF HF2 2

G T C C.

1− ⋅ ω

=ω + ω τ

τ ( 3.41)

C (p

F)G

/ω (p

F)

CHF

CL F

T

CHF + ∆C/2ω1 ω2 ω3

T1 T2 T3T

Fig. 3.13. C-T and G-T curves obtained from admittance spectroscopy. The probe frequencies are ω1 (dashed line), ω2 (solid line) and ω3 (dash-dot line), ω1 < ω2 < ω3. At ωτ = 1, the capacitance curves have an inflection point and the conductance curves a maximum.

At ωτ = 1, the capacitance curve has an inflection point, and the

conductance curve peaks. The time constant of the trap is obtained from:

3.5. Admittance spectroscopy 29

( )max1Tτ =ω

. ( 3.42)

Activation energy (Ea = EC-ET) and capture cross section (σn) can be

obtained from an Arrhenius plot. The following assumptions have to be taken into

account:

- NC ∝ T3/2;

- vt,n = vt0,n·T1/2 (vt0,n is a temperature-independent term);

- σn = σ0 n·Tα, where σ0 n is temperature-independent and α is an

unknown exponent; its value is assumed to range from 0 (multi-

phonon process) to -2 (cascade process).

Introducing the assumptions made above into Eq. (3.39), we obtain:

( )( )2 C Tmax

E E 1ln T T const.k T

+α −τ ⋅ = ⋅ − ( 3.43)

The variation of the probe frequency in the range from 20 Hz to 1 MHz results in

pairs (τ, T), which are used for the Arrhenius plot. This plot is fitted by a straight

line; its slope gives the activation energy Ea = EC-ET. Its intercept with the y-axis

results in the temperature-independent parameter σ0 n. The error bar in the

determination of the activation energy is largely due to the unknown exponent α.

4. Experimental

4.1. Sample surface preparation

Standard cleaning procedure

Contaminants present on the surface of SiC wafers were removed, prior to

the high temperature oxidation process by using a combination of the “piranha”

process and the RCA method [Ker-70]:

1. de-ionized water (DI) rinse;

2. 1 min ultrasound clean in methanol (dissolving organic adsorbates);

3. DI rinse and oxide strip using a diluted H2O: HF solution (50:1), followed by

DI rinse;

4. piranha clean, H2O:H2SO4:H2O2 = 5:1:1 (exothermic);


DI rinse;

6. removal of insoluble organic contaminants with H2O:H2O2:NH4OH = 5:1:1

at 80ºC;


DI rinse;

8. removal of ionic and heavy metal atomic contaminants using a solution of

H2O:H2O2:HCl = 6:1:1 at 80ºC;


DI rinse.

Before loading the samples into the oxidation furnace, they were dried in a

jet of pure nitrogen. Steps 1 to 9 were performed only for the processing of new

samples. The cleaning procedure for oxidized samples consisted in steps 5 to 9

only (RCA clean).

UV cleaning procedure

The UV procedure was developed at the University of Erlangen with the

purpose to effectively remove graphite-like clusters from SiC surfaces. It consists

on:

1) RCA cleaning,

30

4.2. Standard oxidation 31

2) 24 h exposure to UV light (deuterium lamp, hν ≤ 10 eV) in a reasonably

clean ambient,

3) RCA cleaning.

At the end of each RCA step, the samples were dried in pure nitrogen.

4.2. Standard oxidation

At the Institute of Applied Physics, Erlangen, we performed the “standard”

oxidation in a resistively heated furnace. The oxidation takes place in a quartz

tube (oxidation chamber). The gases are conducted through Teflon pipes to the

oxidation chamber inlet. The chamber outlet can be opened to allow sample load.

Ar flows permanently through the tube in order to keep impurities away from the

furnace wall during the loading and unloading procedure. The tube end, where

the samples are loaded, is located in a flow box to minimize dust contamination.

The furnace tube is resistively heated in three zones, in order to obtain a

constant temperature over a certain region. Each region is controlled using

thermocouples of type S (Pt/RhPt), which feed back the proportional / integral

temperature controllers (PITC) in order to adjust the heating power. The

temperature set-point is the value needed in the middle of the three zones; the

outer zones are adjusted 50ºC above the set-point temperature. Thus, a 40 cm

long region reaches a constant temperature (within ±0.5ºC) in a temperature

range of 1000º to 1200ºC.

The gas supply is designed to allow dry or wet oxidation and post oxidation

annealing (POA). The nominally dry oxidation consists of five steps:

- The sample is loaded at about 630ºC (furnace stand-by

temperature) in inert gas (Ar);

- The temperature is smoothly ramped up (3ºC/min) in Ar, until the

oxidation temperature of 1120ºC is reached;

- oxidation is started by switching on the oxygen (Ar can be switched

off), the oxygen flow is constant over the oxidation time;

- the POA is performed at the same temperature in pure Ar for a

certain time (usually 1 h);

- the temperature is ramped down to the stand-by level of 630ºC and

the sample unloaded.

4. Experimental 32

For the dry oxidation, nominally dry oxygen (99.99998% purity) flows directly

into the furnace. Wet oxidation is realized by bubbling the oxygen or the argon

through a water balloon (DI water). To control the partial pressure of the DI water

vapor, the balloon is heated to 95ºC.

Unless other specified, the oxidation temperature is 1120ºC, oxidation time

is 24 h followed by a post oxidation annealing (POA) for 1 h at the same

temperature and the O2 gas flow rate is 10 l/h.

4.3.

4.4.

Oxidation in nitrogen oxides

Nitric oxide NO and nitrous oxide N2O were used during the oxidation of SiC

samples. An airtight oxidation furnace was used, because the nitrogenous oxides

are toxic [Jam-01, Ce1-03]. This oxidation process was conducted by Prof. Dr.

Sima Dimitrijev, and Dr. Kwan Yew Cheong at Griffith University, Brisbane,

Australia.

The oxidation process was similarly conducted as in Erlangen with two

differences:

- The “NO oxidation” was conducted using an NO atmosphere either

alone during the entire oxidation step or by initiating the oxidation in

pure NO for one hour, then switching to O2 for a limited period, and

finishing the process again in pure NO for the final hour. The

oxidation temperature was 1175ºC. These oxides are called

oxynitrides.

- The “N2O oxidation” was conducted by mixing N2O in N2 in various

concentrations, in a range between 0.5% and 100% (pure N2O).

The oxidation temperature was 1300ºC.

The POA process was performed in N2 at the corresponding oxidation

temperature.

Oxidation of N-implanted SiC layers

The process parameters and a list with the used samples are given in Table

4.2. Except samples marked “_000”, all the residual samples were N-implanted

prior to the oxidation. The implantation was performed at the Institute of Applied

Physics, Erlangen, using a “High Voltage” implanter with energies in the range

(20-350) keV. One set of samples, merked “C30_”, were in-situ N-doped by Dr.

4.4. Oxidation of N-implanted SiC layers 33

Adolf Schöner at ACREO AB (Kista, Sweden). All the samples were exposed to

the standard oxidation process for various times, between 1 h and 24 h. The

samples were exposed to POA at the oxidation temperature for 1 h. The

thickness of the consumed SiC crystal dcons (see Fig. 4.1) is given in Table 4.2.

A scheme of the N-implanted and in-situ N-doped SiC epilayer is presented

in Fig. 4.1. A single N-implantation was performed, aiming a Gaussian N-

distribution close to the surface of the SiC sample. The N+- depth profile was

computed using the TRIM_C software (Transport of Ions in Matter and Cascades,

[Zie-85]). The positions of the peak maximum dpeak are given in.

The “A-“, “B-“ and “C-“ batch of samples are n-type 4H-SiC (0001) epilayers

with a background nitrogen doping of 2⋅1016 cm-3. Batches “A-“ and “B-“ were N-

implanted with doses DN varying between 8 x 1011 cm 2 and 4 x 1013 cm-2. “A”-

samples were not annealed after the implantation. The “B-” samples were

subsequently annealed in Ar at 1500ºC for 30 min.

x

dmax

[N] (cm-3)

N-implanted sampleepilayer:[ND] = 2x1016cm-3

1x1019

x

[N] (cm-3)

5µm

8µmdmax

3x1018

in-situ N-doped sampleepilayer:[ND] = 2x1016cm-3

a)

b)

dcons

x

dmax

[N] (cm-3)

N-implanted sampleepilayer:[ND] = 2x1016cm-3

1x1019

x

[N] (cm-3)

5µm

8µmdmax

3x1018

in-situ N-doped sampleepilayer:[ND] = 2x1016cm-3

a)

b)

dcons

Fig. 4.1. Scheme of N-doped n-type 4H-SiC MOS capacitors: a) N-implanted and b) in-situ N-doped top layer; the dashed straight lines indicate the depth dcons, where the SiO2/SiC interface is established (shaded area is consumed for the oxidation).

4. Experimental 34

Separately the “C”-samples were in situ doped reaching an N concentration

of the top layer (dmax = 30 nm) of 3⋅1018 cm-3. The same oxidation procedure,

however, for 3 h and 22 h, resulted in dox = 25 nm and dox = 86 nm respectively.

The polytype, conduction type and surface orientation of samples “D-“, “E-“,

“F-“, “G-“, “H-“, “J-“ and “K-“ are given in Table 4.1. Samples “_030“ were N-

implanted using the same dose (DN = 1.5 x 1012 cm-2) in order to reach

[N]peak = 3 x 1018 cm-3. The sample D300 was implanted using the dose

DN = 4 x 1013 cm-2 in order to reach [N]peak = 3 x 1019 cm-3.

Table 4.1. List of used conduction types, polytypes and crystal orientations sample series conduction type polytype orientation

A-, B-, C- n 4H (0001) D- p 4H (0001) E- n 4H (000-1) F- p 4H (000-1) G- n 6H (0001) H- p 6H (0001) J- n 6H (000-1) K- p 6H (000-1)

4.4. Oxidation of N-implanted SiC layers 35

Table 4.2. List of used samples and process parameters. N-implantation was performed at an energy of 20 keV (exception: 25 keV to the samples B300 and B30x). The annealing step was performed at 1500ºC for 30 min in Ar

sample conduction type/ polytype / orientation

[N]peak(cm-3) anneal dmax

(nm) dcons(nm)

A000 n-/4H/(0001) not-implanted - - 46 A002 n-/4H/(0001) 2 x 1017 no 30 46 A007 n-/4H/(0001) 7 x 1017 no 30 46 A010 n-/4H/(0001) 1 x 1018 no 30 46 A030 n-/4H/(0001) 3 x 1018 no 30 46 A070 n-/4H/(0001) 7 x 1018 no 30 46 A100 n-/4H/(0001) 1 x 1019 no 30 46 B030 n-/4H/(0001) 3 x 1018 yes 30 46 B070 n-/4H/(0001) 7 x 1018 yes 30 46 B100 n-/4H/(0001) 1 x 1019 yes 30 46 B300 n-/4H/(0001) 3 x 1019 yes 45 45 B30x* n-/4H/(0001) 3 x 1019 yes 45 90 C30a n-/4H/(0001) in situ, 3 x 1018 - 30 12 C30b n-/4H/(0001) in situ, 3 x 1018 - 30 39 D000 p-/4H/(0001) not implanted - 30 46 D030 p-/4H/(0001) 3 x 1018 no 30 46 D300 p-/4H/(0001) 3 x 1019 no 30 46 E000 n-/4H/(000-1) not implanted - 30 46 E030 n-/4H/(000-1) 3 x 1018 no 30 46 F000 p-/4H/(000-1) not implanted - 30 46 F030 p-/4H/(000-1) 3 x 1018 no 30 46 G000 n-/6H/(0001) not implanted - 30 46 G030 n-/6H/(0001) 3 x 1018 no 30 46 H000 p-/6H/(0001) not implanted - 30 46 H030 p-/6H/(0001) 3 x 1018 no 30 46 J000 n-/6H/(000-1) not implanted - 30 46 J030 n-/6H/(000-1) 3 x 1018 no 30 46 K000 p-/6H/(000-1) not implanted - 30 46 K007 p-/6H/(000-1) 7 x 1017 no 30 46 K030 p-/6H/(000-1) 3 x 1018 no 30 46

* Sample B30x was obtained by removing the oxide of sample B300, and re-

oxidizing.

4. Experimental 36

4.5.

4.6.

Hydrogen plasma treatment of thermal oxide

To inject protons into SiO2, a shallow implantation into non-metallized

thermal oxide layers on Si and SiC was performed by Pr. Dr. V Afanas’ev at

University of Leuven Belgium. The protons are injected at an energy Ep < 100 eV

from a hot-cathode ion gun at room temperature. The hot-cathode ion gun allows

minimizing the radiation from the H-plasma because of a low gas pressure (10-2

torr). The density of implanted ions was determined by monitoring the target

current (with accuracy better than 5%). Implanted ion doses of up to ~1014 cm-2

were achieved. For comparison, a high dose of H+ of ~1018 cm-2 was implanted at

higher energy of Ep < 300 eV.

13 nm thick Au electrodes of 0.5 mm2 area were evaporated onto the oxide,

to fabricate metal-oxide-semiconductor (MOS) capacitors. The trapped charge

density was determined from the shift of the flatband voltage (UFB) of C-V curves

(1 MHz).

High-k dielectric deposition

4.6.1. Stack of HfO2/SiO2/SiC

The stack formation on SiC was performed by thermally growing an initial

thin (4 to 12 nm) oxynitride at University of Brisbane, Australia (see cap. 4.3)

followed by deposition of HfO2 at 400°C with the nitrate-precursor Hf(NO3)4. This

precursor contains no carbon, which might degrade the interface quality.

Moreover, there is no hydrogen-containing species, which could damage the thin

SiO2 interlayer grown on SiC prior to the HfO2 deposition. The HfO2 deposition

was conducted by Pr. Dr. S.A. Campbell at the University of Minnesota,

Minneapolis USA.

Hafnium oxide exhibits a large dielectric constant (κ = 20), but has an

energy bandgap of only 5.6 eV (see Fig. 4.2). The band offsets of 4H-SiC with

respect to SiO2 are 2.7 eV and 3.0 eV for EC and EV, respectively. With respect to

HfO2, however, the corresponding band offsets of 4H-SiC are 1.6 eV and 0.7 eV.

4.6.2. Deposition of Al2O3

The SiC-MIS capacitors using Al2O3 deposition was fabricated and post-

deposition processed by Pr. Dr. L. Ley, Dr. Th. Seyller and Dr. K. Gao at the

4.6. High-k dielectric deposition 37

University of Erlangen, Germany. Prior to deposition the 4H- and 6H-SiC surface

was exposed to chemical cleaning using the RCA method (section 4.1, as

“cleaning 1” step) and passivation in ultra-pure hydrogen at 1000ºC for 15 min

(“cleaning 2” step) (see [Sie-02]).

Al2O3 is deposited onto the 4H- and 6H-SiC (0001) surface (Si-face) by the

atomic layer deposition process (ALD) from the gas phase of trimethylaluminium

(Al(CH3)3, (TMA)) and water vapor according to the reaction:

3 3 2 2 3 42 Al(CH ) +3 H O Al O +6 CH→ ( 4.1)

The substrate was held at 300°C during the ALD-process. The reaction is

split into two reactions by admitting consecutively TMA and H2O to the substrate

for 1 s each and purging with N2 for 2 s in-between. The deposition conditions are

chosen in such a way that each step leads in a self-limiting reaction to the

deposition of an effective monolayer of Al followed by oxygen atoms. This insures

a complete reaction to Al2O3 and leads to a homogeneous coverage of the

substrate.

9.0 eV

3.0 eV

3.3 eV

2.7 eV

2.3 eV

5.6 eV

1.1 eV

HfO2

SiO2

4H-SiC

EC

EV

Fig. 4.2. Energy offsets of 4H-SiC with respect to HfO2.

The total Al2O3 thickness is a strictly linear function of the number of

deposition cycles. For layer thicknesses between 50 and 200 nm, a growth rate of

0.10 ± 0.01 nm Al2O3 per deposition cycle is determined with the ellipsometry

method.

4. Experimental 38

After ALD a final H-annealing step was performed in ultra-pure hydrogen at

500ºC for 30 min. Gold contacts have been used. The nomenclature of the

samples and their description is given in Table 4.3.

Table 4.3. List of used samples and the preparation steps

sample description RCA4 RCA6 H-te4 H-te6 H6Hp

polytype 4H 6H 4H 6H 6H

cleaning 1 RCA RCA RCA RCA RCA

cleaning 2 H-passivation

H-passivation

H-passivation

insulator deposition Al2O3 Al2O3 Al2O3 Al2O3 Al2O3

post-deposition process - - - -

H-annealing T = 500ºC, t = 30 min

The aluminum oxide exhibits a large dielectric constant (κ ≈ 9) and an

energy bandgap of 7 eV. There is an energy off-set of 1.5 eV between the

conduction band edges of 4H-SiC and Al2O3 [Gao-03]. The conduction band

offset between 6H-SiC and Al2O3 is 1.8 eV (see Fig. 4.3).

7.0 eV

2.2 eV

3.3 eV

1.5 eV

2.2 eV

3.0 eV

1.8 eV

6H-SiC

Al2O3

4H-SiC

EC

EV

Fig. 4.3. Energy offsets of 4H- and 6H-SiC with respect to Al2O3. (After Gao et al. [Gao-03].)

4.7. Admittance set-up 39

4.7. Admittance set-up

The differential admittance was determined using the four-terminal pair

configuration of an LCR meter (HP 4284 A). The bias voltage ranges between

-40 V and +40 V. The probe frequency ranges between 20 Hz and 1 MHz and the

amplitude of the ac signal can be continuously adjusted from 5 mV to 2 V. The I-V

characteristics are acquired using a Keithley 6517 electrometer working in the

bias voltage range of ±100 V with a resolution of 0.2 pA. The two measurement

systems are coupled to the sample through an HP3488A switch control unit.

The samples are fixed in a sample holder by a platinum ball (Ø = 5 mm),

which is pressed on the gate contact by springs. A metal plate insures the back

side contact and simultaneously the thermal contact between the sample and the

temperature sensor.

The temperature dependent measurements are conducted in a CryoVac

cryostat in the temperature range from 30 K to 800 K. The cooling fluid was liquid

helium, controlled through an electronic valve. A ThermoCoax coil insured the

adjustable heating. The temperature was measured by means of a PT1000

resistance, supplied with a 10 µA current; the temperature range below 300 K

was calibrated with a Si diode (LakeShore DT-470-SD-13).

The set-up is fully computer-controlled through an IEEE 488 bus. The

operation software was developed under the “TestPoint” environment. The main

tools offered by the software are:

- C-V and G/ω-V (conductance method) measurements with the bias

as variable and ω as parameter at constant temperature;

- C-T and G/ω-T (admittance spectroscopy) measurements with the

frequency as parameter at constant dc bias;

- I-V characteristics at constant T;

- I-T characteristics (TSC) at constant bias,

The temperature can be ramped up and down (maximum ±300 K) or kept

constant (noise: 0.01 K).

5. Experimental results This chapter presents admittance measurements (C-V and G-V

characteristics) taken on SiC MOS structures. Firstly oxide charge effects in SiO2

are presented (section 5.1). The influence caused by the SiC polytype, the crystal

orientation, the oxidation method and implantation on the traps at / or close to the

SiC/SiO2 interface are presented in sections 5.2 to 5.5. Section 5.6 deals with

high−κ dielectrics deposited on SiC.

5.1. Proton de-trapping in SiO2 layers

To study the properties of traps in the thermal oxide, hydrogen ions

(protons) have been implanted into the oxide layer as described in section 4.5.

This work aims to investigate how the protons are spatially distributed in the silica

layer and to deduce the activation energy for thermally-induced de-trapping of

protons.

N-type Si (100) and Si (111) together with 4H- and 6H-SiC substrates were

investigated. The list of samples and the process parameters are given in Table

5.1.

To gain information about the location of implanted protons etch-back

experiments were performed by Pr. Dr. V Afanas’ev at University of Leuven

Belgium on SiO2/Si (100) [Afa-02]. The results are summarized in Fig. 5.1 and

Fig. 6.1. This method consists of time-dependent etching-off the layers from the

H+-implanted thermal oxide. The silica layer was etched using HF solution [HF

(49%):H2O; 1:9 (by volume)] stabilized at 21°C. Afterwards, MOS capacitors were

fabricated and C-V measurements were conducted in Erlangen. The oxide

thickness dox was determined using Eq. (3.17).

Fig. 5.1 shows the remaining oxide thickness as a function of the etching

time for samples Si100100 and Si100300 (see Table 5.1). Two independently

processed Si (100) sets of samples with an approximately 200 nm thick oxide

were implanted with protons at an energy of 100 eV and a dose of 1014 cm-2

(sample Si100100, circles) and at 300 eV and 1018 cm-2 (sample Si100300,

squares), respectively. Within experimental error, the linear fit of the experimental

data of Fig. 5.1 reveals an HF-etch rate retch = 0.77±0.02 nm/s for both samples

Si100100 and Si100300. For comparison, the etch rate of a standard (un-

40

5.1. Proton de-trapping in SiOB2B layers 41

implanted) silica layer reported in the literature [Van-91] of 0.5 nm/s is plotted as

dashed curve.

Etching time (s)

d ox (

nm)

retch=0.77 nm/s

retch=0.5 nm/sstandard oxide

H+ implanted oxideSi100100Si100300exp. fitliterature

200

150

100

50

00 20015010050 250

Fig. 5.1. Oxide thickness as a function of etching time in a HF solution [HF (49%):H2O; 1:9 (by volume)] stabilized at 21°C for Si/SiO2 samples implanted with H+ at an energy of 100 eV with dose of 1014 cm-2 (circles) and at an energy of 300 eV with dose of 1018 cm-2 (squares). The dashed line corresponds to the etching behavior of a non-implanted thermal SiO2 layer, as reported in the literature [Van-91].

Table 5.1. List of H+-implanted samples using 100 eV (dose of 1014 cm-2) or 300 eV proton energy (dose of 1018 cm-2).

H+ energy Sample 100 eV 1014 cm-2 300 eV 1018 cm-2

Si100100 +

Si100300 +

Si111100 +

Si111300 +

4H100 +

4H300 +

6H100 +

6H300 +

5. Experimental results 42

Experiments of thermally-induced proton de-trapping were conducted on n-

type Si/SiO2 samples with (100) or (111) orientation, together with n-type 4H- and

6H-SiC/SiO2 samples with (0001) orientation.

All the H+-implanted MOS samples showed a large negative flatband

voltage, increasing up to -40 V for the 300 eV implanted samples. The

measurement temperature has to be below room temperature for the following

reason: measurements conducted at room temperature (or higher) alter the

experiment, because the gate bias needed to bring the MOS capacitor in

depletion induces a field-assisted thermal emission of protons from the oxide. In

order to separate the thermally-induced de-trapping process from the field-

assisted emission process, no bias was applied during the sample exposure to

high temperatures. The measurement temperature was equal to Tmes = 200 K.

This low temperature prevents the on-set of field-assisted thermal emission of

protons from the oxide, even when a large negative bias is applied in order to

sweep the MOS capacitor from depletion (-40V) to accumulation (+10V).

Tann 1

10 min

TmesC-V

Tsample

time

C-V

Tann 2

C-V C-V

10 min 10 min 10 min Fig. 5.2. Scheme of the measurement sequence: the C-V curve was recorded at Tmes = 200 K, then the sample was heated to Tann for tann = 10 min. Subsequently the sample was cooled again to Tmes and the process was repeated until the flatband voltage of the C-V characteristics did no longer change.

Fig. 5.2 schematically shows the conducted measurement sequence.

Between two subsequent C-V measurements one annealing step is performed.

The annealing step (thermal stimulation of proton de-trapping) consists in heating

the sample to a constant temperature Tann (starting at 380 K) for 10 min. During

the annealing step no bias is applied. The process is repeated until the flatband

voltage of the C-V characteristics does not change anymore (saturation). Then a

higher Tann is chosen (in a range up to 450 K) and the process is repeated until all

5.1. Proton de-trapping in SiOB2B layers 43

the positive charge disappears (flatband voltage recovers to that one of an un-

implanted MOS sample). Annealing temperatures below 380 K result in too slow

proton de-trapping, while above 450 K a very fast annealing of the protons is

induced. The C-V characteristics of samples annealed above 450 K are similar to

the un-implanted reference sample.

Fig. 5.3 shows C-V characteristics of sample 6H100 (n-6H-SiC MOS

capacitor, see Table 5.1) taken at 1 MHz and at different annealing temperatures

Tann of 380 K (a), 400 K (b), 420 K (c) and 440 K (d). The normalized capacitance

Cm/Cox is shown as a function of the gate bias UG. The data was acquired using a

bias sweep from depletion to accumulation (see section 3.3).

n-6H-SiC MOSTann = 380 K

UG (V)-14 -12 -10 -8 -6

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

initial10 min20 min40 min60 min80 min100 min

a)


UG (V)-10 -8 -6 -4

C/C

ox

0.0

0.2

0.4

0.6

0.8

initial10 min20 min40 min60 min80 min100 min

b)


UG (V)-7 -6 -5 -4 -3 -2 -1

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

initial10 min20 min30 min40 min50 min60 min70 min

c)


UG (V)-6 -4 -2 0 2 4 6

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

initial10 min20 min30 min40 min

d)

Fig. 5.3. C-V characteristics of sample 6H100 (see Table 5.1) taken at 200 K. The solid curve is the initial record; the subsequent curves were recorded after successive annealing steps of 10 min at annealing temperature Tann of: a) 380 K, b) 400 K, c) 420 K and d) 440 K.

The C-V characteristics shift towards the positive voltage direction upon

annealing at temperature Tann. This positive shift of the C-V characteristics means

a loss of positive charge, which is attributed to de-trapping of protons from the

oxide. However for each Tann, the positive shift of the flatband voltage saturated


after a certain annealing time (see Fig. 5.3 a, b and c). A next higher Tann was

necessary in order to de-trap the remaining proton amount from the oxide. At

Tann = 440 K (Fig. 5.3 d), the protons de-trapped completely within an annealing

time of 40 min. The C-V characteristics of samples annealed above 450 K were

similar to those of the un-implanted reference sample (not shown).

In section 6.1, the spatial distribution of protons in the silica layer and the

thermal stability of the induced traps are discussed and the activation energy Ea

required for proton de-trapping is determined.

5.2. CG-V characteristics of 4H- and 6H-SiC MOS capacitors

fabricated by standard process

The plot of the MOS capacitance Cm normalized by the oxide capacitance

Cox as a function of the applied gate bias UG is called “C-V characteristics” of the

MOS device (Cm/Cox = f(UG)). Similarly, the plot of the measured conductance Gm

normalized by the angular frequency ω versus the applied gate bias UG is called

“G-V characteristics” of the MOS device (Gm/ω = f(UG)). When both the

conductance and the capacitance characteristics are plotted together, it is

denoted as “CG-V plot”.

Fig. 5.4 depicts CG-V plots of standard-processed n-type samples A00a,

G00a and n3Ca (see Table 5.2) of the polytype 4H- (Si-face), 6H- (Si-face) and

3C-SiC (001), respectively. The probe frequencies are 1 kHz, 10 kHz, 100 kHz

and 1 MHz. The oxidation temperature is 1120ºC. The oxidation time is 24h

(A00a), 20h (G00a) and 30min (n3Ca). The oxide thickness dox of the 4H-, 6H-

and 3C-SiC MOS capacitor is 98 nm, 80 nm and 25 nm, respectively.

The dc component of the bias is swept from depletion to accumulation and

vice-versa (sweep rate 0.1 V/s), in steps of 0.2 V; the ac component has

amplitude of 0.1 V. The direction of the bias sweep is indicated by arrows. The

corresponding scale for C-V and G-V is indicated by the long arrows. Overview

information concerning hysteresis ∆UH (Eq. (3.13)), density of hysteresis charges

∆NH (Eq. (3.14)), flatband shift UFB and the corresponding net-densities of charge

at the interface Neff (defined by Eq. (3.12)) is given in Table 5.2.

5.2. CG-V characteristics of 4H- and 6H-SiC MOS capacitors fabricated by standard process

45

4H-SiCn-type

UG (V)-3 -2 -1 0 1 2 3 4 5

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

Gm

/ω/C

ox

0.00

0.01

0.02

0.03

0.04

0.05

1 kHz10 kHz100 kHz1 MHz

a)

6H-SiCn-type

UG (V)-4 -2 0 2 4

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

Gm

/ω/C

ox

0.00

0.02

0.04

0.06


b)

3C-SiCn-type

UG (V)-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

Gm

/ω/C

ox

0.00

0.01

0.02

0.03

0.04

0.05


c)

Fig. 5.4. CG-V of n-type SiC MOS capacitors as a function of the gate bias for four frequencies. a) n-4H- (sample A00a), b) n-6H-SiC (Si-face) / SiO2 (sample G00a), c) n-3C-SiC (001) / SiO2 (sample n3Ca). The dc bias (superimposed with an ac component of 0.1 V) was swept in both directions. The direction is indicated by arrows; sample temperature was 300 K. The oxide thickness of the MOS capacitors is given in Table 5.2.


At a bias above +3V (+2V for 6H- and -1V for 3C-SiC), the 4H-SiC capacitor

reaches accumulation (see discussion in section 3.2.3 and Fig. 3.10). The

capacitance saturates at a maximum value, which is equal to the oxide

capacitance for low applied frequencies or at a lower value, when high

frequencies are used. This reduction is caused by the bias-dependent serial

resistance (see section 3.4.1 and Eq. (3.30)).

When the bias is negative, the measured capacitance is reduced; the

capacitor passes over to depletion (see description in section 3.4.2 and Fig.

3.10). In the range of +3 V to -1 V (4H-SiC, Fig. 5.4 a), the normalized

conductance Gp/ω passes through a peak. The bias range for the conductance

peak for 6H-SiC is +2 V to -1 V (Fig. 5.4 b) and for 3C-SiC -1.5 V to -3 V (Fig.

5.4 c). The peak height is a direct quantity for the interface state density Dit. The

frequency dispersion of the conductance peak maxima stretches over about 2 V

(4H-SiC, Fig. 5.4 a), 1 V (6H-SiC, Fig. 5.4 b) and 0.6 V (3H-SiC, Fig. 5.4 c) in the

above mentioned probe frequency range.

As the bias moves further to negative values (UG < -3 V), the capacitance

steadily decreases. The capacitors are in deep depletion (see section 3.2.5) and

the charge of the space charge region is dominated by ionized donors.

The hysteresis (difference of the C-V curves taken at opposite sweep

directions) is less than 0.1 V for both the 6H- and 3C-SiC capacitor. This implies a

density of hysteresis charge ∆NH < 1010 cm-2, for both polytypes. The 4H-SiC

polytype presents a hysteresis of 0.2 V corresponding to ∆NH = 4.3 x 1010 cm-2.

The flatband shift due to the “fixed” charge (oxide and deep interface traps)

is (2.4 ± 0.1) V, (1.4 ± 0.1) V, and (-1.5 ± 0.1) V for the 4H-, 6H- and 3C-SiC

capacitor, respectively, corresponding to net-densities of deep states Neff of

-5.1 x 1011 cm-2, -3.7 x 1011 cm-2 and +1.3 x 1012 cm-2.

This kind of CG-V measurement was performed at stabilized temperatures

between 100 K and 500 K, in order to be able to probe the energy positions in the

bandgap between EC-Eit = 0.1 eV - 0.95 eV.

Fig. 5.5 shows a comparison of CG-V plots for p-type 4H- (Si-face), 6H- (Si-

face), and 3C-SiC (001) MOS capacitors (see Table 5.2) taken at 300 K and

ν = 1 kHz. The samples were standard-processed with an oxidation time of 22h


47

(D00a), 22h (H00a) and 30min (p3C001). The oxide thickness dox of the 4H-, 6H-

and 3C-SiC MOS capacitor is 87 nm, 90 nm and 26 nm, respectively.

For the standard processed p-type SiC-MOS capacitors, accumulation is

reached when a negative bias is applied, while depletion and deep depletion

occur when the bias is swept toward positive voltages. The frequency dispersion

shifts the normalized conduction peak maxima toward more negative biases with

increasing frequency meaning that faster ac signals excite shallower states,

which are closer to the SiC valence band (not shown).

p-type SiCT = 300 Kν = 1 kHz

UG (V)-14 -12 -10 -8 -6 -4 -2 0 2 4

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

Gm

/ω/C

ox

0.00

0.02

0.04

0.06

4H6H3C

Fig. 5.5. CG-V of p-type 4H- (Si-face) (D00a, solid), 6H- (Si-face) (H00a, dash-dot) and 3C-SiC (001) (p3C001, dash) MOS capacitor as a function of the gate bias. The dc bias (superimposed with ac amplitude of 0.1 V) was swept in both directions starting in depletion (+5 V). The direction is indicated by arrows. The sample temperature was T =300 K and the probe frequency ν = 1 kHz. The oxide thickness of the MOS capacitors is given in Table 5.2.

The p-type 3C-SiC (dashed curve of Fig. 5.5) goes in inversion for biases

above -1 V. In the same voltage range, the G-V curve increases, indicating

charge exchange at the SiC/SiO2 interface.

The hysteresis of p-type SiC MOS capacitors is larger than in the case of n-

type. The flatband shift is negative and reaches (-6.7 ± 0.1) V, (-6.8 ± 0.1) V, and

(-7.4 ± 0.1) V for the 4H-, 6H- and 3C-SiC MOS capacitor, respectively,

corresponding to net-densities of deep states Neff of +1.4 x 1012 cm-2, +1.6 x 1012

cm-2 and +7.2 x 1012 cm-2 (see Eq. (3.12)).


Table 5.2. C-V relevant parameters ∆UH, ∆NH, UFB and Neff of standard-processed 4H-, 6H- (Si-face) and 3C-SiC MOS capacitors taken at T = 300 K

polytype 4H 6H 3C

cond. type n p n p n p

sample A00a D00a G00a H00a n3Ca p3C001

dox (nm) 98 87 80 90 25 26

∆Uhys (V) 0.2 -4.8 < 0.1 -1.8 < 0.1 -1.0

∆NH (cm-2) -4.3 x 1010 +1.0 x 1012 < -1010 +4.2 x 1011 < -1010 +9.7 x 1011

∆UFB (V) 2.4±0.1 -6.7±0.1 1.4±0.1 -6.8±0.1 -1.5±0.1 -7.4±0.1

Neff (cm-2) -5.1 x 1011 +1.4 x 1012 -3.7 x 1011 +1.6 x 1012 +1.3 x 1012 +7.2 x 1012

• Low temperature C-V characteristics Fig. 5.6 presents C-V curves of an n-type 4H-SiC MOS capacitor fabricated

on the Si-face (0001). The curves are taken at 300 K (virgin record, dotted line)

and at 100 K (circles and triangles). The first sweep at 100 K corresponds to the

circles and the second sweep to the triangles. All the measurements start in

depletion (UG = -10 V); the sweep direction is indicated by arrows. The room

temperature C-V curve shows a hysteresis of 0.2 V corresponding to

∆NH = 4.3 x 1010 cm-2 (similar to sample A00a in Table 5.2). The first record at

100 K shows a different behavior. Starting in depletion the interface states are not

occupied by electrons and far away from the Fermi level. Up to UG = +0.4 V

(Cm/Cox = 0.45), the 100 K C-V curve (circles) is similar to the 300 K one. Above

this gate bias, the states at the interface are faster than the voltage sweep rate

and can capture electrons from the conduction band once they are pushed below

the Fermi level. This leads to the stretch out of the arrow-up C-V curve (circles)

with respect to the dotted curve in the shaded area of Fig. 5.6. Once the

accumulation is reached all the traps are beneath the Fermi level and are

occupied with electrons. A very large concentration of interface states induces the

extremely stretch-out feature of the C-V characteristics: the C-V curve flattens at

a certain value of Cm < Cox never reaching accumulation. An example is shown in

section 5.5.


49

n-type 4H-SiCSi-face (0001)ν = 1 kHz

UG (V)

-10 -8 -6 -4 -2 0 2 4 6 8 10

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0first sweep (100K)seccond sweep (100K)RT (300K)

shift

hysteresis

Fig. 5.6. Subsequent C-V curves taken on an n-type 4H-SiC MOS capacitor at T =100 K and ν = 1 kHz: first sweep (circles) and second sweep (triangles). For comparison, the dotted curve is the virgin record at T = 300 K. The measurements start in depletion (UG = -10 V); the sweep directions are indicated by arrows. The C-V stretch-out of the first run (depletion to accumulation curve) is shaded. The C-V sweep lasts up to 5 min.

Reversing the sweep direction the arrow-down C-V curve (circles) shows a

positive flatband bias shift of 6.5 V with respect to the arrow-up C-V curve

(circles). Subsequent records result in stationary C-V characteristics (triangles in

Fig. 5.6). With respect to the room temperature C-V curve, the depletion to

accumulation C-V wing of the stationary characteristic at 100 K has a flatband

shift due to an additional fixed charge of UAFC = 4.8 V. This indicates an additional

negative fixed charge of NAFC = 1.2 x 1012 cm-2. The hysteresis of the stationary

C-V curve is ∆UH(100 K) = 1.7 V. This indicates that during the sweeps in both

directions (sweep rate 0.14 V/s, total record time equals 5 min) a trap density of

∆NH ≥ 0.4 x 1012 cm-2 changes its charge state.

Heating the n-type 4H-SiC MOS capacitor up again to room temperature the

positive shift is completely removed. The subsequent C-V record results in same

C-V characteristics as the dotted curve of Fig. 5.6 (not shown).


Fig. 5.7 shows the first sweep C-V records (see explanation of Fig. 5.6)

taken at 100 K of n-4H-SiC MOS capacitors, which are oxidized using different

techniques: standard- (solid curve), NO- (dashed curve) or N2O oxidation (section

4.3) (dotted curve). These C-V curves are compared with the C-V record taken at

300 K (grey solid curve) of the NO-oxidized sample. The NO oxidation shows no

flatband voltage shift, no stretch-out and only a small hysteresis of the C-V curve.

Both standard and N2O oxides show C-V stretch-out and an increased hysteresis.

n-type 4H SiCν = 1 kHz

UG (V)-2 0 2 4 6 8

C/C

OX

0.0

0.2

0.4

0.6

0.8

1.0

NO (300K)NO (100K)standard (100K)N2O (100K)

Fig. 5.7. C-V curves taken at T =100 K and ν = 1 kHz of n-type 4H-SiC MOS capacitors providing a standard- (solid curve), NO- (dashed curve) or N2O oxide (dotted curve). A reference C-V curve of the NO-oxidation sample taken at 300 K is given by the solid grey curve.

Relative to 4H-SiC, by the 6H- and 3C-SiC polytypes the low temperature

(T = 100 K) induce smaller flatband voltage shift with respect to the record at

room temperature (RT, T = 300 K). This is shown in Fig. 5.8. The flatband shift for

the n-6H-SiC capacitor due to an additional fixed charge is UAFC = 1.2 V and the

hysteresis is ∆UH(100 K) = 0.2 V (Fig. 5.8 a). The flatband shift of the n-3C-SiC

capacitor due to an additional fixed charge is UAFC = 0.4 V and the hysteresis

∆UH(100 K) is less than 0.1 V (Fig. 5.8 b).


51

n-type 6H-SiCSi-faceν = 1 kHz

UG (V)-4 -2 0 2 4 6

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

100 K300 K

a)

shifthysteresis

n-type 3C-SiCν = 1 kHz

UG (V)-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

100 K300 K

b)

shift

hysteresis = 0

Fig. 5.8. Comparison of C-V curves for n-type SiC MOS capacitors taken at 300 K (dotted line) and 100 K (solid line): a) 6H-SiC Si-face and b) 3C-SiC.

Information on the hysteresis ∆UH and density of hysteresis charge ∆NH of

C-V characteristics taken at 100 K together with the flatband shift with respect to

the C-V curve taken at 300 K UAFC as well as the corresponding additional fixed

charge NAFC for n-type 4H-, 6H- and 3C-SiC MOS capacitors are given in Table

5.3.


Table 5.3. Low temperature (100 K) changes with respect to room temperature C-V characteristics of standard processed n-type 4H- 6H- (Si-face) and 3C-SiC MOS capacitors

polytype 4H 6H 3C

∆UH (V) 1.7 0.2 < 0.1

∆NH (cm-2) 4.2 x 1011 7.9 x 1010 < 1010

UAFC (V) 4.8 1.2 0.4

NAFC (cm-2) 1.2 x 1012 4.8 x 1011 3.6 x 1011

5.3. CG-V characteristics of 4H- and 6H-SiC capacitors with

different surface orientation

Fig. 5.9 shows normalized CG-V curves taken at 100 K using a probe

frequency of 1 kHz for n-type 4H- (a) and 6H-SiC MOS capacitors (b) of different

sample orientation. For comparison, the Si-face (0001), the a-plane (11-20) and

the C-face (000-1) are plotted together.

The samples were cooled down without bias. All the measurements started

in depletion (-10 V) and were swept towards accumulation and vice-versa. The

4H-SiC MOS capacitor shows a hysteresis greater than 4.6 V at T = 100 K (Fig.

5.9 a) corresponding to a negative charge density of ∆NH ≥ 1.1 x 1012 cm-2. The

6H-SiC MOS capacitor shows a marginal hysteresis of 1.2 V corresponding to a

negative charge density of ∆NH ≤ 1.3 x 1011 cm-2.

The increased flatband shift manifested by the C-face (dashed curve) for

both the 4H- and 6H-SiC MOS capacitor indicates the presence of a large

concentration of fixed negative charge (oxide and deep interface traps). The

flatband shift of the C-face 4H- and 6H-SiC MOS capacitor is (14.4±0.1) V and

(9.1±0.1) V, respectively. The calculated net-density of deep states Neff is

4.4 x 1012 cm-2 and 2.7 x 1011 cm-2, respectively.

5.4. CG-V characteristics of 3C-SiC MOS capacitors 53

n-type 4H-SiCT = 100 Kν = 1 kHz

UG (V)-25 -20 -15 -10 -5 0 5 10 15 20 25 30

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

Gm

/ω/C

ox

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07Si-facea-planeC-face

a)

n-type 6H-SiCT = 100 Kν = 1 kHz

UG (V)-10 -5 0 5 10 15

Cm

/Cox

0.0

0.2

0.4

0.6

0.8

1.0

Gm

/ω/C

ox

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

Si-facea-planeC-face

b)

Fig. 5.9. CG-V curves of n-type 4H- (a) and 6H-SiC (b) MOS capacitors taken at T = 100 K and ν = 1 kHz. The orientation of sample surface is (0001) Si-face (solid curve), (11-20) a-plane (dotted curve) or (000-1) C-face (dashed curve).

5.4. CG-V characteristics of 3C-SiC MOS capacitors

Standard processed MOS capacitors realized on an n-type 3C-SiC substrate

from Hoya Advanced Semiconductor Technologies Co. showed a negative flat-

band voltage of the C-V characteristics relative to the theoretical expectations. N-


and p-type epilayers were grown on the Hoya substrate by Dr. Adolf Schöner at

ACREO AB (Kista, Sweden).

Table 5.4. Processing scheme of the n- and p-type 3C-SiC MOS capacitors sample n3Ca n3Cb p3Cc n3Cd / p3Cd n3Ce / p3Ce

UV clean no yes no yes yes epilayer no no yes yes yes

Oxidation standard standard standard standard NO-oxidation

Gate bias (V)

-10 -8 -6 -4 -2 0

C/C

OX

0.00.10.20.30.40.50.60.70.80.91.0

G/ ω

/CO

X (x

10-3

)02468101214

n3Can3Ce

x 20

n-type 3C-SiCMOS capacitorT = 100 K

Fig. 5.10. CG-V characteristics of n-3C-SiC MOS capacitors recorded at 100 K using 0.2 V/s sweep rate. Sample n3Ca (solid curve) consists of a substrate, which is exposed to a standard process, while sample n3Ce consists of an epilayer exposed to an UV cleaning (section 4.1) and an NO oxidation process (section 4.3). The conductance curve of sample n3Ce is 20 times magnified.

Fig. 5.10 shows the CG-V characteristics of samples n3Ca and n3Ce (see

Table 5.4) recorded at 100 K. The UV-cleaning procedure (section 4.1) combined

with NO-oxidation (section 4.3) led to a reduction of the negative flatband voltage

and to a reduction of the conductance peak. The CG-V records were taken at

temperatures between 100 K and 500 K, using probe frequencies of 1 kHz to

5.4. CG-V characteristics of 3C-SiC MOS capacitors 55

1MHz, and sweep rate of 0.2 V/s. The data were analized using the conductance

method ( 3.4).

The admittance spectra (ν = 1 kHz) taken on the O2-oxidized MOS

capacitors p3Cd (solid curves) and on the NO-oxidized MOS structure p3Ce

(dashed curves) are shown in Fig. 5.11. Both conductance spectra show the

peaks Al and RE (described in [Res-03]). These defect centers can also be

observed in the space charge region of a Schottky diode [Pen-03] demonstrating

that they are located in the bulk of SiC. A broad peak X(C) with maximum at

280 K is, in addition, observed in the conductance spectrum of sample p3Cd. In

contrast, peak X(C) is observed neither in Schottky contacts nor in AS spectra

taken in depletion. This demonstrates that the traps causing X(C) are localized at

the interface of the p-type 3C-SiC/SiO2 MOS structure. Peak X(C) is completely

removed, when sample p3Ce is exposed to NO oxidation (see dashed curve in

Fig. 5.11).

Ugate = -26V(accumulation)ν = 1kHz

T (K)100 200 300 400 500

C/C

OX

0.00.20.40.60.81.0

G/ω

/ CO

X

0.0

0.1

0.2

p3Cdp3Ce

AlRE1/2

X(C)

p-type 3C-SiC

Fig. 5.11. Capacitance and conductance of sample p3Cd (solid curve) and p3Ce (dashed curve) as a function of temperature as obtained from admittance spectra using 1 kHz probe frequency.


5.5. Effect of N-implantation on the density of interface states

N- and p-type 4H- and 6H-SiC MOS capacitors fabricated on the Si-face

(0001) or C-face (000-1) as described in section 4.4 are analyzed by CG-V

measurements.

4H-SiCSi-faceT=300Kν=1kHz

UG (V)-30 -25 -20 -15 -10 -5 0 5 10

0.0

0.2

0.4

0.6

0.8

1.0

standardN-implanted

C/C

OX

∆UFB(N)p-type

n-typea)

6H-SiCSi-faceT=300Kν=1kHz

UG (V)-30 -25 -20 -15 -10 -5 0 5

C/C

OX

0.0

0.2

0.4

0.6

0.8

1.0

standardN-implanted

p-type

n-type

b)

Fig. 5.12. Comparison of C-V characteristics taken on SiC MOS capacitors (Si-face). a) 4H-SiC: A000 (n-type, dashed curve), A030 (n-type, solid curve), D000 (p-type, dashed curve) and D030 (p-type, solid curve); and b) 6H-SiC: G000 (n-type, dashed curve), G030 (n-type, solid curve), H000 (p-type, dashed curve) and H030 (p-type, solid curve). Sample description is given in Table 4.2 (section 4.4). The change of the flatband voltage induced by N-implantation ∆UFB = UFB (N) - UFB (reference) is indicated by arrows.

Independent of the conduction type, the substrate orientation or the sample

polytype, the N-implantation leads to a negative flatband voltage shift

5.5. Effect of N-implantation on the density of interface states 57

∆UFB = UFB (N) - UFB (reference). Only the results taken on Si-face MOS

capacitors are presented here (for p-type C-face capacitors see Fig. 5.18 to Fig.

5.22).

Fig. 5.12 shows the comparison of C-V curves for both the n- and p-type 4H-

(Fig. 5.12 a) and 6H-SiC MOS capacitors (Fig. 5.12 b) taken at T = 300 K. The

standard-processed (un-implanted) samples A000, D000, G000 and H000 are

marked by dashed curves, while the N-implanted samples A030, D030. G030 and

H030 are marked by solid curves. The sample description and process

parameters are given in Table 4.2 (section 4.4). The parameters: UFB,

∆UFB = UFB (N) - UFB (reference) and UH are given in Table 5.5.

It is important to point out that the normalized conductance peaks of N-

implanted n-type 4H- and 6H-SiC MOS capacitors decreased even below the

detection limit of our admittance set-up (described in section 4.7) for an N-dose

larger than DN = 2 x 1012 cm-2 as shown in Fig. 5.13. Contrary, the corresponding

conductance peaks of N-implanted p-type capacitors increased with respect to

the un-implanted samples with increasing implanted N-dose (see Fig. 5.14).

These issues are discussed in the section 6.5.

Table 5.5. Change of UFB and UH induced by N-implantation in n- / p-type 4H- and 6H-SiC (Si-face) MOS capacitors. Samples “-30” are N-implanted with [N]peak = 3 x 1018 cm-3 (see Table 4.2 in section 4.4). C-V characteristics are recorded at room temperature.

polytype 4H-SiC (Si-face) 6H-SiC (Si-face) Sample A000 A030 D000 D030 G000 G030 H000 H030

cond. type n n p p n n p p

UFB (V) 1.4 -8.6 -5.5 -15.3 -0.2 -20.5 -5.0 -13.2

∆UFB (V) -10 -9.8 -20.3 -8.2

UH (V) 0.4 0.2 0.7 1.5 0.1 0.1 0.9 2.0

A negative shift of the flatband voltage is observed, which is caused by a

positive fixed charge. It increases with increasing implanted dose. Fig. 5.14

shows normalized CG-V characteristics of N-implanted n-type 4H-SiC (Si-face)

MOS capacitors taken at 300 K as a function of the implanted N-dose (see Table

5.6). The height of the normalized conductance peak decreases with the

increasing N-implantation dose DN to the detection limit of the set-up (Fig. 5.14).


In the section 6.5.1 will be deduced a linear dependency between the implanted

dose and the created oxide fix charge.

4H-SiC Si-faceT=300K, ν=1kHz

UG (V)-20 -15 -10 -5 0 5

0.00

0.02

0.04

0.06

0.08

0.10

referenceN-implanted

G/ω

/CO

X p-typen-type

a)

6H-SiC Si-faceT=300K, ν=1kHz

UG (V)-25 -20 -15 -10 -5 0 5

0.00

0.05

0.10

0.15

0.20

0.25


G/ω

/CO

X

p-typen-type

b)

x 10

Fig. 5.13.Comparison of G-V characteristics taken on n- and p-type 4H- (a) and 6H-SiC(b) (Si-face) MOS capacitors presented in Fig. 5.12. Only the accumulation-to-depletion bias sweep is depicted. The G-V curve of n-type 6H-SiC MOS capacitor (sample G000) is magnified with factor 10.

Table 5.6. Implanted dose DN and peak concentration [N]peak of n-type 4H-SiC (Si-face) MOS capacitors presented in Fig. 5.14

Sample A000 A007 A030 A070 A100

DN (1013 cm-2) - 0.28 1.5 2.7 4.0 [N]peak (1018 cm-3) - 0.7 3 7 10


N-implantedn-4H-SiCSi-faceT=300°Cν = 1kHz

UG (V)-30 -20 -10 0 10 20 30

C/C

OX

0.0

0.2

0.4

0.6

0.8

G/ω

/CO

X

0.00

0.01

0.02

0.03

0.04

A000A007A030A070A100

Fig. 5.14. Normalized CG-V characteristics of N-implanted 4H-SiC (Si-face) MOS capacitors taken at room temperature using ν = 1 kHz and a sweep rate of 0.2 V/s. The N-implanted doses are given in Table 5.6.

The large flatband shift of C-V characteristics of surface-near N-implanted

samples can be reduced by either optimizing the implantation depth or by a

sacrificial oxidation. This is demonstrated by the results presented in Fig. 5.15.

Upon the highest implanted N dose of DN = 1 x 1014 cm-2, a maximum

concentration of the Gaussian N-profile of [N]max = 3 x 1019 cm-3 was generated.

The oxidation time and the implantation energy were adjusted in such a way that

the SiC/SiO2 interface and the peak maximum of the N-profile coincides (sample

B300). In this case the UFB of sample B300 showed an extremely high negative

shift (above the experimental access of -40 V).

Removing the oxide and exposing the SiC wafer to a new oxidation step

sample B300 transforms into B30x. Now the SiC/SiO2 interface is located at the

end of the trailing edge of the Gaussian N-profile. In addition, half of the

implanted N is removed. The dashed curve of Fig. 5.15 (sample B30x) results in a

flatband voltage shift of only – 5.3 V and the conduction peak is extremely low

and cannot be distinguished from the noise.


n-4H-SiC MOS, N-implantedT = 300 K, ν = 1 kHz

UG (V)-40 -30 -20 -10 0 10

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

G/ω

/CO

X

0.00

0.02

0.04

0.06

0.08

0.10

A000B300B30x

x 20

Fig. 5.15. CG-V of N-implanted 4H-SiC MOS capacitors differently processed: reference sample A000 (solid line), sample B300 (dotted line) sample B30x (dashed line). The SiC/SiO2-interface of sample B300 is located in the maximum of the implanted Gaussian N profile, while the interface of sample B30x is located at the end of the trailing edge of the Gaussian N profile (see description in Table 4.2).

For comparison, we fabricated in-situ N-doped 4H-SiC MOS capacitors as

shown in Fig. 4.1 b) (see section 4.4). A top-layer of dmax = 30 nm was highly

doped with N at a concentration of 3 x 1018 cm-3 (the back-ground epi

concentration was 2 x 1016 cm-3) during the CVD epitaxial growth. Two different

oxidation times were chosen in order to adjust the SiC/SiO2 interface either in the

highly doped region (dcons = 12 nm, sample C30a) or behind the highly doped

area (dcons = 39 nm, sample C30b).

The corresponding CG-V curves (see discussion concerning Fig. 5.6 in

section 5.2) of samples A000, C30a and C30b taken at T = 100 K are plotted in

Fig. 5.16. The CG-V characteristics of sample C30b (dotted curve) taken at 100 K

are similar to the un-implanted sample A000 (solid curve). The positive flatband

voltage shift is UAFC = 2.6 V, 0.2V and 3.2 V for samples A000, B30a and B30b,

respectively. This indicates an additional negative fixed charge NAFC of

6.5 x 1011 cm-2, 5 x 1010 cm-2 and 8.0 x 1011 cm-2, respectively. The hysteresis is

UH = 2.6 V, 0.5 V and 2.0 V (sweep rate 0.2 V/s, total record time 2 min), implying


a hysteresis trap density ∆NH of 6.5 x 1011 cm-2, 1.3 x 1011 cm-2 and

5.0 x 1011 cm-2. The conductance peak of samples A000 and B30a is broadened

in a similar way, while sample B30a (dotted curve) shows a conductance peak,

which is reduced to the detection limit.

n-4H-SiC Si-facein-situ N-dopedT = 100ºKν = 1 kHz

UG (V)-4 -2 0 2 4 6 8 10

C/C

OX

0.0

0.2

0.4

0.6

0.8

1.0

G/ω

/Cox

0.00

0.01

0.02

0.03

0.04

A000C30aC30b

Fig. 5.16. Normalized CG-V characteristics of in-situ N-doped 4H-SiC MOS capacitor taken at T = 100 K, ν = 1 kHz and sweep rate = 0.2 V/s (total record time up to 2 min). The SiC/SiO2-interface of sample C30a is located in the highly N-doped region (dcons = 12 nm), while the interface of sample C30b is located behind the highly N-doped area (dcons = 39 nm). The sample description is given in Table 4.2.

Table 5.7.CV relevant parameters UAFC, NAFC, UFB and Neff of n-type 4H-SiC (Si-face) MOS capacitors A000 (reference) and in-situ N-doped capacitors C30a and C30b taken at 100 K

Sample A000 C30a C30b UAFC (V) 2.6 0.2 3.2

NAFC (cm-2) 6.5 x 1011 5.0 x 1010 8.0 x 1010

UFB (V) 2.6 0.5 2.0 Neff (cm-2) 6.5 x 1011 1.3 x 1011 5.0 x 1011


n-type 4H-SiC(C-face)T=300Kν=1kHz

UG (V)-20 -10 0 10 20 30

0.0

0.2

0.4

0.6

0.8

1.0

G/ω

/CO

X

0.00

0.02

0.04

0.06

0.08

0.10

referenceN-implantedC

/CO

X

∆UFB(N)a)

n-type 6H-SiC(C-face)T=300K, ν=1kHz

UG (V)-20 -10 0 10 20

0.0

0.2

0.4

0.6

0.8

1.0

G/ω

/CO

X

0.00

0.01

0.02

0.03

0.04

0.05


C/C

OX

b)

Fig. 5.17. Comparison of CG-V characteristics taken on n-type 4H- (a) and 6H-SiC MOS capacitors (b) with C-face. Reference capacitors E000 and J000 are drawn dashed curve, while the N-implanted ones (E030, J030) correspond to the solid curves (see sample description in Table 4.2, section 4.4). The sweep direction and the change of the flatband bias ∆UFB = UFB (N) - UFB (reference) induced by N-implantation are indicated by arrow.

Fig. 5.17 shows the comparison of CG-V curves for n-type 4H- (a) and 6H-

SiC (C-face) MOS capacitors (b) taken at T = 300 K using ν = 1 kHz. The

standard-processed (un-implanted) samples E000 and J000 are marked by

dashed curves, while the N-implanted samples E030 and J030 are marked by

solid curves. The sample description and process parameters are given in Table

4.2 (section 4.4). The N-implantation leads also to a negative flatband voltage

shift. The influence of the N-implantation to the normalized conductance peak is


stronger in the case of 4H-SiC MOS capacitor (Fig. 5.17 a) and marginal in the

case of the 6H-SiC MOS capacitor (Fig. 5.17 b).

p-4H-SiC, C-faceT = 300 K, ν = 1 kHz[N]peak = 3 x 1018 cm-3

Gate bias (V)-40 -30 -20 -10 0 10

Cm

(pF)

0

20

40

60

80

100

G/ω

(pF)

0.0

0.2

0.4

0.6

0.8

1.0

F000 un-implantedF030 N-implanted

Fig. 5.18. CG-V characteristics of reference (F000, dashed curve) and of N-implanted (F030 [N]peak = 3 x 1018 cm-3, solid curve) p-type 4H-SiC (C-face) MOS capacitors taken at room temperature with probe frequency ν = 1 kHz. The C-V curves are black, the G-V curves grey. The description of the fabrication of the samples is given in Table 4.2 (section 4.4).

The C-V characteristics of p-type 4H- and 6H-SiC (C-face) MOS capacitors

measured under dark condition did not reach the accumulation within the voltage

range that was available (-40 V). Fig. 5.18 shows the CG-V characteristics of p-

type 4H-SiC (C-face) MOS capacitors F000 and F030. Starting in depletion

(+10 V) Cm increases up to about 100 pF, then it remains constant down to a gate

voltage of -40 V. The reverse sweep direction results in a more than 40 V

negative flatband shifted C-V characteristic for both the implanted and the un-

implanted sample. The G-V characteristic (grey curves in Fig. 5.18) of the un-

implanted sample F000 shows only noise; the implanted sample F030 shows an

increased normalized conductance level of 0.3 pF at the same gate bias where

the C-V characteristics becomes flat during the voltage sweep from depletion to

accumulation. Reversing the voltage sweep, the G-V characteristics of sample

F030 falls to a noisy curve around zero pF. A model explaining this CG-V feature

is proposed in section 6.5.4.


p-6H-SiC C-face[N]peak=7x1017cm-3

UG (V)-40 -30 -20 -10 0 10

C/C

ox (p

F)

0.3

0.4

0.5

0.6

0.7

0.8

first dark sweepsubsequent dark sweepsubsequent sweep with UV light

Fig. 5.19. C-V characteristics of an N-implanted p-type 6H-SiC (C-face) MOS capacitor (sample K007) (see Table 4.2). Depicted are the virgin bias sweep (gray-dashed), the subsequent sweep under dark conditions (solid curve) and the subsequent sweep under UV illumination (hv = 7.3 eV) (dotted curve).

The C-V characteristics of both the p-type 4H- and 6H-SiC (C-face) MOS

capacitors behave similar, when measuring at room temperature in dark or under

UV illumination (hν = 7.3 eV). Repeating the C-V measurement under dark

conditions immediately after the reverse sweep, the C-V characteristics is more

than 40 V negatively shifted, resembling the C-V wing of the reverse bias sweep

of the virgin C-V measurement. This is shown in Fig. 5.19 for the p-type 6H-SiC

(C-face) MOS capacitor K007 (see Table 4.2). The grey dashed curve is the

virgin record and resembles the feature revealed in Fig. 5.18. The solid curve is

the subsequent measurement. This large negative UFB shift is maintained even

after keeping the capacitor one day at room temperature in dark. The dotted

curve is the C-V record after illuminating the sample with UV light (hν = 7.3 eV)

for 5 min at room temperature.

Alternatively the large flatband shift can be recovered at elevated

temperatures (T ≥ 450 K). Fig. 5.20 shows that the subsequent gate bias sweep


at T = 300 K results in a C-V characteristics, which is similar to the initial bias

sweep at the same temperature.

Fig. 5.21 shows the temperature dependence of the C-V characteristics of a

p-type 4H-SiC (C-face) MOS capacitor (F000). The flatband voltage shifts

negatively with increasing temperature. The change of the sample temperature

from 350 K to 450 K induces a change in the flatband voltage of ∆UFB = 3.8 V.

Fig. 5.22 shows the C-V curves of p-type 6H-SiC (C-face) MOS capacitors

taken at 300 K. The increasing implanted N-dose induces an increasing UFB shift

to the depletion-toward-accumulation sweep. Qualitatively this is similar to the

case shown in Fig. 5.14.

Sample F000:p-4H-SiC C-faceT=450 Kν=10 kHz

UG (V)-40 -30 -20 -10 0 10

C/C

ox (p

F)

0.0

0.1

0.2

0.3

0.4

0.5

first recordsubsequent record

Fig. 5.20. C-V characteristics of a p-type 4H-SiC (C-face) MOS capacitor (reference sample F000) taken at T = 450 K. The subsequent C-V bias sweeps under dark conditions (dotted curve) are identical with the virgin sweep (gray, solid curve).


Sample F000:p-4H-SiC C-faceν = 10 kHz

UG (V)0 2 4 6 8 10

C/C

OX(th

)

0.2

0.3

0.4

0.5

0.6350 K400 K450 K

∆UFB

Fig. 5.21. Temperature dependent C-V characteristics of a p-type 4H-SiC (C-face) MOS capacitor (sample F000). The sweep direction and the negative shift of UFB due to the increased temperature are indicated by arrow.

p-type 6H-SiC (C-face) MOS

UG (V)-40 -30 -20 -10 0 10

C/C

ox (p

F)

0.4

0.5

0.6

0.7

0.8

K000, referenceK007, 7 x 1017 cm-3

K030, 3 x 1018 cm-3

Fig. 5.22. CG-V characteristics of N-implanted p-type 6H-SiC (C-face) MOS capacitors taken at T = 300 K. Compared are the samples: K000 (reference, dashed curve), K007 ([N]peak = 7 x 1017 cm-3, solid curve) and K030 ([N]peak = 3 x 1018 cm-3, dotted curve).

5.6. CG-V characteristics of high-k dielectric MIS capacitors 67

5.6. CG-V characteristics of high-k dielectric MIS capacitors

The need of scaling down the integrated circuits leads to a reduction of the

surface area of MOSFETs and to a lowering of the dielectric capacitance Cins

(Fig. 5.23). The surface area A in Eq. (5.1) corresponds to the product of the

length L (see Fig. 5.23) and width D of the MOSFET. The attempt to further

reduce the oxide thickness dox is ineffective, while leakage currents occur below a

certain thickness.

0ins

ox

ACd

.ε κ= ( 5.1)

A possible solution is found by using high−κ dielectrics (Al2O3, ZrO2, HfO2,

etc). Section 5.6.1 deals with thin SiO2 oxides (7-11 nm), section 5.6.2 shows

results of using a stack HfO2/SiO2 as an insulator on 4H-SiC and section 5.6.3

presents results of Al2O3 as insulator.

.dox

metal

dielectric

SiC

n+ n+

L Fig. 5.23. Scheme of an MOSFET. The surface area A is the product of length L and depth D (not shown). The insulator thickness is dox.

5.6.1. 4H-SiC/SiO2 (with thin oxides)

Thin oxide MOS capacitors are prepared to investigate the reliability of the

oxide and the influence of oxide thickness on Dit. Samples An (n-) and Ap (p-type

4H-SiC) were oxidized using the standard dry oxidation procedure: oxidation in

nominally dry O2 at 1000ºC for 2 h followed by 30 min POA in Ar. Another set

(samples Bn and Bp) was irradiated prior to the oxidation with UV light

(hν = 7.3 eV) for 30 min at room temperature in air ambient. The sample

preparation is described in Table 5.8.


n-4H-SiC MOST = 300 K, ν = 1 kHz

UG (V)-4 -3 -2 -1 0 1 2 3 4 5

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

G/ω

/CO

X

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

AnBn

Fig. 5.24. C-V and G-V characteristics of n-type 4H-SiC MOS capacitors with thin oxides. Sample description is given in Table 5.8.

p-4H-SiC MOS, T = 300 K, ν = 1 kHz

UG (V)-8 -6 -4 -2 0 2

C/C

ox

0.0

0.2

0.4

0.6

0.8

1.0

G/ω

/CO

X

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

ApBp

Fig. 5.25. C-V and G-V characteristics of p-type 4H-SiC MOS capacitors with thin oxides. The sample description is given in Table 5.8.

The CG-V characteristics of n- and p-4H-SiC MOS capacitors are plotted in

Fig. 5.24 and Fig. 5.25, respectively. Both n- and p-type samples show G-V


characteristics indicating that the corresponding MOS capacitors are leaky. The

standard processed p-type MOS capacitor results in half the G-V peak height of

the UV treated one. The n-type MOS capacitors show similar peak heights. The

40% thicker oxide of the UV treated samples increases the corresponding C-V

flatband voltage (towards positive direction for n-type and towards negative

direction for p-type).

Table 5.8. Processing of n- and p-type 4H-SiC MOS capacitors. For the UV-clean was used a Ne-lamp (hν = 7.3 eV).

An Bn Ap Bp sample n-type n-type p-type p-type

UV-clean no yes no yes dox (nm) 8 11 7 10

An oxide thickness smaller than 7 nm could not be tested in our set-up due

to the high leakage current.

5.6.2. 4H-SiC/SiO2/HfO2

Hafnium oxide HfO2 with a relative dielectric constant of κ = 20 was

deposited on a thin thermal SiO2 layer on 4H-SiC to form a reliable dielectric

stack. Fig. 5.26 displays the dc I-V characteristics for an n- and p-type 4H-SiC

MOS capacitor using an insulating stack of 20 nm HfO2 deposited on 4 nm

thermally-grown oxynitride (NO oxidation, section 4.3). Fig. 5.26 shows that the

stack with only 4 nm thick SiO2 layer is reliable up to gate bias of ±4 V. This stack

of two insulators is equivalent to a thermal SiO2 layer having the thickness

deq = 8 nm. This thickness is estimated using the following formula:

2

2 2

2

SiOeq SiO HfO

HfO

d d d= + ⋅κκ

. ( 5.2)

This estimate is confirmed by the experiment. About 8 nm thick SiO2 on a

4H-SiC MOS capacitor is reliable up to ±4 V (compare Fig. 5.26 with the G-V

characteristics of sample An in Fig. 5.24 and of sample Bn in Fig. 5.25, and see

Table 5.8).


UG (V)-8 -6 -4 -2 0 2 4 6

10-12

10-11

10-10

10-9

10-8

10-7

10-6

p-type n-type

10-5 HfO2/SiO2/4H-SiC stack

J (A

/cm

2 )

Fig. 5.26. I-V characteristics of 4H-SiC MOS capacitors with an insulating stack of 4 nm thermally-grown oxynitride and 20 nm deposited HfO2.

0.04

0.03

0.02

0.01

-4 -2 0 2 4U G (V)

G/

ω/C

ox

p-type n-type

HfO2/SiO2/4H-SiC MOS12 nm8 nm4 nm

Fig. 5.27. Normalized ac conductance as a function of applied voltage for n- (positive bias) and p-type (negative bias) 4H-SiC MOS structures taken at room temperature and at 10 kHz probe frequency. All structures consist of a 15 nm thick HfO2 layer deposited on thermally grown oxynitride of 4 nm (circles), 8 nm (squares) and 12 nm thicknesses (triangles).

Admittance (ac) measurements of HfO2/SiO2/4H-SiC MOS capacitors with

different thermal oxide thickness, conducted at room temperature with 10 kHz

probe frequency provide the normalized conductance peaks in Fig. 5.27. Both the

n- and p-type MOS capacitors show an increasing conductance peak with

increasing thickness of the oxynitride inter-layer.


5.6.3. 4H- / 6H-SiC/Al2O3

Aluminum oxide (Al2O3) with a relative dielectric constant κ = 8.8 is

deposited on 4H- and 6H-SiC to form MIS capacitors (section 4.6.2). Fig. 5.28

compares the C-V curves of differently processed samples (for sample

preparation and description see Table 4.3). The C-V curves show a positive

flatband voltage indicating the presence of a negative fixed charge. The flatband

voltage decreases in the order RCA4 > H-te4 for 4H-SiC MIS capacitors and

RCA6 > H-te6 > H6Hp for 6H-SiC MIS capacitors; in other words, H-passivation

reduces UFB. Generally, the flatband voltage of 6H- is smaller than that of 4H-SiC

MOS capacitors having Al2O3 insulator.

Table 5.9. Sample parameters dox and UFB together with preparation steps for the fabrication of Al2O3/SiC MOS capacitors

sample RCA4 RCA6 H-te4 H-te6 H6Hp polytype 4H 6H 4H 6H 6H

dox (nm) 120 120 120 120 120 UFB (V) 18.8 10.6 15.2 5.4 0.5

cleaning 1 RCA RCA RCA RCA RCA

cleaning 2 - - H-passivation

H-passivation

H-passivation

ALD Al2O3 Al2O3 Al2O3 Al2O3 Al2O3

post-deposition process

- - - - H-annealingT = 500ºC, t = 30 min

For comparison, Fig. 5.29 shows the peak heights of sample H6Hp recorded

at different times after the sample preparation. The high probe frequency

(100 kHz) and the low measurement temperature (T = 100 K) were chosen in

order to probe the shallowest states in the structure. The increase of the peak

height indicates a surface degradation with time.


Al2O3/SiC(0001) MOS

T = 300 K, ν = 1 kHz

UG (V)-10 0 10 20 30

C/C

OX

0.0

0.2

0.4

0.6

0.8

1.0 RCA4RCA6 H-te4H-te6H6Hp

Fig. 5.28. C-V characteristics of Al2O3/4H- and /6H-SiC MOS capacitors as described in Table 4.3. Depicted are sample RCA4 (solid line), RCA6 (dotted line), H-te4 (dash-dot), H-te6 (dash) and H6Hp (dash-dot-dot).

Sample H6Hp:Al2O3/n-6H-SiC (0001)T = 100ºKν = 100 kHz

UG (V)-4 -3 -2 -1 0 1 2 3 4

G/ω

/CO

X

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

initialafter 1 weekafter 2 weeks

Fig. 5.29. Normalized conductance versus gate bias for sample H6Hp, as measured at 100 K with a probing frequency of 100 kHz after sample preparation (solid line), after one week (dashed line) and after two weeks (dotted line).

6. Discussion

6.1. Oxide traps

In this section, the results of the proton trapping experiments are discussed.

They reveal that trapping of protons can reproducibly be conducted in thermal

oxides grown on both Si and SiC.

6.1.1. Distribution of oxide traps in Si/SiO2 structure

Si capacitors were H+-implanted using proton energies of 100 eV (samples

Si100100) and 300 eV (sample Si100300), and etch-off experiments were

conducted. They yield etch rates of retch = 0.75 nm/s and 0.78 nm/s, respectively

(Fig. 5.1 in section 5.1). This result reveals that the HF-etch rate is the same

(within experimental error) in both the H+-implanted Si-capacitors. For

comparison, the dashed line of Fig. 5.1 depicts the HF-etch rate of 0.5 nm/s for

an un-implanted thermal SiO2 reported in the literature [Van-91].

In the following, the two implantation energies are referred to as “low”

(100 eV, dose ≈ 1014 cm-2) and “high” energy (300 eV, dose ≈ 1018 cm-2). One can

assume the complete dissipation of both proton energies within a thin (5–10 nm)

surface layer of the oxide. However, the etch rate of the low-energy implanted

samples remains constant across the whole oxide thickness and is similar to the

etch rate of the high-energy implanted oxide. This observation cannot be

explained in the framework of implantation damage, because the damaged layers

for the low- and high-energy implantation differ strongly due to the large

difference in the implanted proton dose. Instead, it might suggest that the

accelerated HF etch is field enhanced and may be related to the presence of a

high density of positive charge at the Si/SiO2 interface. A quantitative estimation

can be extracted from the plot of Fig. 5.3 a): the initial C-V curve of sample 6H100

shows an UFB = -13.8 V; using the oxide capacitance Cox = 103 pF and the

contact area A = 2.38 x 10-3 cm2 a positive oxide charge of Neff = 5.6 x 1012 cm-2

can be calculated using Eq. (3.12). This amount of positive charge may be

responsible for the field-enhanced HF-etch.

73

6. Discussion 74

Si100100Si100300parabolic fitlinear fit

UFB

(x)/U

FB(d

ox)

Remaining oxide thickness x (nm)

dox1dox2

0 50 100 150 2000

0.2

0.4

0.6

0.8

1.0

Fig. 6.1. Variation of the flatband voltage shift UFB normalized by UFB of the unetched sample as a function of the remaining oxide thickness for samples Si100100 (100 eV/1014 cm-2, circles) and Si100300 (300 eV/1018 cm-2, squares). The implantation conditions are given in Table 5.1. The dashed curve models the flatband voltage variation under the assumption that the entire positive charge is located at the Si/SiO2 interface (using Eq. (6.6)); the solid curve models the variation of UFB under the assumption that the oxide charge is uniformly distributed throughout the oxide using Eq. (6.7). (After Afanas’ev et. al. [Afa-02].)

In order to determine the location of this charge, C-V measurements were

conducted. Fig. 6.1 shows the shift of UFB(x) of Si MOS capacitors as a function

of the oxide thickness x, normalized to the initial value UFB(dOX) of the unetched

sample (initial thickness dOX). Let us consider Eq. (3.11) (section 3.2.2):

( )s

ox fit it s 0FB ms

ox

Q Q QU

CΨ =

+ + Ψ= Φ − ( 6.1)

and neglect the interface trap-related charges (Qit and Qfit), the sign and Φms.

Reducing the oxide capacitance Cox to C(x)-1 = K·x, where x is the oxide thickness

and K contains dielectric constant and the surface area, Eq. (6.1) can be written:

( )FB oxU x K x Q= ⋅ ⋅ . ( 6.2)

Taking into account that the oxide charge has a distribution ρox (y) over the oxide

thickness x, the total oxide charge is given by integrating the charge from the

6.1. Oxide traps 75

SiC/SiO2 interface toward the surface using the following equation (see Eq. 46, p.

395 in [Sze-81]):

( ) ( )x

ox ox0

Q x y y dy= ρ∫ .

y.∫

( 6.3)

Then Eq. (6.2) becomes:

( ) ( ) ( ) ( )x d

FB ox FB ox0 0

U x K x y y dy, U d K d y y d= ⋅ ⋅ ρ = ⋅ ⋅ ρ∫ ( 6.4)

Assuming that all the charge is located at the interface,

oxox

Q , x=0 (x)

0, x>0,⎧

ρ = ⎨⎩

( 6.5)

Eq. (6.4) can be re-written as

( )( )

FB

FB

U x x .U d d

= ( 6.6)

This linear dependence of UFB on x is shown by the dashed straight line in Fig.

6.1. In this case the shift of the C-V curve is scaled down by increasing the

capacitance of the oxide.

Assuming that the charge is uniformly distributed throughout the oxide

ρox (y) = P · y, Eq. (6.4) has to be re-written as:

( )( )

2FB

2FB

U x x ,U d d

= ( 6.7)

which corresponds to the parabolic curve in Fig. 6.1.

Our results exhibit a gradual deviation from the linear dependence

suggesting that the charge resides predominantly in the vicinity of the Si/SiO2

interface, although a non-negligible portion must be distributed in the oxide bulk

and at the outer oxide surface (probably related to implantation knock-on

damage).

6. Discussion 76

In conclusion:

- protons are trapped both in the bulk of the oxide and near the

surface and Si/SiO2 interface;

- the protons induce a positive charge in all the studied MOS

capacitors;

- both the low-energy and the high-energy proton implantation

show similar etching rates.

6.1.2. Binding energy of protons trapped in SiO2

In order to determine the activation energy necessary to release protons

captured in the oxide, we studied the temperature and time dependence of UFB

for samples Si100100, Si111100, 4H100 and 6H100 (see Table 5.1 in section

5.1). As an example, in Fig. 6.2 the flatband voltage decay of sample 6H100 (Fig.

5.3) is shown for four different annealing temperatures. The exponential decay of

the flatband shift vs. annealing time (Fig. 5.3. a), b) c) and d)) is fitted for each

annealing temperature with the following equation:

( ) ( ) ( )( t A TFB 0 finU t U U 1 e−∆ = − − i ), ( 6.8)

where U0 is the starting flatband shift, Ufin the saturation flatband shift and ∆UFB(t)

the recorded shift after the integrated annealing time t at constant temperature

Tann. A(T) is the annealing rate in s-1. The fit parameters determined for sample

6H100 are given in Table 6.1.

Table 6.1. Parameters U , U and A(T) for sample 6H100 used to fit the measured curves in Fig. 6.2 with Eq.

0 fin (6.8).

Tann(K)

U0(V)

Ufin (V)

A(T) (x 10-4 s-1)

380 -13.8 -8.1 0.18 400 -8.0 -6.6 0.20 420 -6.5 -3.7 1.23 440 -3.6 1.6 8.22

6.1. Oxide traps 77

The proton annealing rate is given by

( ) a0

B

EA T A expk T

⎛ ⎞= ⋅ −⎜

⎝ ⎠,⎟ ( 6.9)

where A0 is the annealing rate at Tann = ∞ and Ea the activation energy.

a)

6H100Tann = 380 K

Annealing time (s)0 30 60 90 120 150

UFB

(V)

-15-14-13-12-11-10

-9-8-7

b)

6H100Tann = 400 K

Annealing time (s)0 30 60 90

UFB

(V)

-8.2-8.0-7.8-7.6-7.4-7.2-7.0-6.8-6.6-6.4

c)

6H100Tann = 420 K

Annealing time (s)0 10 20 30 40 50 60 70

UFB

(V)

-7.0

-6.5

-6.0

-5.5

-5.0

-4.5

-4.0

-3.5

d)

6H100Tann = 440 K

Annealing time (s)0 10 20 30 40

UFB

(V)

-4.0

-3.0

-2.0

-1.0

0.0

1.0

2.0

Fig. 6.2. Flatband voltage vs. annealing time of sample 6H100 taken at Tann of 380 K (a), 400 K (b), 420 K (c) and 440 K (d); the experimental data is extracted from the C-V measurements presented in Fig. 5.3, section 5.1.

Taking the logarithm of Eq. (6.9), it follows:

( )( ) ( ) a0

B

E 1ln A T ln A .k T

= − ⋅ ( 6.10)

which leads to the Arrhenius plot in Fig. 6.3, for samples Si100100, Si111100,

4H100 and 6H100. From the slope of the linear fit-curve, the activation energy for

the release of protons is obtained. The activation energies for the release of

protons from the structures SiO2/Si and SiO2/SiC are summarized in Table 6.2.

6. Discussion 78

1000/T (K-1)2.2 2.3 2.4 2.5 2.6 2.7

ln(A

(T))

-13-12-11-10-9-8-7-6-5-4-3

Si(111) Si(100) 4H-SiC 6H-SiC

Fig. 6.3. Arrhenius plot of proton annealing rates as a function of the reciprocal temperature for (111)-Si (circles), (100)-Si (squares), 4H-SiC (triangles) and 6H-SiC (rhombs). The activation energies Ea obtained from the slope of the linear fit using the Eq. (6.10) are given in Table 6.2.

Table 6.2. Activation energy obtained from the Arrhenius plot (Fig. 6.3) using Eq. (6.10).

sample Si111100 Si100100 4H100 6H100

MOS substrate (111) Si (100) Si 4H-SiC 6H-SiC Ea (eV) 1.7±0.2 1.6±0.2 1.4±0.2 1.3±0.2

According to Table 6.2 the mean activation energy of proton de-trapping

from the thermal oxide grown on Si and on 4H- and 6H-SiC is determined to be

equal to Ea = 1.5 ± 0.2 eV, which is close to the activation energy of the thermal

annealing of holes trapped in the oxide after injection from Si (1.4 eV, after [Fuj-

01]). This energy is considerably larger than the value of 0.6–0.7 eV reported for

mobile protons in thermally degraded buried SiO2 layers [Sta-98] or the filling of

hole traps at low temperatures [Fuj-01] indicating that there exist also proton

trapping sites with different binding energy. In the oxide grown on SiC, the

activation energy for proton de-trapping seems to be somewhat lower as

compared to the oxide grown on Si. However, this deviation is within the

experimental error bar.

6.2. Interface state density DBitB generated by standard oxidation process (4H- / 6H-SiC)

79

The binding energy of protons in SiO2 is within the experimental error

equal to

Ea = (1.5 ± 0.2) eV

for all thermally grown SiO2 oxides on Si and on 4H- and 6H-SiC suggesting

that the same Si-O network fragments are involved in capturing protons.

The spatial distribution of these fragments is evaluated in Si/SiO2 (see

section 6.1.1) revealing that these fragments are encountered in the bulk of the

oxide and at the Si/SiO2 interface. Apparently, a similar distribution is expected

for oxidized SiC.

The determined proton binding energy resembles to the activation energy

for thermal annealing of holes trapped in the oxide after injection from Si.

6.1.3. Thermal stability of oxide traps

The trapped proton represents an important source for the instability of Uth in

MOSFETs. At T > 450°C, the protons are fast and effectively de-trapped. Thus in

the case of SiC MOSFETs, one may obtain a higher stability when operating at

T > 450 K. By irradiating the MOSFETs with UV light (hν = 10 eV), a proton-

related charge is generated originating from hole trapping. In the light of the

reported observations (sections 6.1.1 and 6.1.2), it can be expected that the

radiation hardness of SiC MOSFETs operated at elevated temperatures will

increase.

6.2. Interface state density Dit generated by standard oxidation

process (4H- / 6H-SiC)

The energy range in which information on Dit can be gained using the ac

conductance method is limited by the time window, which is given by the probe

frequency (20 Hz to 1 MHz) as shown in Fig. 3.3. In this figure, the time constant

of traps in the bandgap of an n-type 4H-SiC MOS capacitor is depicted. In order

to extend the “visible” energy range, the sample temperature is scanned from

100 K to 500 K. In this way, traps located up to 0.9 eV from the SiC conduction

band edge can be monitored.

6. Discussion 80

p-type 4H-SiC

Eit-EV (eV)0.20.40.60.81.01.2

Tim

e co

nsta

nt (s

)

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

150K250K350K450K

high limit

low limit

Fig. 6.4. Time constant as a function of the energy position of interface traps in the bandgap for a p-type 4H-SiC MOS capacitor.

Fig. 6.4 plots the response time of traps at the interface of a p-type 4H-SiC

MOS capacitor using the modified Eq. (3.9):

it Vp

p t,p V

E E1 exp ,v N kT

−⎛τ = ⎜σ ⎝ ⎠⎞⎟ ( 6.11)

where σp is the energy-independent [Sze-81] hole capture cross-section, vt,p is

the average thermal velocity of holes and NV is the density of states in the

valence band. In analogy to n-type MOS capacitors, traps located up to 0.9 eV

above EV can be monitored with the ac conductance method.

The ac conductance method described in section 3.4 results in the

determination of a distribution of traps as shown in Fig. 6.5. The MOS capacitors

in Fig. 6.5 are prepared according to section 4.2. The energy reference point is

the valence band edge, which has the same energy distance from the SiO2

conduction band edge for all SiC polytypes (see section 3.2.2, and Fig. 3.5).

Dit of the p-type 4H- and 6H-SiC MOS capacitors coincides. Taking the

energy position of the valence band edge with respect to EC of SiO2 (see Fig.

3.5), then Dit is identical for all the studied SiC polytypes. As a consequence, it

can be concluded that the same chemistry and physical structure must be

6.2. Interface state density DBitB generated by standard oxidation process (4H- / 6H-SiC)

81

responsible for Dit at 4H- and 6H-SiC/SiO2 interfaces. Dit of the p-type 3C-SiC

capacitor is higher than that one of 4H- / 6H-SiC capacitors by a factor of 2 to 3.

This may indicate a higher amount of carbon clusters [Afa-97].

Dit of an n-type 6H-SiC capacitor follows the course of Dit of an n-type

4H-SiC capacitor and reaches values around 1011 eV-1 cm-2 at 2.3 eV above EV.

Dit close to EC of the 3C-SiC capacitor is about two orders of magnitude lower

than the corresponding Dit values of 4H- and 6H-SiC capacitors, which may lead

to an enhanced channel mobility in n-channel 3C-SiC MOSFETs. This

expectation is already confirmed in the literature; Lee et al. [Lee-03] reported

channel mobility values of 230 cm2 V-1 s-1.

Close to the conduction band edge, 4H- and 6H-SiC MOS capacitors show

a steep increase of Dit. The increase of Dit continues in the 4H-SiC capacitor and

reaches values > 1013 eV-1 cm-2; these high Dit values lead to small effective

electron drift mobilities in the channel of 4H-SiC MOSFETs.

SiC MOS

Eit-EV (eV)0.00.51.01.52.02.53.0

inte

rface

sta

te d

ensi

ty D

it (c

m-2

eV

-1)

1011

1012

1013

4H6H3C

E C(4

H-S

iC)

E C(6

H-S

iC)

E C(3

C-S

iC)

Fig. 6.5. Dit of 4H- (0001) (circles), 6H- (0001) (triangles) and 3C- (100) SiC MOS capacitors fabricated by dry thermal oxidation (standard oxidation, section 4.2). The energy scale starts at the SiC valence band edge EV.

In the following, a model is briefly described, which explains the distribution

of Dit at SiC/SiO2 interfaces. Dit is composed of three different types of traps (Fig.

6.6):

6. Discussion 82

SiC

Energy (eV)

EC EC EC

EC EVEV

Inte

rface

sta

te d

ensi

ty D

it (cm

-2eV

-1)

1015

1014

1013

1012

1011

1010

10 9

3 2 1

4H 6HSi Si

3C

0

Carbon Clusters

Dangling Bonds

(can be reduced by hydrogenation)

NITs: Near Interface Traps

Si/SiO 2

Fig. 6.6. Scheme of the density of states Dit at the semiconductor/SiO2 interface of Si and of different SiC polytypes; the band edges (EV, EC) of Si and of SiC polytypes are marked on the x-axis. Dit is composed of dangling bond centers, carbon clusters and near interface traps (NITs).

(a) Dangling bond centers So-called Pb-centers, which are caused by structural misfit between the

semiconductor and the oxide, are expected at SiC/SiO2 interfaces in analogy to

Si/SiO2 interfaces. These dangling bond centers are in detail discussed in the

literature; their density is of the same order like at Si/SiO2 interfaces and plays

only a marginal role compared to the total density of interface traps at SiC/SiO2

interfaces ([Pen-01] and [Afa-03]). At Si/SiO2 interfaces, these centers can be

passivated by hydrogenation.

(b) Carbon clusters The broad distribution of Dit over the SiC bandgap can be explained in the

framework of the "carbon-cluster-model" assuming a combination of π-bonded

carbon clusters of different sizes at the SiC/SiO2 interface [Afa-97]. The graphite-

like structures resulting from a distorted Si-C network at the SiC surface are hard

to remove by standard cleaning methods such as RCA. The incomplete oxidation

of the SiC crystal at the interface of SiC/SiO2 contributes also to the formation of

C-clusters. C-structures can exist already on the SiC surface before the oxidation

and they can be formed during the oxidation. In the following section, it is

6.3. Comparison of DBitB in 4H- / 6H-SiC MOS capacitors with different surface orientation

83

demonstrated that using an adequate cleaning method for removing the graphite-

like clusters at the SiC surface Dit can be reduced. A detailed presentation of the

carbon-cluster-model can be found in section 6.2 of [Bas-01].

(c) Near interface traps (NITs) According to Hall effect investigations, Dit approaches 1014 cm-2 eV-1 close

to the conduction band edge of 4H-SiC/SiO2 MOS capacitors ; these defect states

are not correlated with the π-bonds of sp2-hybridized carbon atoms [Sak-02]. It is

concluded that they belong to a chemically different defect species. Comparative

photon stimulated electron tunneling (PST) investigations conducted on both

SiC/SiO2 and Si/SiO2 interfaces result in acceptor states in the oxide close to the

interface, which are located in a narrow energy range at around 2.8 eV below the

conduction band edge of SiO2 [Afa-07]. This energy range coincides with the

conduction band edge of 4H-SiC, while it is resonant in the conduction band of Si,

6H- or 3C-SiC. In 4H-SiC, these states can trap electrons from the 4H-SiC

conduction band, which leads to a reduction of the free electron concentration

and to an additional scattering by charged impurities in the channel of MOSFETs.

In this way, the electron Hall mobility µH,e determined in the bulk of SiC can be

strongly reduced. These states have been termed: "Near Interface Traps" (NITs)

[Afa-97]. Although the atomic structure of NITs is unknown, their density

correlates with the presence of excess Si in the oxide that means they appear to

be associated with an oxygen deficiency of Si-O-Si bridges. The NITs are due to

SiO2 imperfections located in the spatial range up to 20 Å away from the interface

[Afa-97].

6.3. Comparison of Dit in 4H- / 6H-SiC MOS capacitors with

different surface orientation

Dit profiles of n-type 4H- and 6H-SiC MOS capacitors with different crystal

orientation are presented in Fig. 6.7. The energy reference is the valence band

edge, which is 6.0 eV below the conduction band edge of SiO2 (see Fig. 3.5). The

samples were thermally oxidized using the same standard oxidation process, as

described in section 4.2.

6. Discussion 84

Fig. 6.7 shows that Dit of 6H- and 4H-SiC MOS capacitors with identical

orientation follow the same “trend line”. It seems that faces with higher C-content

result in higher Dit values.

The polar Si-face provides less carbon content for oxidation than the a-

plane, which provides an equivalent number of Si and C atoms at the surface.

The polar C-face offers the oxidant species a maximum number of C-atoms for

the oxidation. Fig. 6.7 demonstrates that Dit increases in the order of the Si-face,

a-plane and C-face, especially for interface traps energetically located deeper in

the bandgap. This observation confirms the “carbon-cluster-model”.

Christiansen analyzed in his thesis [Chr-00] the dependence of the oxide

thickness as a function of SiC crystal orientation. A 6H-SiC crystal ball was

oxidized using dry thermal oxidation procedure (see section 4.2). He established

that under identical condition the oxide thickness of the C-face (000-1) was 4-10

times larger than that one of the Si-face (0001); the oxide thickness of so-called

a-planes ((11-20) and (1-100)) was about 3 times larger than that one of the

Si-face (0001). During the faster oxidation the out-diffusion of C-related species is

reduced, which may lead to the observed enhanced Dit due to C-clusters (see

Fig. 6.7).

The steep increase of Dit above 2.9 eV is attributed to NITs. Due to the

larger bandgap, 4H-SiC is especially affected by NITs. To receive a quantitatively

overview, it is necessary to introduce the quantity:

( )C

C

E 0.1eV

sh it it itE 0.4eV

N D E−

−

= ∫ dE , ( 6.12)

describing the surface density of the shallow states (close to EC). The integrated

value of Dit in the range (Eit-EV) of 2.9 to 3.2 eV – considered as the surface

density of shallow states Nsh – is 16.9x1011 cm-2, 3.3x1011 cm-2 and 8.4x1011 cm-2

for the Si-face, a-plane and C-face, respectively. In the case of 6H-SiC, Nsh, is in

the corresponding energy range (Eit-EV) of 0.8x1011 cm-2, 1.8x1011 cm-2 and

5.4x1011 cm-2 for the Si-face, a-plane and C-face, respectively. These Dit values

are summarized in Table 6.3 together with values for the effective channel

mobility taken from the literature.


85

Eit-EV (eV)

2.12.42.73.03.3

Dit (

cm-2

eV-1

)

1011

1012

1013 [0001]

[0001]

EC (4H) EC (6H)

n-type SiC MOS 4H 6H

[1120]

Fig. 6.7. Dit profiles for n-type SiC MOS capacitors fabricated on the (0001) Si-face (squares), (11-20) a-plane (circles) and (000-1) C-face (triangles). Empty symbols are for 4H- and full symbols for 6H-SiC MOS capacitors.

As can be seen, the integrated Dit values in 4H-SiC capacitors scale with the

channel mobility demonstrating that Nsh dominates the effective electron mobility.

The effect of NITs on the C-V characteristics of n-type 4H-SiC (Si-face)

MOS capacitors is demonstrated by comparing the C-V curves in Fig. 5.6, section

5.2 taken at T = 300 K and T = 100 K. The dotted curve in Fig. 5.6 corresponds to

the voltage sweep (in both directions) at 300K. With decreasing temperature, part

of the NITs can no longer emit their electron; they contribute to an additional fixed

charge (∆QAFC), which causes the flat band voltage shift ∆Vfb(AFC). NITs, which

are energetically shallower, are filled with an electron in accumulation, can emit

their electron on the way toward depletion and are responsible for the hysteresis

between opposite voltage sweeps at 100 K (∆NNIT). This effect leads to the

stationary triangle-curve in Fig. 5.6 (T = 100 K). In n-type 6H-SiC MOS capacitors

a much smaller flat band voltage shift and hysteresis are observed for identical

experimental conditions (Fig. 5.8 a). In the n-type 3C-SiC MOS capacitors, only a

marginal shift and no detectable hysteresis is observed (Fig. 5.8 b).

Other than Nsh, Neff contains integral information concerning surface

concentration of occupied interface traps Qit + Qfit (together with a parasitic

contribution from oxide traps Qox):

6. Discussion 86

( ) ( )eff FB ms OX ox fit it sN U C Q Q Q= − − Φ = + + Ψ =i 0 . (3.12)

and is obtained directly from the UFB shift of the C-V characteristics. Apparently,

Neff gives no information about the energy position of the interface traps in the SiC

bandgap.

Fig. 6.8 presents the absolute value of Neff as a function of temperature for

the three 4H-SiC crystal orientations. The three SiC orientations show a large

concentration of Neff at T = 100 K. Neff decreases to a saturation level with

increasing temperature. The C-face orientation provides a higher saturation value

of Neff; its decrease with increasing temperature is smaller than for the other

orientations.

n-4H-SiC MOS

T (K)0 100 200 300 400 500

Nef

f (cm

-2)

1012

(0001) (11-20)(000-1)

Fig. 6.8. Temperature dependence of the |Neff| (Eq. (3.12)) in n-type 4H-SiC MOS capacitors with dox = 100 nm; compared are Si-face (0001) (circles), a-plane (11-20) (triangles) and C-face (000-1) (squares). C-V curves were swept from accumulation to depletion. The entire recording of a C-V characteristic took up to 5 min.

Starting the C-V sweep in accumulation, the SiC energy bands are bended

downward and the interface traps are below the Fermi level. In this case the traps

are occupied with electrons and are negatively charged. As the bias is swept

toward depletion, the states are pulled above the Fermi level and emit their


87

electron into the conduction band. However, energetically deeper states cannot

emit their electron, if their time constant is greater than the reciprocal probe

frequency or the sweep rate (see Fig. 3.3). From Fig. 3.3, it can be assumed that

1000 s is an upper time constant, which enables an exchange of electrons. For

greater time constants, the occupied states act as „fixed charge”. At 100 K, states

beneath 3.1 eV freeze out and act as fixed charge, while this limit moves to

2.5 eV at 300 K.

The difference between Neff(100 K) and Neff(500 K) corresponds to the net

density of states in the energy range (2.7 to 3.1) eV, and results for the (0001),

(11-20) or (000-1) orientation of 4H-SiC MOS capacitors in -19.6x1011 cm-2,

-10.1x1011 cm-2 and -8.2x1011 cm-2, respectively. These values agree well with

the calculated Nsh-values for the comparable energy range (see Table 6.3). It can

be concluded that the major contribution to Neff originates from NITs, that is the

large flatband shift of C-V characteristics of 4H-SiC capacitors taken at low

temperatures (T = 100 K) is due to the freeze out of the NITs.

Table 6.3. Nsh and Neff of n-type 4H- and 6H-SiC MOS capacitors with (0001), (11-20) and (000-1) crystal orientation.

polytype 4H-SiC 6H-SiC orientation (0001) (11-20) (000-1) (0001) (11-20) (000-1)

Nsh (1011 cm-2) 16.9 3.3 8.4 0.8 1.8 5.4 in the range (Eit-EV) of 2.9 to 3.2 eV 2.6 to 2.9 eV

Neff (1011 cm-2) -19.6 -10.1 -8.2 -6.9 -3.8 -5.9

in the range (Eit-EV) of 2.8 to 3.1 eV 2.5 to 2.8 eV

µeff (cm2/Vs) 4.9 # 27.6 # ## 36.3 # 25.2 # ## # p. 99 in [Yan-00]

## no comparable data in the literature (dry oxidation)

The above statement is supported by the results obtained from 6H-SiC

capacitors, as demonstrated in Fig. 6.9. This figure reveals the absolute values of

Neff as a function of temperature for the three analyzed crystal orientations. The

difference between Neff(100 K) and Neff(500 K) corresponds to the net density of

states in the energy range (2.5 to 2.8) eV; the values are -6.9 x 1011 cm-2,

6. Discussion 88

-3.8 x 1011 cm-2 and -5.9 x 1011 cm-2, respectively. Due to the fact that NITs do not

strongly contribute to Dit in 6H-SiC, these values are smaller than the

corresponding Neff values for 4H-SiC.

n-6H-SiC MOS

T (K)0 100 200 300 400 500

Nef

f (cm

-2)

1011

1012

(0001) (11-20)(000-1)

Fig. 6.9. Temperature dependence of |Neff| in n-type 6H-SiC MOS capacitors with dox = 100 nm; compared are Si-face (0001) (circles), a-plane (11-20) (triangles) and C-face (000-1) (squares). C-V curves were swept from accumulation to depletion. The entire recording of the C-V characteristics took up to 5 min.

In conclusion proportional to the surface carbon content, the SiC crystal

orientation provides Dit-values, which increase in the order of Si-face, a-plane

and C-face, especially with regard to interface traps energetically located

deeper in the bandgap. During the faster oxidation, the out-diffusion of C-

related species is reduced, which may lead to the observed enhanced Dit-

values due to C-clusters. This observation confirms the “carbon-cluster model”

[Bas-01].

The large variation of UFB in 4H-SiC with temperature is due to a large

concentration of NITs within the bandgap. The apparent presence of “slow

traps” at 4H-SiC/SiO2 interfaces is a consequence of the freeze out of the NITs.


89

• Nitrogen at the SiO2/SiC interface An alternative way of reducing Dit at interfaces of SiC MOS capacitors is the

use of special oxidation techniques. A substantial increase in the effective

channel mobility by factor of 10 in the 4H-SiC MOSFET, was reported, when

thermal nitridation in NO was applied as compared to standard dry oxidation

[Sch-02]. This section presents the effect of oxidation in NO or a mixture of N2O

and N2 (as described in chapter 4.4) on the carbon clusters and on NITs of

SiC/SiO2 interfaces.

Dit distributions obtained from temperature- and frequency-dependent CG-V

measurements taken on dry (circles), N2O (squares), and NO oxides (triangles)

are shown in Fig. 6.10. The nitridation reduces Dit both in the lower and upper

part of the SiC bandgap; the improvement is particularly pronounced in the case

of oxide growth in NO. In this case, Dit is reduced by a factor of (3-4) near the SiC

conduction band edge. Near the SiC valence band, Dit is only decrease by a

factor of (2-3).

4H SiC

Eit-EV (eV)0.00.30.60.92.73.03.3

Dit (

cm-2eV

-1)

1012

1013

1012

1013standard oxidationN2O oxidationNO oxidation

Fig. 6.10. Energy distribution of interface traps in 4H-SiC MOS capacitors obtained from ac conductance measurements on samples with oxides grown at 1300 °C in dry O2 (circles) or O2+10%N2O (squares) and at 1175 °C in NO (triangles).

6. Discussion 90

Fig. 6.11 reveals the absolute value of Neff as a function of temperature for

the analyzed oxides. At low temperatures, O2 and N2O oxides results in a high

concentration of Neff. This contribution to the trap density is due to NITs. We can

conclude that the N2O does not efficiently reduce NITs at the SiC/SiO2 interface.

Contrary, the NO oxidation results in a flat temperature dependence of Neff, which

indicates that the density of NITs is considerably reduced in NO.

The saturation values of Neff for T > 300 K decrease in the order O2, NO

oxide and N2O oxide (see Fig. 6.11). This indicates an overall reduction of

carbon-related structures at the interface.

T (K)100 200 300 400 500

Nef

f (cm

-2)

1011

1012

O2

N2ONO

4H-SiC(0001)

Fig. 6.11. Temperature dependence of |Neff| in n-type 4H-SiC (0001) MOS capacitors with dox = 20 nm. Compared are oxides grown in nominally dry oxygen (circles), 10% N2O diluted in N2 (squares) and pure NO (triangles). The lines are eye guides. The C-V curves were swept from accumulation to depletion.

SIMS studies on MOS structures prepared in the same way as in this work

have shown that NO and N2O oxidation introduce a similar N content at the 4H-

SiC/SiO2 interface [Jam-01].

6.4. Process-induced effects on DBitB of 3C-SiC MOS capacitors 91

In summary, N2O reduces a substantial portion of C-clusters but only a

small portion of NITs. NO reduces strongly NITs, but the effect on C-clusters is

marginal, in comparison to N2O. A possible explanation is that N2O

decomposes at high temperatures in NO and atomic oxygen, which is highly

reactive. This is supported by the higher linear oxidation rate in N2O than in NO

reported by [Ja1-01]. Thus the reduction of NITs competes with the re-

oxidation, when using N2O. On the other hand, the reactive oxygen seems to be

more efficient in removing the C-clusters.

6.4. Process-induced effects on Dit of 3C-SiC MOS capacitors

Among the SiC polytypes, the cubic one (3C-SiC) has the narrowest

bandgap of 2.2 eV. For the reasons discussed in section 6.2, NITs are resonant

in the conduction band of 3C-SiC. It is expected that close to the conduction band

edge only carbon clusters and dangling bonds contribute to Dit (see Fig. 6.6). In

this section it is demonstrated that Dit values below 1011 eV-1 cm-2 are realized by

combination of UV cleaning (section 4.1) and NO oxidation (section 4.3).

Fig. 6.12 reveals Dit spectra of n- and p-type 3C-SiC MOS capacitors as

obtained subsequent to different processing steps. The sample description is

given in Table 5.4 and the processing was described in chap. 4. In the vicinity of

the conduction band edge, the use of a high quality epilayer combined with a UV

cleaning procedure and NO-oxidation results in Dit-values in the range of

1011 cm-2eV-1.

Comparing curves N3Ca with n3Cb of Fig. 6.12 a) and p3Cc with p3Cd of

Fig. 6.12 b) one can see a reduction of Dit in the entire analyzed energy range.

This has been achieved by the surface UV cleaning procedure. The surface of the

3C-SiC crystal must have strong distortion of SiC stoichiometry after the epitaxial

growth. The carbon builds graphite like structures, which are extremely resistant

to chemical cleaning processing [Koh-01]. Irradiation UV light (hν = 10 eV) in

atmosphere produces extremely aggressive ozone, and provides the excitation

energy to burn these C-structures at the SiC surface. The clean surface results in

a better interface quality of the subsequent oxidation.

6. Discussion 92

n-type 3C-SiCMOS capacitor

Eit-EV (eV)1.51.82.1

Dit

(cm

-2eV

-1)

1011

1012

XXXXXXXXX

XXXXXX

n3CaXn3Cbn3Cdn3Ce

a)

p-type 3C-SiCMOS capacitor

Eit-EV (eV)0.00.40.8

Dit

(cm

-2eV

-1)

1012

1013

p3Ccp3Cdp3Ce

b)

Fig. 6.12. Dit spectra of 3C-SiC MOS capacitors of a) n-type ([ND] = 2 x 1016 cm-3), and b) p-type ([NA] = 3 x 1017 cm-3).

An additional 3C-SiC epilayer deposited on the 3C-SiC substrate by CVD

improves further Dit as demonstrated by samples n3Cb and n3Cd in Fig. 6.12 a).

This implies that the starting condition (surface cleanness and epi- roughness)

are of great importance for the fabrication of high quality 3C-SiC MOS capacitors.

∆EX(C)=560±40 meV

1/T (1/K)3.1 3.2 3.3 3.4 3.5 3.6

ln(τ

T2 ) (s

K2 )

-2

-1

0

1

2

3 Sample p3Cd:p-type 3C-SiC MOS

Fig. 6.13. Arrhenius plot of peak X(C) of sample p3Cd in Fig. 5.11 (section 5.4) resulting in an activation energy of EX(C) = 560±40 meV.

6.5. Effect of N-implantation on DBitB in n- / p-type 4H- / 6H-SiC MOS capacitors

93

An Arrhenius analysis of the conductance peaks of sample p3Cd with probe

frequencies in the range 1 kHz – 1 MHz (e.g. ν = 1 kHz in Fig. 5.11, section 5.4)

results in an activation energy of EX(C) = (560 ± 40) meV (see Fig. 6.13). We

suggest that carbon clusters located at the interface are responsible for the broad

X(C) signal. The removal of X(C) in sample p3Ce is in agreement with the strong

reduction of Dit in this sample as demonstrated in Fig. 6.12.

Comparing Dit of samples n3Ce and p3Ce with that one of n3Cd and p3Cd

in Fig. 6.12 a) and b), the role of N at the SiC/SiO2 interface is demonstrated.

Close to EV, the Dit values of the NO-oxidized p-type 3C- (circles in Fig. 6.12) and

4H-SiC MOS capacitor (triangles in Fig. 6.10) are comparable.

In conclusion, the NO oxidation process reduces Dit over the entire 3C-SiC

bandgap, confirming the observation on the role of N at 4H-SiC/SiO2 interfaces

(see section 6.3).

Dit of the p-type 4H- and 3C-SiC MOS capacitor is comparable close to EV,

but differs by more than two orders of magnitude close to EC. The presence of

NITs within the bandgap of 4H-SiC is thus demonstrated. Due to the smaller

bandgap, NITs do not affect Dit close to the conduction band edge of 3C-SiC.

This makes the 3C-SiC attractive for MOSFET applications [Spr-04].

6.5. Effect of N-implantation on Dit in n- / p-type 4H- / 6H-SiC

MOS capacitors

An alternative method to introduce nitrogen at the interface is implantation of

a surface-near Gaussian N-profile and subsequent over-oxidation of the

implanted layer (see experimental details in section 4.4).

The effect of the surface near N-implantation in 4H-SiC results in two

features: the flatband voltage of C-V curves shifts to negative voltages (1) and the

G-V peak maxima reduce in n-type and increase in p-type SiC MOS capacitors

(2).

6. Discussion 94

6.5.1. N-implantation and flatband voltage UFB

As demonstrated in Figs. 5.12 a) and b) (section 5.5) UFB of N-implanted n-

and p-type 4H-SiC (Si-face) MOS capacitors shifts to negative voltages. The

flatband voltage shift of C-V curves shown in Fig. 5.14 is transferred into Neff

using Eq. (3.9).

T (K)

100 200 300 400

QFC

(cm

-2)

1012

1013

A000*A007 A030 A070A100

4H-SiC (0001), N-implanted

* negative charge

Fig. 6.14. Temperature dependence of Neff of N-implanted n-type 4H-SiC MOS capacitors prepared as described in section 4.4 (see Table 4.2). Sample A000 presents a negative charge, while all the other capacitors result in a positive charge due to the negative flatband shift (as seen in Fig. 5.14)

Fig. 6.14 depicts Neff as a function of temperature. N-implanted n-type 4H-

SiC (Si-face) MOS capacitors prepared as described in section 4.4 are compared

(see Table 4.2). Sample A000 resembles the O2 curve of Fig. 6.11 and indicates

a negative charge at the interface (see discussion in section 6.3). Neff (A000) is

about -3 x 1011 cm-2 and increases by a factor of 3 toward low temperatures.

Sample A002 behaves identical as sample A000 (not shown). Neff in the

implanted samples A007, A030, A070 and A100 (positive charge) shows only a

weak dependence on the temperature. This charge may be caused either by

implantation-induced defects in the oxide or by N atoms, which diffuse to the

interface to form energetically deep defects there, whose charge state cannot be


95

changed during the measurement even at 450°K. Based on the thermal stability

this charge can be considered as a fixed charge QFC = Neff.

n-type 4H-SiC (0001) MOSN-implantedT = 300 K, ν = 1 kHz

DN (1013 cm-2)0 1 2 3 4

QFC

(1012

cm

-2)

0

1

2

3

4

5

experimentallinear fit

y = 1012 + 0.1·x (cm-2)

Fig. 6.15. QFC as a function of the N-implanted dose for n-type 4H-SiC (Si-face) MOS capacitors. From low to high dose, the experimental points are obtained from samples A002, A007, A030, A070 and A100. The data is recorded at T = 300 K.

The onset of the shift of UFB occurs in N-implanted capacitors for

DN > 2 x 1012 cm-2; the shift increases proportional to DN. This is demonstrated in

Fig. 6.15 (Neff = QFC of capacitors in Fig. 5.14). According to Fig. 6.15, the ratio

QFC/DN is equal to 0.1 meaning that ten implanted N atoms generate one fixed

positive charge. The shift of the flatband voltage in p-type SiC (Si-face) MOS

capacitors shows the identical dependence on the implanted N dose. The

negative flatband voltage shift induced by N-implantation can be reduced without

increasing Dit (see section 6.5.2 and Fig. 6.17) by optimizing the relationship

between the implantation depth and the oxidation time (depth) and/or by using a

sacrificial oxidation, as demonstrated in Fig. 5.15 (section 5.5). The flatband

voltage engineering is not a topic of this work.

Prior to oxidation, samples B030, B070 and B100 (see Table 4.2, section

4.4) were exposed to a post-implantation annealing step at 1500°C for 30 min in

Ar, in order to avoid any negative effect of implantation damage. The oxide

thickness, the thermally stable QFC and Dit of the fabricated MOS capacitors were

6. Discussion 96

identical to the not-annealed samples A030, A070 and A100 (not shown). It

seems that the long time oxidation at 1120°C (for 24 h) results in the same

annealing effect as the post-implantation annealing step.

4H-SiC (Si-face) MOS,in-situ N-doped during CVD[N] = 3 x 1018 cm-3

T (K)100 150 200 250 300 350 400 450

Nef

f (cm

-2)

1012

A000C30aC30b

Fig. 6.16. Temperature dependence of Neff for in situ N-doped n-type 4H-SiC (Si-face) MOS capacitors. Compared are sample A000 (reference, circles), C30a (interface in the highly doped region, squares) and C30b (interface over the highly doped region, triangles). Sample fabrication is described in section 4.4 (see Table 4.2).

The effect of in-situ N doping (during CVD) on UFB of n-type 4H-SiC (Si-

face) MOS capacitors is different. The flatband voltage shift to positive voltages is

negligibly small indicating a small amount of fixed negative charge. Fig. 6.16

presents the temperature dependence of Neff for samples A000, C30a and C30b.

Neff of sample C30a shows only weak temperature dependence.

The temperature dependence of Neff for samples C30b and A000 is similarly

pronounced, while sample C30a shows only a weak dependence of Neff on the

temperature. This may be caused by the fact that the SiC/SiO2 interface of

sample C30a is located in the middle of the in situ N- highly-doped region, while

the interface of sample C30b is located behind the N-doped δ-layer, similar to

sample A000.


97

The presence of N-atoms at the SiC/SiO2 interface implies a temperature-

independent QFC. The N-implantation induces the formation of a fixed positive

charge QFC. The on-set of the positive fixed charge occurs at an N doses DN

above a threshold value of 2 x 1012 cm-2. Ten implanted N atoms are required

to create a fixed positive charge.

6.5.2. N-implantation and the density of interface states Dit

The G-V peaks of n-type 4H-SiC (Si-face) MOS capacitors (Fig. 5.14) are

strongly reduced in height up to a peak N concentration of 3 x 1018 cm-3 (sample

A030). In this case, the conductance peak height is lowered close to the detection

limit. With further increasing implanted N concentration, the conductance peak

height increases again (see samples A070 and A100). The density of interface

states Dit is obtained from the area below the conduction peak. In the Fig. 6.17,

Dit is plotted as a function of the energy for the reference capacitor A000 and the

N-implanted capacitors A030, A100 and A30x.

n-type 4H-SiC (Si-face) MOSN-implantation

E-EV (eV)2.42.73.03.3

Dit (

cm-2

eV-1

)

109

1010

1011

1012

1013

XXXXXX

XXXX

XXXX

XXXXXXX

A000XA030A100A30x

detection limit

Fig. 6.17. Dit vs. energy for N-implanted n-4H-SiC (Si-face) MOS capacitors. Compared are samples A000 (reference, x), A030 ([N]peak = 3 x 1018 cm-3, squares), A100 ([N]peak = 1 x 1019 cm-3, triangles) and A30x ([N]peak = 3 x 1019 cm-3, circles). The sample description is given in Table 4.2.

6. Discussion 98

The encouraging feature is that Dit can be reduced using N implantation by

two orders of magnitude in the whole investigated energy range. Both NITs and

carbon clusters are electrically eliminated from the upper half of the SiC bandgap.

Particularly close to EC, Dit reaches values of 1010 eV-1 cm-2.

In-situ N doping reduces Dit only close to the conduction band edge as

indicated in Fig. 6.18. This is a hint that particularly NITs are eliminated.

Energetically deeper states in the bandgap of sample C30b remained unaffected.

As demonstrated, the effect of N on interface traps in in-situ N-doped 4H-

SiC MOS capacitors differs from that one caused by the near surface N-implanted

profile. This difference can be caused by N atoms that either occupies different

microscopic positions or implantation damage plays an essential role.

n-type 4H-SiC (Si-face) MOSin-situ N-doped

E-EV (eV)2.73.03.3

Dit (

cm-2

eV-1

)

1011

1012

1013

A000C30b

Fig. 6.18. Dit vs. energy for the reference capacitor A000 (squares) and the in-situ N-doped capacitor C30b (see description in Table 4.2).


99

It is demonstrated that implantation of N into n-type 4H-SiC Si-face

epilayers prior to a standard nominally dry oxidation process at 1120°C strongly

reduces the density of states of n-type 4H-SiC MOS capacitors. Dit values of

1010 eV-1 cm-2 to 1011 eV-1 cm-2 are reached in the whole investigated energy

range (EC-(0.1 eV -0.6 eV)), when the SiC/SiO2 interface is positioned at the

end of the trailing edge of the implanted Gaussian N profile and the implanted N

peak concentration ranges from a few 1018 cm-3 to 1019 cm-3. In situ N-doping of

n-type 4H-SiC MOS capacitors resulted in reduction of Dit only close to the

conduction band edge.

N-implantation of p-type 4H-SiC (Si-face) samples results in an increase of

Dit close to EV. As demonstrated in Fig. 6.19, Dit increases proportional with the

peak concentration of the implanted N-profile.

p-4H SiC Si-face

E-EV (eV)0.00.30.6

Dit (

cm-2

eV-1

)

1011

1012

1013

reference3x1018

3x1019

[N]peak (cm-3)

Fig. 6.19. Dit vs. energy in the bandgap for a reference and two N-implanted p-type 4H-SiC (Si-face) MOS capacitors: un-implanted reference (grey circles), 3 x 1018 cm-3 (squares) and 3 x 1019 cm-3 (triangles).

The lowest Dit values in n-type 4H-SiC (Si-face) capacitors were reached at

DN = 1.5 x 1013 cm-2 corresponding to an implanted N peak maximum of

6. Discussion 100

[N]peak = 3 x 1018 cm-3. This optimized N-dose was used to investigate different

SiC MOS capacitors.

Dit vs. energy in the bandgap of n- / p-type 4H-SiC (Si-face) MOS capacitors

is presented in Fig. 6.20. Dit in the upper half of the bandgap is strongly reduced,

while it is increased in the lower half of the bandgap. Particularly close to EC the

reduction is 3 orders of magnitude. A similar behavior is obtained for 6H-SiC (Si-

face) capacitors as demonstrated in Fig. 6.21.

4H SiC Si-face[N]peak=3x1018cm-3

Eit-EV (eV)

0.00.30.60.92.42.73.03.3

Dit (

cm-2

eV-1

)

1010

1011

1012

1013

un-implantedN-implanted

Fig. 6.20. Dit determined in the bandgap of 4H-SiC (Si-face) MOS capacitors for the un-implanted capacitors n- (A000) and p-type (E000) (gray circles) and N-implanted capacitors n- (A030) and p-type (E030) (squares).

Although the n-type 4H-SiC (C-face) capacitor shows the highest integrated

Dit in the upper half of the bandgap, the N-implantation still results in a reduction

of Dit by more than one order of magnitude close to EC as demonstrated in Fig.

6.22.


101

6H SiC Si-face[N]peak=3x1018cm-3

Eit-EV (eV)0.00.30.60.92.42.73.0

Dit (

cm-2

eV-1

)

1010

1011

1012

1013


Fig. 6.21. Dit determined in the bandgap of 4H-SiC (Si-face) MOS capacitors for the un-implanted capacitors n- (G000) and p-type (J000) (gray circles) and N-implanted capacitors n- (G030) and p-type (J030) (squares).

n-4H SiC MOS C-face[N]peak=3x1018cm-3

Eit-EV (eV)

2.42.62.83.03.2

Dit (

cm-2

eV-1

)

1010

1011

1012

1013


Fig. 6.22. Dit in the bandgap of an N-implanted n-type 4H-SiC (C-face) MOS capacitor (squares) and a corresponding un-implanted capacitor (grey circles).

6. Discussion 102

n-6H-SiC C-face[N]peak=3x1018cm-3

E-EV (eV)2.12.42.73.0

Dit (

cm-2

eV-1

)

1011

1012


Fig. 6.23. Dit in the bandgap of an N-implanted n-type 6H-SiC (C-face) MOS capacitor (squares) and a corresponding un-implanted capacitor (grey circles).

Fig. 6.23 shows Dit of the N-implanted n-type 6H-SiC (C-face) capacitor and

a corresponding un-implanted reference. Because NITs are energetically located

above EC of 6H-SiC the N-implantation results only in a marginal reduction of Dit

close to EC. Energetically deeper in the bandgap, Dit in the implanted capacitor

increases compared to Dit of the un-implanted capacitor.

The above observations lead to the conclusion that the N-implantation

effectively eliminates both the NITs and C-clusters close to EC of 4H-SiC/SiO2

interfaces of polar orientations (Si- and C-face).

6.5.3. N-induced Coulomb-interaction

The IPE spectra shown in Fig. 6.24 indicate that N implantation does not

affect the quantum yield in the low photon energy range of 2.5 < hν < 4.5 eV. This

energy region corresponds to electrons in the conduction band of 4H-SiC

[Afa-96].

A strongly reduced IPE signal of the N-implanted capacitor (Fig. 6.24,

squares) as compared to the reference one (Fig. 6.24, circles) is observed when

the photon energy exceeds 4.5 eV. In this spectral range, the IPE signal is

dominated by excitation of electrons from SiC/SiO2 interface states related to

carbon clusters [Afa-96]. It can be concluded that N affects the interface states.


103

n-4H-SiC Si-face

photon energy hν (eV)2 3 4 5 6

IPE

yel

d (re

lativ

e un

its)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

reference N-implanted

Ug= +10 V

C1 C2

Fig. 6.24. IPE spectra of n-type 4H-SiC (Si-face) MOS capacitors: reference (A000, grey circles) and N-implanted (A030, squares). (Description of the analysis technique in [Ada-92, Bas-01].)

The IPE threshold is blue-shifted by ∆E = (1.0-1.2) eV (C1→ C2 in Fig. 6.24).

The shift is ascribed to Coulomb interaction between an electron and one

elementary positive charge induced by N-implantation (interface donor, QN = 1) in

a C-cluster. Considering the energy difference of ∆E ≈ 1 eV as Coulomb energy,

then the equation for Coulomb potential:

N

0 r e N

Q qE4 d −

⋅∆ =

πε ε, ( 6.13)

results in an electron-nitrogen donor distance de-N:

[ ]e Nr

1.44686d − =ε

nm . ( 6.14)

Here εr is the dielectric constant of the interface donor environment. The exact

value is not known. Taking into account the dielectric constant in the range (3.8 –

10), which corresponds to SiO2 or SiC surrounding matrix, the electron-nitrogen

average distance de-N is in the range (0.15 – 0.4) nm. In the case that QN ≥ 1, this

distance would be larger.

6. Discussion 104

An electron-nitrogen average distance of (0.15 – 0.4) nm indicates that

positively charged N-donors are located within the C-clusters causing a global

shift of the electron levels to higher binding energies. This effect may account

for the reduction of Dit near the SiC conduction band edge by a downshift of the

C-related levels and for the increase of Dit close to the SiC valence band (see

Fig. 6.20 and Fig. 6.21). In the presence of N atoms at the SiC/SiO2 interface -

similarly to the case of NO annealing [Afa-03] - the interface traps related to

near-interface oxide defects (NITs) are largely eliminated. This may be due to a

more compact structure of the nitrided oxide allowing a smaller mismatch with

the SiC crystal.

6.5.4. Dit of C-face p-type SiC MOS capacitors; effect of N-implantation

The CG-V characteristics of p-type 4H- and 6H SiC C-face MOS capacitors

do not reach accumulation, as shown in Figs. 5.18 - 5.22 (section 5.5). It is

proposed that a high concentration of deep traps pins the Fermi level and traps

holes from the valence band. An extreme stretch out fixes the measured

capacitance to a maximum value Cm, st, at which the Fermi level is pinned.

Firstly it is the aim to energetically localize these traps in the bandgap of 4H-

/ 6H-SiC. Holes are captured at such a high amount that the C-V flatband voltage

is shifted to more than -40 V (Fig. 5.18). In addition, these holes cannot be

emitted at room temperature on the way back to depletion. Illumination with UV

light (hν = 7.3 eV) is required to release the holes (Fig. 5.19). This may indicate

that the high concentration of traps is located either in the oxide close to the

interface or directly at the interface energetically deeper in the SiC bandgap. The

C-V characteristics in Fig. 5.20 show that the holes are emitted within a bias

sweeping at elevated temperature (450 K) in dark. This experimental observation

favors that the traps are directly located at the interface. In this case, the

evaluation via the conductance method (cap. 3) can be employed.

The CG-V characteristics do not allow to correctly estimate the oxide

thickness and as a consequence to determine Dit = f(Eit - EV). It is conducted,

therefore, an approximation using the conductance method algorithm in order to

estimate Dit and the corresponding energy position.


105

Ellipsometric measurements on p-type 4H-SiC/SiO2 (C-face) structures

oxidized for 80 min resulted in a dox = 120nm (these measurements were

conducted by Prof. T. Kimoto at the Kyoto University). The contact area is

A = 5.67 x 10-3 cm2. Then, the calculated oxide capacitance is Cox = 196 pF (Eq.

(3.17)).

Fig. 6.25 displays the experimental C-V (a) and G-V (b) curves recorded on

the reference sample F000 (grey curves) together with the theoretical C-V (a) and

G-V (b) curves, which are calculated by using the conductance model described

in section 3.4. The experimental parameters T = 300 K, ν = 1kHz,

NAl = 5 x 1015 cm-3 together with the assumed value of σs = 0.1 are used. The

floating parameter is Dit; its values are varied in the range of 1010 to

5 x 1014 eV-1 cm-2.

The C-V features of Fig. 5.4 a) support the theoretical considerations given

in section 3.4.6: at energies deeper than 0.7 eV from the conduction band edge

(at room temperature), the C-V is not stretched out and is not influenced by bias

sweep or probe frequency.

In the case of p-type capacitors, this maximum energy distance from the

valence band edge (Eit – EV)m, st, where stretch out occurs, can be estimated

starting from the capacitance value at which the Fermi pinning takes place. Cm, st

substitutes Cp in Eq. (3.6): 1

m, stox sc it

1 1CC C C

,−

⎛ ⎞= +⎜ +⎝ ⎠

⎟ ( 6.15)

where Cox, Csc and Cit are the oxide, space charge region and interface trap

capacitance, respectively. Introducing Eqs. (A-13) (Appendix A) and Eq. (3.27)

(section 3.2):

( )s

s

ssc s

d,n s

A eC sgn2 L e 1

βΨ

βΨ

ε= Ψ

⋅1−

− βΨ −, (A-13)

( )( ) ( )( )

( )2 2

sitit 2

s ss

arctan exp xe D 1 xC exp dx .2 exp x 22

+∞

−∞

ωτ ψ − ⎛ ⎞= −⎜ ⎟

ωτ ψ − σπ ⋅σ ⎝ ⎠∫

(3.27)

in Eq. (6.15) results in Ψst, max = 0.29 V. Using Eq. (3.36) for the case of p-type

conductance the energy position of the traps is given by:

6. Discussion 106

( ) ( )it V F V sE surface E E E bulk q ,− = − − ⋅ ψ ( 6.16)

and the maximum distance from the valence band is determined (at T = 300K) to

be equal to:

[ ]it V m, stE E 0.52 eV− =

( 6.17)

Sample F000:p-4H-SiC (000-1)ν = 1kHz, T = 300KFit param.: σs = 0.1

UG (V)-40 -30 -20 -10 0 10

C (p

F)

0

50

100

150

200

UG (V)-40 -30 -20 -10 0 10

G/ω

(pF)

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.00115102050exp.

Param.: Dit

(x1013cm-2eV-1)a) b)

x 0.12

Fig. 6.25. Comparison of theoretical and experimental C-V (a) and G-V (b) characteristics of sample F000 using the conductance method (section 3.4) and assuming a fix value σs = 0.1. The free parameter is Dit; it is varied in the range (1010 – 5 x 1014) eV-1 cm-2. The experimental CG-V characteristics (grey dashed curves) were recorded at T = 300 K using ν = 1 kHz.

As shown in Fig. 6.25, a trap concentration of 1010 eV-1 cm-2 generates

neither a C-V stretch out nor a G-V peak. A Dit of 1 x 1013 eV-1 cm-2 leads to a

ledge in the Cth-V characteristic starting at UG = 0.5 V (named in the following

“kink point”) and places the Gth-V peak maximum at UG = -17.5 V. Assuming

Dit ≥ 5 x 1013 eV-1 cm-2, the Gth-V peak maximum shifts above -40 V, which is the

experimentally available limit. The ledge means that the Fermi level is pinned at

the SiC/SiO2 interface. Fermi pinning is due to the presence of a high amount of

interface traps, which capture the available holes at the interface. This process

delays or prevents a change in the band bending (see section 3.4.6). Under this

condition, the surface potential does not change and the MOS capacitance

remains constant (the experimental value is Cm, st ~ 98 pF).

Independent of the trap concentration, interface traps located deeper than

Eit – EV = 0.52 eV cannot follow the bias sweep and act as fixed charge (see

discussion in sections 3.2 and 3.4.6). For this reason, the conductance curve

(Fig. 6.25 b) consists only of a noise signal at UG > 0.5 V. Assuming


107

Dit ≥ 5 x 1013 = eV-1 cm-2 in the complete bias range of (0.5 to -40 V), the Gth-V

characteristics does not show any peak (dash-do-tot curve, Fig. 6.25 b). Instead it

shows an extremely stretched-out feature and an increasing G/ω value at the kink

point. A further increase of Dit results in a shift of the peak position outside the

experimentally available bias range (1), broadens the G-V peak (2) and increases

the peak height (3). As shown in Fig. 6.25 b), the trap density of

( ) 13 1 2itD F000 5 10 eV cm− −= ⋅

( 6.18) (the dash-dot-dot curves of Fig. 6.25) reproduces sufficiently the experimental

data and may, therefore, be responsible for the uncommon CG-V characteristic of

the reference capacitor F000 (un-implanted p-type SiC (C-face) MOS capacitor).

Sample F000:p-4H-SiC (000-1)ν = 1kHz, T = 300K

UG (V)-30 -20 -10 0 10

C (p

F)

0

20

40

60

80

100

120

G/ω

(pF)

0.0

0.2

0.4

0.6

0.8

exp.fit

Fit: Dit=5x1013cm-2eV-1, σs = 0.1

Fig. 6.26. Best fit curves (dashed curves) of the experimental CG-V characteristics (grey curves) of the un-implanted sample F000 (p-type 4H-SiC (C-face) MOS capacitor) using the conductance method (section 3.4).

The energy position of the Dit, which determines the conduction peak,

cannot exactly be established. It differs from the (Eit - EV)m, st. In the case of the

Si-face p-type SiC MOS capacitor (Fig. 6.19), Dit of the un-implanted sample

D000 does not vary significantly in the energy range of (0.3-0.6) eV above EV.

Therefore, it can be assumed that also in the case of the C-face p-type SiC MOS

capacitors Dit does not significantly vary in this energy range. As a consequence,

6. Discussion 108

it is assumed that Dit is in the same order of magnitude with that one deduced in

Eq. (6.18), at (Eit - EV)m, st (kink point) as given by Eq. (6.17).

Fig. 6.26 shows the best fit obtained from Fig. 6.25. For the un-implanted

sample F000, the following parameters are determined:

13 -1 -2s it it V=0.1, D 5 10 eV cm , E -E 0.52 eVσ ≈ ⋅ .

( 6.19) and for the implanted sample F030 (Fig. 6.27) the following parameters:

14 -1 -2s it it V= 5.2, D 1 10 eV cm , E -E 0.52 eVσ ≈ ⋅

( 6.20) are determined by the same fit procedure.

Sample F030:p-4H-SiC (000-1)ν = 1kHz, T = 300K

UG (V)-40 -30 -20 -10 0 10

G/ω

(pF)0.0

0.2

0.4

0.6

0.8

1.0

1.2

C (p

F)

0

20

40

60

80

100

120

exp.fit

Fit: Dit=1x1014cm-2eV-1, σs = 5.2

Fig. 6.27. Best fit curves (dashed curve) of the experimental CG-V characteristics (grey curves) of the N-implanted sample F030 (p-type 4H-SiC (C-face) MOS capacitor) using the conductance method (section 3.4).

At 450 K, the flatband voltage shift of the C-V characteristics is

∆UFB = 3.8 V; the increased temperature enables energetically deeper traps to

communicate with the valence band. Using Eq. (3.12), the additional density of

traps, obtained from ∆UFB, is Neff = 8 x 1011 cm-2. Using Eqs. (3.6), (6.16), (A-13)

and (3.27) and the corresponding results determined at T = 350 K and 450 K, the

following positions are obtained for sample F000:


109

[ ] ( )[ ] ( )

it V boundary

it V boundary

E E 350 K 0.57 eV,

E E 450 K 0.61 eV

− =

− = .

V,

( 6.21)

Assuming a constant value of Dit in the interval (Eit-EV) = (0.57 – 0.61) eV and

using: 0.61

eff it it0.57

N D dE D 0.04 e= = ⋅∫ ( 6.22)

Dit of sample F000 can be estimated:

( ) −− ≈ = ⋅ 13 -1 2it it VD E E 0.6 eV 2 10 eV cm

( 6.23)

Eit-EV (eV)0.10.40.7

Dit (

cm-2

eV-1

)

10 12

10 13

p-type SiCMOS capacitor

10 14

D000 Si-faceF000 C-faceF030 C-face

Fig. 6.28.Estimated Dit-profiles of p-type 4H-SiC (C-face) MOS capacitors (F030: [N]peak = 3 x 1018 cm-3, triangle, F000: un-implanted, square); they are compared with Dit of the p-type 4H-SiC (Si-face) MOS capacitor (A000: un-implanted, Si-face, circle).

Fig. 6.28 summarizes the proposed Dit profiles of p-type 4H-SiC (C-face)

MOS capacitors. For comparison, also Dit of the corresponding Si-face MOS

capacitor is displayed. Dit of the N-implanted capacitor F030 is higher than of the

un-implanted capacitor (F000).

Fig. 6.29 displays CG-V characteristics for sample F030 recorded at room

temperature using 1 kHz probe frequency; parameters σs = 5.2 and

6. Discussion 110

Dit = 1 x 1014 eV-1 cm-2 are fixed. The energy position (Eit - EV) is the floating

parameter; it varies in the energy range (0.3 – 0.65) eV. Smaller energy values

(Eit - EV) - mean that the Fermi pinning occurs at shallower traps – resulting in

higher capacitance values Cm, st and in a steep increase of the normalized

conductance G/ω (see Fig. 6.29).The best fit of the experimental data is given by

the following energy:

it VE E 0.5 eV− ≈ .

( 6.24)

Dit=1x1014eV-1cm-2

ν=1kHz, T=300K, σs=5.2

UG (V)-40 -30 -20 -10 0

G/ω

(pF)

0.0

0.5

1.0

1.5x 0.05

Sample F030:p-4H-SiC C-face

UG (V)-40 -30 -20 -10 0 10 20

C (p

F)

0

30

60

90

120

150

180

0.300.350.450.500.550.65exp.

a) b)

Param.: ET-EV (eV)

Fig. 6.29. Fit of the C-V (a) and G-V (b) characteristics of sample F030 using the conductance method model (section 3.4) and assuming fix values σs = 5.2 and Dit = 1 x 1014 eV-1 cm-2. The free parameter is Eit – EV in the range (0.3-0.65) eV. The experimental CG-V characteristics (grey dashed curves) were recorded at T = 300 K using ν = 1 kHz.

Fig. 6.30 shows the dependence of the CG-V characteristics of sample F030

on the variation of the surface potential fluctuation σs. The following parameters

Dit = 1 x 1014 eV-1 cm-2, (Eit - EV) = 0.5 eV, T = 300 K and ν = 1kHz are fixed and

σs is considered as the floating parameter; it is varied between 1 and 5.2. Fig.

6.30 a) demonstrates that σs has only marginal effect on C-V characteristics,

while Fig. 6.30 b) shows that smaller values of σs underestimate the step-feature

of the experimental G-V characteristics. For our discussion above, therefore, a σs-

value of 0.1 for the un-implanted and of 5.2 for the N-implanted MOS capacitors

has been taken. For the un-implanted F000 capacitor, any value used for the

parameter σs, which is higher than 0.1 resulted in a much higher step increase at

the kink point than the noise level of the experimental curve (compare the grey

and the dashed G-V characteristics of Fig. 6.26).

6.6. DBitB in high-k dielectric MOS capacitors 111

Sample F030:p-4H-SiC C-faceν=1kHz, T = 300Kfit: Dit=1x1014eV-1cm-2

UG (V)-30 -20 -10 0 10

C (p

F)

0

20

40

60

80

100

UG (V)-30 -20 -10 0 10

G/ω

(pF)

0.0

0.3

0.6

0.9

1.2

1.55.25.04.74.01.0exp.

a) b)Param.: σs

Fig. 6.30. Fit of the C-V (a) and G-V (b) characteristics of sample F030 using the conductance method (section 3.4) and assuming a fix value Dit = 1 x 1014 eV-1 cm-2. The free parameter is σs in the range (4 - 5.2). The experimental CG-V characteristics (grey dashed curves) were recorded at T = 300 K using ν = 1 kHz.

6.6. Dit in high-k dielectric MOS capacitors

The fundamental limit for the thickness of a thin SiO2 oxide is about 1 nm.

Below 1 nm, very large gate leakage currents degrade the dielectric reliability and

prevent any practical use of the conventional SiO2. The only feasible solution to

the gate oxide scaling problem is to replace SiO2 by novel high−κ gate dielectrics,

such as HfO2, ZrO2, Al2O3, Y2O3. These materials offer significantly reduced gate

leakage and allow for continued device scaling.

6.6.1. 4H-SiC/SiO2 (with thin oxides)

The scaling down of oxide thickness results in increasing leakage currents.

On the other side, it is to expect that thinner oxides cause a lower formation of

carbon clusters and, thus, a lower Dit in the SiC bandgap. For part of the MOS

samples, the initial content of carbon at the SiC surface is removed prior to the

oxidation by means of UV irradiation. In the following, the most significant results

are summarized.

Thin oxides on 4H-SiC (dox = 7 to 11 nm) result in Dit profiles as given in Fig.

6.31. Samples “A-“ are not UV-irradiated, while samples “B-“ are irradiated with

UV (hν = 7.3 eV) prior to the oxidation. The letter “n” and “p” indicates the

conduction type.

6. Discussion 112

The density of interface states Dit close to EC is dominated by NITs. As

mentioned in section 6.2, NITs originate from a region in the oxide less than 2 nm

thick. The UV treatment of the SiC surface prior to oxidation cannot affect the

NITs in oxides, which are thicker than 2 nm. This is confirmed by comparing the

Dit profiles of samples An (not UV-irradiated) and Bn (UV-irradiated), which have

an oxide thickness of 8 and 11 nm, respectively.

4H-SiC MOS

Eit-EV (eV)0.00.52.53.0

Dit (

eV-1

cm-2

)

1012

1013

1012

1013

AnBnApBp

n-type p-type

Fig. 6.31. Dit of 4H-SiC MOS samples oxidized in nominally dry O2 at 1000ºC for 2 h. Samples Bn and Bp were irradiated with UV light (hν = 7.3 eV) for 30 min prior to oxidation. The oxide thickness dox is given in Table 5.8.

The effect of the UV treatment becomes obvious for p-type samples.

Exposing p-type SiC to UV light (Bp capacitor, rhombus curve) prior to the

oxidation results in higher Dit close to EV as compared to the not UV-irradiated Ap

capacitor in Fig. 6.31.

This observation can be explained in the framework of the carbon-cluster-

model (CCM). According to this model, Dit in the SiC bandgap originates from a

combination of large area graphite-like structures and smaller sized sp2-bonded

areas. The first have a continuum of states, while the last show influence only in

the lower half of the SiC bandgap as indicated in Fig. 6.32.

The carbon structures obtained after SiC epitaxial growth are hard to

remove by standard chemical cleaning. The UV-irradiation in environmental


atmosphere produces highly reactive ozone, which reduces the graphite-like

structures to smaller size sp2-bonded clusters. This causes an increase of Dit

close to EV as demonstrated.

Dit (

a. u

.)

E-EV (eV)5 4 3 2 1 0

EC(4H SiC)

EF

sp2 -

bond

ed

grap

hite

-like

EC(6H SiC) EC(3C SiC)EV(SiC)

oxid

e tra

ps

sp2 -b

onde

d

Fig. 6.32. Scheme of the energy distribution of interface states originating from small-size sp2-bonded carbon clusters, large area graphite-like carbon clusters and NITs (near-interfacial oxide defects). The zero point of the energy scale is placed at the valence band edge of SiC; the arrows indicate the conduction band edges of 4H-, 6H- and 3C-SiC (after [Afa-97]) as well as the valence band edge of SiC.

It is not reliable to analyze MOS capacitors having an oxide thickness

thinner than 7 nm using the conductance method. In the following, the stack

combination of thinner SiO2 and HfO2 is discussed.

6.6.2. 4H-SiC/SiO2/HfO2

Fig. 6.33 shows the energy distribution of interface traps Dit as determined

from temperature-dependent admittance measurements, using the conductance

method [Nic-67]. Dit is reduced below 1012 cm-2eV-1 close to the conduction band

edge by using a 4 nm oxynitride / 20 nmHfO2 stack as insulator. Dit in the lower

half of the SiC bandgap of Fig. 6.33 is smaller by a factor of 2 than that one of

Fig. 6.31. This can be interpreted as a reduction of the C-cluster density due to

the use of NO-oxidation combined with a 4 nm thick oxide (circles in Fig. 6.33).

The conductance peak height increases, when thicker oxynitride layers are

used as demonstrated in Fig. 5.27. This is due to a larger amount of carbon

provided by the SiC substrate during the oxidation.

6. Discussion 114

3.0E-E V (eV)

0.32.7 0.6

10 12

10 13

Dit (c

m-2

eV-1

)n-4H-SiC

NO-oxideHfO2/SiO2

Fig. 6.33. Dit of n-4H-SiC MOS capacitors. Compared are dielectrics consisting of 13 nm thick NO-oxide (triangles) and a stack of 4 nm NO-oxide / 20 nm HfO2 (circles).

In summary, the use of a 4 nm oxynitride / 20 nm HfO2 stack insulating

layer on 4H-SiC (0001) results in an interface with a trap density of

1012 eV-1 cm-2 close to the conduction band edge. The use of a thin NO-oxide

interlayer lowers the interface state density of the SiC/insulator interface and

increases the conduction band energy offset between SiC and the insulator (Fig.

4.2).

6.6.3. 4H- / 6H-SiC/Al2O3

The high positive flatband voltage UFB shown in Fig. 5.28 is caused by a

negative charge located most probable at the Al2O3/SiC interface, but

energetically deep in the SIC bandgap. The 4H-SiC MIS capacitors result in

higher UFB than the 6H-SiC MIS capacitors. This may be due to the larger

bandgap of the 4H-SiC. The H-passivation steps before and after ALD gradually

reduce UFB.

Fig. 6.34 reveals Dit profiles of MOS capacitors having Al2O3 as insulator

(see section 4.6.2). RCA cleaning prior to the deposition of Al2O3 on n-type 4H-


(open circles) and 6H-SiC (open triangles) samples results in the highest

observed Dit profile (samples RCA4 and RCA6). Hydrogen termination of the

surface prior to the insulator deposition reduces the Dit profile by about one order

of magnitude (samples H-te4 with solid circles and H-te6 with solid triangles) over

the entire analyzed energy range. Particularly in the upper half of the SiC

bandgap, Dit does not indicate the NIT-specific increase.

A hydrogen annealing step subsequent to the insulator deposition further

reduces Dit of the 6H-SiC capacitor H6Hp (open squares) by almost one order of

magnitude (7 x 1010 cm-2eV-1) near the middle of the bandgap with respect to the

H-te6 capacitor (solid triangles). This can be attributed to the hydrogenation of

SiC dangling bonds at the interface.

Al2O3/(0001)-SiC MOS

E-EV (eV)2.12.42.73.03.3

Dit (

cm-2

eV-1)

1011

1012

1013

RCA4: 4H/RCARCA6: 6H/RCAH-te4: 4H/RCA/H-pass.H-te6: 6H/RCA/H-pass.H6Hp: 6H/RCA/H-pass./H-ann.

EC(4

H)

EC(6

H)

Fig. 6.34. Dit of 4H- and 6H-SiC MIS capacitors prepared by RCA cleaning (RCA4 / open circles and RCA6 / open triangles), or RCA + H-passivation (H-te4 / solid circles, H-te6 / solid triangles) prior to ALCVD and RCA + H-passivation + ALCVD + post-deposition H-annealing (H6Hp / open squares).

However, Dit of the H6Hp capacitor (open squares) increases strongly

towards EC resembling the Dit shape of the SiC/SiO2 interface, which is attributed

to NITs.

Repeating the CG-V measurement of the H6Hp capacitor after storing the

sample at room temperature for one and for two weeks, the peak height of the G-

V characteristics taken at 100 K and a 100 kHz probe frequency increases and

becomes broader as demonstrated in Fig. 5.29. With respect to these probe

parameters predominantly shallower interface traps are monitored. This means

6. Discussion 116

that the sample “aging” induces an increased Dit-range close to EC of 6H-SiC,

which is specific to SiOx layers. It might indicate that the Al-O-Si bonds at the

Al2O3/SiC interface nucleate to a more stable SiOx-Si bonding with increasing

time, which results in a generation of NITs.

In conclusion, Al2O3/SiC MIS capacitors can be optimized to achieve Dit in

the order of 1010 eV-1 cm-2 by passivation of the surface with hydrogen prior to

the atomic layer deposition (ALD) and by hydrogen annealing of the interface

subsequent to the ALD. This procedure reduces also the shift of the flatband of

the C-V characteristics. The low Dit close to the conduction band edge of 6H-

(~ 1011 eV-1 cm-2) and of 4H-SiC (~ 7 x 1011 eV-1 cm-2) favors Al2O3 for

MOSFET applications.

The time stability of Al2O3/SiC interfaces remains an open question.

7. Summary The present work analyzes the trap properties of SiC-based metal-insulator-

semiconductor (MIS) structures.

The role of hydrogen H (proton) in the oxide of MOS capacitors is

systematically investigated. Thermally grown SiO2 layers on Si, 4H- and 6H-SiC

were implanted with H of energy E ≤ 300 eV. C-V measurements are conducted

in order to analyze the temperature-induced proton de-trapping. The effect of the

orientation of 4H- and 6H-SiC on Dit is consistently investigated. The influence of

nitrogen N on Dit of 4H-, 6H- and 3C-SiC/SiO2 MOS capacitors is investigated. A

novel approach of N implantation is described and systematically analyzed.

Dit of MIS structures using the high-κ dielectrics HfO2 and Al2O3 on SiC is

determined.

The results provided by the present work are summarized in the followings.

Oxide traps

Positive oxide traps are largely accounted to H (proton). The presence of

trapped protons both at the Si/SiO2 interface and in the oxide bulk is

evidenced in this work.

The oxide etch rate in hydrofluoric acid HF is enhanced due to the

electric field induced by positive trapped protons;

retch = 0.75 nm/s

The binding energy of protons in SiO2 is equal to:

Ea = 1.5 ± 0.2 eV

for thermally grown SiO2 oxides on Si and on 4H- and 6H-SiC. This

energy resembles to the activation energy required for thermal annealing

of holes, which are trapped in the oxide after injection from Si [Fuj-01].

At T > 450°C, the protons are fast and effectively de-trapped. Thus, a

higher stability is expected for SiC MOSFETs, when operating at

T > 450 K.

Dit in 4H- / 6H-SiC MOS capacitors with different surface orientation

Dit of 4H- and 6H-SiC MOS capacitors is affected by the substrate

orientation and increases in the order

117

7. Summary 118

Si-face < a-plane < C-face,

proportional with the oxidation rate [Chr-00] and with the surface carbon

content. A fast oxidation rate favors the formation of carbon clusters at

the interface.

The high concentration of NITs close to EC of 4H-SiC induces a large

hysteresis of C-V characteristics and a large variation of the flatband

voltage UFB with temperature T, especially at T < 200 K.

Nitrogen at the 4H-SiC/SiO2 interface

N introduced at the 4H-SiC/SiO2 by exposing SiC to an NO or N2O

ambient at high temperatures contributes to the reduction of both the

NITs and the carbon-clusters.

NO-oxidation reduces NITs.

N2O decomposes into NO and atomic O at high temperatures. A

competition between NO-induced NIT removal and O-induced NIT

building takes place. The highly reactive oxygen seems more effective in

removing the carbon clusters.

Nitrogen at the 3C-SiC/SiO2 interface

NO-oxidation reduces Dit over the entire 3C-SiC bandgap.

Combination of UV exposure (hν = 10 eV) and NO-oxidation results in a

reduction of Dit by two orders of magnitude. The obtained value close to

EC is:

Dit (3C-SiC) ≈ 1011 eV-1 cm-2.

This makes 3C-SiC attractive for MOSFET applications.

Effect of N-implantation on Dit in SiC MOS capacitors

An alternative method to introduce nitrogen at the interface is the

implantation of a surface-near N Gauss profile and the subsequent over-oxidation

of the implanted N layer. The results of N-implantation on n- / p-type 4H- and 6H-

SiC capacitors with Si- or C-face orientation are:

N-implantation induces a fixed positive charge QFC, when the implanted

N-dose is greater than DN = 2 x 1012 cm-2. Ten implanted N atoms are

required for one fixed positive charge.

119

N at the SiC/SiO2 interface implies temperature independent UFB.

N-implantation reduces Dit to:

Dit = (1010 – 1011) eV-1 cm-2

in the energy range:

Eit – EV = (3.2 eV – 2.6 eV).

This suggests an effective elimination of NITs, likely through a more

compact structure of the nitrided oxide and a smaller mismatch of the

lattice constant with that of SiC.

N-implantation increases Dit close to EV.

The shift of the steep increase in the IPE yeld of 1.2 eV, which is due to

carbon clusters, is assumed to be caused by the Coulomb interaction

between electrons and implanted N atoms. An electron-nitrogen average

distance of

de-N = (0.15 nm – 0.4 nm)

is estimated. This indicates that the positively charged N-donors are

located within the C-clusters. This effect may explain the reduction of Dit

near EC and the increase close to EV of SiC through a downshift of the C-

related levels.

High-k dielectrics: stacks of 4H-SiC/SiO2/HfO2

Stacks of HfO2/NO-oxynitride/SiC MIS capacitors are investigated. The

contribution of carbon cluster to Dit is proportional to the thickness of the

oxynitride interlayer.

A 4 nm thick oxynitride interlayer results in

Dit ≈ 1012 eV-1 cm-2

close to EC.

High-k dielectrics: Al2O3

Al2O3/SiC MIS capacitors are optimized by using hydrogen surface

passivation and by hydrogen annealing of the Al2O3/SiC interface. Dit

close to EC is:

Dit (4H-SiC) ≈ 7 x 1011 eV-1 cm-2,

Dit (6H-SiC) ≈ 1 x 1011 eV-1 cm-2.

8. Outlook In this work we performed systematic investigations on the effect of

implanted nitrogen on the SiC/SiO2 interface. In order to establish the role of the

N at the SiC/SiO2 interface, it is necessary to find out whether the N and/or the

implantation damage is the cause for the striking effects reported in this work.

Proposed are:

- Investigation of a delta implantation of Ne into an in situ N-doped

layer (prepared as described in section 4.4, Fig. 4.1 b).

- Further the chemistry at the interface should be investigated using

e.g. XPS investigation as reported in [Lih-99].

- Optimization of flatband voltage in order to obtain nominally-off

MOSFETs.

- MOSFET fabrication using this approach, in order to verify the

prediction that low Dit close to EC results in increased n-channel

mobility.

Further, investigations are suggested using lower N-implantation energy, in

order to obtain thinner oxide thickness.

The techniques used in this work in order to fabricate 3C-SiC MOS

capacitors has to be used by the fabrication of n-channel 3C-SiC MOSFETs. The

extremely low Dit close to EC of 3C-SiC as compared to 4H-SiC predicts

increased n-channel mobility.

120

Appendix

A. The solution of the one-dimensional Poisson equation

The Poisson equation describes the relationship between the potential Ψ(x)

(Eq. (3.8) in section 3.2.1, see Fig. 3.4) and the space charge density, ρ(x) (after

[Sze-81]): 2

2s

d ,dx

ψ ρ= −

ε (A-1)

where εs is the permittivity of the semiconductor.

The charge density is given by:

( ) ( D A n nx q N N p n+ −ρ = − + − ),

,Ψ

.

(A-2)

where ND, A is the doping concentration of donors, respective acceptors, and pn

and nn, are the hole and electron concentrations in n-type semiconductor. The

electron and hole concentration as a function of Ψ(x) are given by:

( )( )

0

0

n n

n n

n n exp ,

p p exp

= βΨ

= −β (A-3)

where β is the reverse value of the “thermal potential”, 1/β = kBT/q.

It is considered x = 0 at the SiC surface and x ∞ in the bulk. The SiC bulk

is at charge neutrality ρ(∞) = 0. It results in:

00D A n nN N n p+ −− = − (A-4)

The potential zero point is taken for the bulk potential Ψ(∞) = 0. Eq. (A-1)

becomes:

( ) (( 0 0

2

n n2s

d q p e 1 n e 1dx

−βΨ βΨψ= − − − −

ε)). (A-5)

Integrating from the bulk (x → ∞) to the surface (x = 0) we obtain:

( ) ( )( )0 0

d / dx

n n0 0s

d d qd p e 1 n edx dx

Ψ Ψ −βΨ βΨΨ Ψ⎛ ⎞ ⎛ ⎞ 1 d .= − − − −⎜ ⎟ ⎜ ⎟ ε⎝ ⎠ ⎝ ⎠∫ ∫ Ψ (A-6)

Taking into account that the electric field is F = -dΨ/dx, Eq. (A-6) becomes:

( ) (0 0

0

n n2

s n

qn p2F e 1 e2 n

−βΨ βΨ⎡ ⎤β⎛ ⎞⎛ ⎞

= + βΨ − +⎢⎜ ⎟⎜ ⎟β ε⎝ ⎠ ⎢ ⎥⎝ ⎠ ⎣ ⎦)1− βΨ − ⎥ (A-7)

From Gauss’s law, the charge is Q = εsF. Using the notations:

121

Appendix A 122

0

sD,n

n

Lqn

ε=

β (A-8)

as extrinsic Debye length for electrons, and:

( ) ( ) ( )0 0

0 0

n n

n n

p pH x , e 1 e 1

n n−βΨ βΨ

⎛ ⎞βΨ = + βΨ − + − βΨ − ≥⎜ ⎟⎜ ⎟

⎝ ⎠0 (A-9)

Eq. (A-7) can be re-written as:

( ) ( ) 0

0

ns

D,n n

pA 2Q sgn H ,L n

⎛ ⎞εΨ = − Ψ βΨ⎜⎜β ⎝ ⎠

,⎟⎟ (A-10)

where A is the contact area.

The sign of the charge must be opposite to the potential; when the bands

bend downward, the surface potential is positive and the electrons accumulate at

the SiC/SiO2 interface. When the bands bend upwards, the surface potential goes

negative and the positive charge dominates at the interface.

At the semiconductor surface (semiconductor/insulator interface):

( ) ( ) 0

s0

nsSC s s

D,n n

pA 2Q Q sgn H ,L nΨ=Ψ

⎛ ⎞ε= Ψ = − Ψ βΨ⎜⎜β ⎝ ⎠

⎟⎟ (A-11)

The differential capacitance of the semiconductor depletion region is:

( )( )0

0

0

0

n

ns ssc s

s nD,ns

n

p1 e e 1

ndQ AC sgnd p2 L

H ,n

βΨ −βΨ− + −ε

= = − ΨΨ ⎛ ⎞⋅

βΨ⎜ ⎟⎜ ⎟⎝ ⎠

(A-12)

The surface charge of an n-type SiC semiconductor can be simplified

depending on the sign of Ψs. Considering the zero point of Ψs as the flatband

situation (see Fig. 3.4 section 3.2), the positive sign is, when the bands bend

downward (accumulation) and the negative sign, when the bands bend upwards

(depletion/deep depletion/inversion).

In accumulation, Ψs is positive and QSC is negative (Eq. (A-11)). The

function H described by Eq. (A-9) is dominated by the fourth term and

QSC ~ -exp(qΨs/2kT). For Ψs = 0, we have the flatband condition (Q = 0). In

depletion, Ψs is negative and QSC becomes positive (comprised of ionized

donors). As long as |Ψs| < |ΨB|, the function H is dominated by the fifth term of Eq.

(A-9) (QSC ~ | Ψs|1/2). In this case, Eq. (A-12) becomes:

123

( )s

s

ssc s

d,n s

A eC sgn2 L e 1

βΨ

βΨ

ε= Ψ

⋅1−

− βΨ − (A-13)

At |Ψs| > |ΨB|, function H is dominated by the first term of Eq. (A-9) and

QSC ~ exp(q|Ψs|/2kT). The semiconductor is in deep-depletion/inversion.

Appendix

B. List of symbols

δψ surface potential fluctuation (eV)

εox oxide dielectric constant

εs semiconductor dielectric constant

κ insulator’s relative dielectric constant

σn, p capture cross-section of electrons / holes (cm-2)

σs standard surface potential deviation

τn response time constant for electron emission from an interface state

τp response time constant for hole emission from an interface state

Ψ(x) potential difference between EF and Ei (depends on x)

ΨB bulk potential (large x)

Ψs surface potential (x = 0)

Ψst, max surface potential limit for stretch out

ω angular frequency related to the probe frequency, ν, by the relationship ω = 2π·ν, (rad)

Α, Α0 annealing rate (of protons from insulator layer)

ALD atomic layer chemical vapor deposition

AS admittance spectroscopy

C capacitance (pF)

CFp measured capacitance at the Fermi pinning bias

Cins insulator capacitance (pF)

Cit interface trap capacitance (pF)

Cm measured capacitance (pF)

Cm,acc measured capacitance in accumulation (pF)

Cm, st measured capacitance value where stretch out begins

Cox oxide capacitance (pF)

Csc space charge region capacitance (pF)

Cth theoretical capacitance (function of applied gate bias) (pF)

CCM carbon cluster model

CM conductance method

124

125

C-V capacitance versus voltage curve (C=f(UG))

CG-V capacitance/conductance versus voltage

de-N average electron-N distance in the carbon cluster

dcons consumed SiC depth during oxidation (nm)

Dit interface-trap density (eV-1 cm-2)

deq thickness of equivalent SiO2 insulating layer

DN nitrogen implantation dose (cm-2)

de-N average distance of electron-nitrogen (interface donor)

dox insulator (oxide) thickness (nm)

dsc depth of space charge region

E energy (eV)

Ea activation energy (eV)

EC energetic level of conduction band minima

EF Fermi level

Ei intrinsic Fermi level

Eit interface trap energy position

En neutrality energy (eV)

EV energetic level of valence band maxima

g±degeneracy factor (describe the change in occupancy from positive to negative charged state)

G conductance (µS)

Git interface trap conductance

Gm measured conductance

Gm,acc measured conductance in accumulation

G-V (normalized) conductance versus voltage curve (G/ω=f(UG))

K relative dielectric constant (also εr)

kB Boltzmann constant

MOS metal oxide semiconductor

MOSFET metal oxide semiconductor field effect transistor

NA doping concentration of acceptors (cm-3)

NAFC additional fixed charge (cm-2)

NC0 density of states in conduction band (temperature independent term)

Appendix B 126

ND doping concentration of donors (cm-3)

Neff effective surface (net-) density of charge at the interface (cm-2)

∆NH density of hysteresis charge (cm-2)

Nsh surface density of shallow states (cm-2)

NV0 density of states in valence band (temperature independent term)

NITs near interface states

PITC proportional / integral temperature controller

POA post oxidation annealing

q elementary charge = 1.6 x 10-19 C

Qf fixed oxide charge

Qfit fix interface trap charge

QG gate charge

Qit(Ψs) potential dependent interface trap charge

Qft fix trapped charge at the interface

Qm mobile ionic charge

QN number of elementary positive charge induced by N-implantation

Qot oxide trapped charge

Qox oxide (total) charge

Qres released charge (protons)

QSC charge of the semiconductor space charge region

rHF oxide etch rate in HF acid

Rs serial resistance

Τ temperature (K)

Τann annealing temperature

Tmes measurement temperature

TSC thermally stimulated current

Uac ac bias component

UAFC flatband shift at low temperatures due to additional fixed charge

UFB flat band bias

UG gate bias

∆UH hysteresis of the C-V characteristics

127

Uox potential drop over the oxide

UT threshold voltage

vt,n/p average thermal velocity of electrons/holes

vt0,n temperature independent thermal velocity term

Ym measured admittance

Ym,acc measured admittance in accumulation

Zacc impedance of the MOS in accumulation

Appendix

C. List of used physical constants and material parameter

Quantity Symbol Value

Elementary charge q 1.6 x 10-19 C

Dielectric constant (vac.) ε0 8.85 x 10-14 F/cm

Relative dielectric constant SiO2 εr 3.84

Relative dielectric constant HfO2 κ 8.8

Relative dielectric constant Al2O3 κ 20

SiC Material parameter

Polytype 4H 6H 3C

Egap (eV) 3.3 2.96 2.2

εr 10.3 10.03 9.24

NC0 (cm-3 K-3/2) 2.24 x 1015 4.12 x 1015 2.62 x 1015

NV0 (cm-3 K-3/2) 4.83 x 1015 4.83 x 1015 7.25 x 1015

<vth>n (cm s-1 K-1/2) 6.74 x 105 6.74 x 105 6.74 x 105

<vth>p (cm s-1 K-1/2) 1.55 x 105 1.30 x 105 1.19 x 105

128

Appendix

D. Bibliography

Ada-92 V.K. Adamcuck and V.V. Afanas’ev, “Internal photoemission

spectroscopy of semiconductor-insulator interfaces”, Progress in

Surface Science, Vol. 41 (1992) 111-211

Afa-95 V.V. Afanas'ev, A.G. Revesz, G.A. Brown and H.L. Hughes, “Charge

instability of bonded silicon dioxide layer induced by wet processing”, J.

Electrochem. Soc. 142 (1995), 1983–1986

Afa-96 V.V. Afanas'ev, M. Bassler, G. Pensl, M. Schulz and E.S. von

Kamienski, “Band offsets and electronic structure of SiC/SiO2

interfaces”, J. Appl. Phys., 79 (1996) 3108-3114

Afa-97 V.V. Afanas'ev, M. Bassler, G. Pensl and M. Schulz, “Intrinsic SiC/SiO2

Interface States”, Physica Status Solidi(a) 162/1 (1997), 321-337

Afa-02 V.V. Afanas’ev, F. Ciobanu, G. Pensl and A. Stesmans, “Proton

trapping in SiO2 layers thermally grown on Si and SiC,”, Solid-State

Electronics 46 (2002) 1815–1823

Afa-03 V.V: Afanas'ev, A. Stesmans, F. Ciobanu, G. Pensl, K.Y. Cheong and

S. Dimitrijev, “Mecanisms responsible for improvement of 4H-SiC/SiO2

interface properties by nitridation”, Appl. Phys. Lett 82 (2003) 568-570

Af1-03 V. V. Afanas'ev, F. Ciobanu, G. Pensl, A. Stesmans, "Contributions to

the Density of Interface States in SiC MOS Structures", in Silicon

Carbide - Recent Major Advances, eds. W. J. Choyke, H. Matsunami,

G. Pensl, Springer, Berlin 2003, pp. 343-371

Bas-01 M. Bassler, “Eigenschaften elektrisch aktiver Zustände an der

Grenzfläche SiC/SiO2”, Doctor of Philosophy Dissertation, Universität

Erlangen-Nürnberg, 2001 (in German)

Ber-66 C.N. Berglund, “Surface states at steam-grown silicon-silicon dioxide

interfaces”, IEEE Trans. Electron. Devices, ED-13/10 (1966), 701-705

129

Appendix D 130

Car-93 E.C. Carr and R.A. Buhrman, “Role of interfacial nitrogen in improving

thin silicon oxides grown in N2O”, Appl. Phys. Lett. 63 (1993) 54-56

Cha-00 K. C. Chang, T. Nuhfer, L. M. Porter, Q. Wahab, "High-carbon

concentrations at the silicon dioxide-silicon carbide interface identified

by electron energy loss spectroscopy", Appl. Phys. Lett. 77 (2000)

2186-2188

Ceo-03 K.Y. Cheong, “Silicon Carbide as the Nonvolatile-Dynamic-Memory

Material”, Doctor of Philosophy Dissertation, Griffith University, 2003

Ce1-03 K.Y. Cheong, S. Dimitrijev, J. Han and B. Harrison, “Electrical and

physical characterization of gate oxides on 4H-SiC grown in diluted

N2O”, J.Appl.Phys 93 (2003) 5682-5686

Chr-00 Kai Christiansen, “Anisotropie des epitaktischen Wachstum und

Aspekte der Oxidation von Siliziumkarbid”, Doctor of Philosophy

Dissertation, Universität Erlangen-Nürnberg, 2000 (in German)

Chu-00 G.Y. Chung C. C. Tin, J. R. Williams, “Effect of nitric oxide annealing on

the interface trap densities near the band edges in the 4H polytype of

silicon carbide”, Appl. Phys. Lett. 76 (2000) 1713-1715

Ch1-00 G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, M. Di Ventra, R.K.

Chanana, S.T. Pantelides, L.C. Feldman and R.A. Weller, “Effects of

anneals in ammonia on the interface trap density near the band edges

in 4H-silicon carbide metal-oxide-semiconductor capacitors”, Appl.

Phys. Lett. 77 (2000) 3601-3603

Chu-01 G.Y. Chung, C.C. Tin, R.J. Williams, K. McDonald, R.K. Chanana, R.A.

Weller, S.T. Pantelides, L.C. Feldman, O.W. Holland, M.K. Das and

J.W Palmour, “Improved inversion channel mobility for 4H-SiC

MOSFETs following high temperature anneals in nitric oxide”, IEEE

electron. Dev. Lett. 22/4 (2001) 2864-2866

Chu-04 G Y Chung, J R Williams, K McDonald and L C Feldman, “4H-SiC

oxynitridation for generation of insulating layers”, J. Phys.: Condens.

Matter 16 (2004) S1857-S1871

131

Coo-97 J.A. Cooper, Jr, “Advances in SiC MOS Technology”, Physica Status

Solidi (a) 162/1 (1997), 305-320

Dha-04 S. Dhar, Y.W. Song, L.C. Feldman, T. Isaacs-Smith, C.C: Tin, R.J.

Williams, G. Chung, T. Nishimura, D. Starodub, T. Gustafsson and E.

Garfunkel, “Effect of nitric oxide annealing on the interface trap density

near the conduction band edge of 4H-SiC at the oxide/(11-20) 4H- SiC

interface”, Appl. Phys. Lett. 84 (2004) 1498-1500

Don-03 K. McDonald, L.C. Feldman, R.A. Weller, G.Y. Chung, C.C. Tin and

J.R. Williams, “Kinetics of NO nitridation in SiO2/4H-SiC”, J. Appl. Phys.

93 (2003) 2257-2261

Do1-03 K. McDonald, R.A. Weller, S.T. Pantelides, L.C. Feldman, G.Y. Chung,

C.C. Tin and J.R. Williams, “Characterization and modeling of the

nitrogen passivation of interface traps in SiO2/4H-SiC”, J. Appl. Phys.

93 (2003) 2719-2722

Fuj-01 S. Fujieda, “Charge centers induced in thermal SiO2 films by high

electric field stress at 80 K”, J. Appl. Phys. 89 (2001), 3337–3342

Gao-03 K.Y. Gao, Th. Seyller, L. Ley, F. Ciobanu, G. Pensl, A. Tadich, J.D.

Riley and R.G.C. Leckey, “Al2O3 prepared by atomic layer deposition

as gate dielectric on 6H-SiC(0001)”, Appl. Phys. Lett. 83 (2003) 1830-

1832

Gre-01 M.L. Green, E.P. Gusev, R. Degrave and E.L. Garfunkel, “Ultrathin (<4

nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics:

Understanding the processing, structure, and physical and electrical

limits”, J. Appl. Phys. 90 (2001) 2057-2121

Jam-01 P. Jamet and S. Dimitrijev, “Physical properties of N2O and NO-nitrided

gate oxides grown on 4H-SiC” Appl. Phys. Lett. 79 (2001) 323-325

Ja1-01 P. Jamet, S. Dimitrijev, and P. Tanner, “Effects of nitridation in gate

oxides grown on 4H-SiC”, J. Appl. Phys. 90 (2001) 5058-5063

Appendix D 132

Ker-70 W. Kern, and D.A. Puotien, “Cleaning Solutions Based on Hydrogen

Peroxide for Use in Semiconductor Technology”, RCA Review, 31(2)

(1970) 187—206

Koh-01 A. Koh, A. Kestle, C. Wright, S.P. Wilks, P.A. Mawby and W.R. Bowen,

“Comparative surface studies on wet and dry sacrificial thermal

oxidation on silicon carbide”, Appl. Surf. Sci. 174 (2001) 210-216

Lee-03 K.K Lee, Y. Ishida, T. Ohshima, K. Kojima, Y. Tanaka, T. Takahashi, H.

Okumura, K. Arai and T. Kamija, “N-channel MOSFETs fabricated on

homoepitaxy-grown 3C-SiC films”, IEEE Electron Dev. Lett. 24 (2003)

466-468

Lih-97 H. Li, S. Dimitrijev, H.B. Harrison, and D. Sweatman, “Interfacial

characteristics of N2O and NO nitrided SiO2 grown on SiC by rapid

thermal processing”, Appl. Phys. Lett, 70 (1997) 2028-2030

Lih-99 H. Li, S. Dimitrijev, D. Sweatman, H.B. Harrison, P. Tanner and B. Feil,

“Investigation of nitric oxide and Ar annealed SiO2/SiC interfaces by x-

ray photoelectron spectroscopy”, J. Appl. Phys., 86 (1999) 4316-4321

Lih-00 H.F. Li, S. Dimitrijev, D. Sweatman and H.B. Harrison, “Effect of NO

annealing conditions on electrical characteristics of n-type 4H-SiC MOS

capacitors”, J. Electr. Mat. 29/8 (2000) 1027-1032

Leh-66 K. Lehovec, “Frequency dependence of the impedance of the

distributed surface states in MOS structures”, Appl. Phys. Lett. 8 (1966)

48-50

Mae-02 Y. Maeyama, H. Yano, T. Hatayama, Y. Uraoka, T. Fuyuki and T.

Shirafuji, “Improvement of SiO2/α-SiC interface properties by nitrogen

radical treatment”, Mat. Sci. Forum Vols 389-393 (2002) 997-1000

MaT-89 T.P. Ma and P.V. Dressendorfer, “Ionizing radiation effects in MOS

devices and circuits”, Wiley, New York (1989)

Nak-96 S. Nakayama and T. Sakai, “Redistribution of in situ doped or ion-

implanted nitrogen in polysilicon” J. Appl. Phys. 79 (1996) 4024-4028

133

Nic-67 E.H. Nicollian and A. Goetzberger, “The Si-SiO2 interface – electrical

properties as determined by the metal-insulator-silicon conductance

technique”, Bell system technical Journal, 46 (1967) 1055-1133

Nic-82a E.H. Nicollian and J.R. Brews, “MOS (metal oxide semiconductor)

physics and technology”, John Wiley & Sons eds. (1982) cap. 5

Nic-82b E.H. Nicollian and J.R. Brews, “MOS (metal oxide semiconductor)

physics and technology”, John Wiley & Sons eds. (1982) cap. 8

Óla-04 H. Ólafsson, “Detection and removal of traps at the SiO2/SiC interface”,

Doctor of Philosophy Dissertation, Chalmers University of Technology,

2004

Pal-89 J.W. Palmour, R.F. Davis, H.S. Kong, S.F. Corcoran, D.P. Griffis,

“Dopant redistribution during thermal oxidation of monocrystalline beta-

SiC thin films”, J. Electrochem. Soc. 136 (1989) 502-507

Pen-01 G. Pensl, M. Bassler, F. Ciobanu, V. Afanas'ev, H. Yano, T. Kimoto, H.

Matsunami, "Traps at the SiC/SiO2-Interface", Mat. Res. Soc. Symp.

Proc. 640 (2001) H3.2.1-H3.2.11.

Pen-03 G. Pensl, F. Schmid, F. Ciobanu, M. Laube, S.A. Reshanov, N.

Schulze, K. Semmelroth, H. Nagasawa, A. Schoner and G. Wagner:

“Electrical and optical characterization of SiC”, Mat. Sci. Forum Vols

433-436 (2003) 365-370

Res-03 S. Reshanov, O. Klettke, G. Pensl, “Majority traps observed in H+- or

He+-implanted Al-doped 6H-SiC by Admittance and Deep Level

Transient Spectroscopy”, Mat. Sci. Forum Vols 433-436 (2003) 379-382

Sak-02 N. S. Saks, M. G. Ancona, E. W. Rendell, "Using the Hall effect to

measure interface trap densities in silicon carbide and silicon metal-

oxide-semiconductor devices", Appl. Phys. Lett. 80 (2002) 3219-3221

Appendix D 134

Sch-02 R. Schörner, P. Friedrichs, D. Peters, D. Stephani, S. Dimitrijev and P.

Jamet, “Enhanced channel mobility of 4H-SiC metal-oxide-

semiconductor transistors fabricated with standard polycrystaline silicon

technology and gate-oxide nitridation”, Appl. Phys. Lett. 80 (2002)

4253-4255

Sch-87 K. Schott, K.C. Hofmann and M. Schulz, “Blocking of silicon oxidation

by low-dose nitrogen implantation”, Appl. Phys. A 45 (1987) 73-76

Sch-93 J. Schmitt, “Oxidation von 6H-SiC Einkristallen in Abhängigkeit von der

Dotierung und der Temperatur”, Doctor of Philosophy Dissertation,

Universität Erlangen-Nürnberg, 1993 (in German)

Sho-52 W. Shockley, T.W. Read Jr., “Statistics of the recombination of holes

and electrons”, Phys. Rev. 87/5 (1952) 835-842

Sie-02 N. Sieber: “Wasserstoff- und sauerstoffstabilisierte 6H-SiC 0001-

Oberflächen – eine Studie chemischer, struktureller und elektronischer

Eigenschaften”, Doctor of Philosophy Dissertation, Universität

Erlangen-Nürnberg, 2001, p. 49 (in German)

Spr-04 D.J. Spry, A.J. Trunek, P.G. Neudeck, “High breakdown field P-type

3C-SiC Schottky diodes grown on step-free 4H-SiC mesas”, Mat. Sci.

Forum Vols 457-460 (2004), 1061-1064

Sta-98 R.E. Stahlbush, R.K. Lawrence and H.L. Hughes, “H+ motion in SiO2:

Incompatible results from hydrogen-annealing and radiation models”,

IEEE Trans. Nucl. Sci. NS-45 (1998), 2398–2407

Sze-81 S.M. Sze, “Physics of semiconductor devices”, 2nd ed., John Wiley &

Sons, Inc. eds. (1981)

Ter-62 L.M. Terman, Solid-State Electron.,5 (1962) 285

Van-91 K. Vanheusden and A. Stesmans, “Chemical etch rates in HF solutions

as a function of thickness of thermal SiO2 and buried SiO2 formed by

oxygen implantation”, J. Appl. Phys. 69 (1991), 6656–6664

135

Wan-02 J. Wan, M.A. Capano, Michael R. Melloch, J.A. Cooper Jr., “N-Channel

3C-SiC MOSFETs on Silicon Substrate”, IEEE Electron. Dev. Lett. 23

(2002) 482-484

Yan-00 H. Yano, “Control of Electronic Characteristics at SiO2/SiC Interface for

SiC Power Metal-Oxide-Semiconductor Devices”, Doctor of Philosophy

Dissertation, Kyoto University, 2000

Yan-03 H. Yano, Y. Maeyama, Y. Furumoto, T. Hatayama, Y. Uraoka, and T.

Fuyuki, “Effects of nitrogen radicals irradiation on performance of SiC

MOSFETs”, Mat. Sci. Forum Vols 433-436 (2003) 945-948

Yan-05 H. Yano, T. Hatayama, Y. Uraoka and T. Fuyuki, “High temperature NO

annealing of deposited SiO2 and SiON films on n-type 4H-SiC”, Mat.

Sci. Forum Vols. 483-485 (2005) 685-688

Zie-85 J.F. Ziegler, J.P. Biersack and U. Littmark, “The Stopping and Range of

Ions in Solids”, Pergamon Press, New York, (1985)

Appendix

E. Publications list

1. Traps at the SiC/SiO2-Interface, G. Pensl, M. Bassler, F. Ciobanu, V. Afanas'ev, H. Yano, T. Kimoto, and H. Matsunami; 2000 Mat.Res.Soc.Symp.Proc 640 (2001), H3.2.(1-11).

2. Proton trapping in SiO2 layers thermally grown on Si and SiC, V.V. Afanas’ev, F. Ciobanu, G. Pensl and A. Stesmans; Solid-State Electronics 46 (2002) 1815-1823.

3. Electrical and Optical Characterization of SiC, G. Pensl, F. Schmid, F. Ciobanu , M. Laube, S.A. Reshanov, N. Schulze, K. Semmelroth, H. Nagasawa, A. Schöner , G. Wagner; Mater. Sci. Forum 433-436 (2002), 365-370.

4. Traps at the interface of 3C-SiC/SiO2-MOS-Structures, F. Ciobanu, G. Pensl, H. Nagasawa, A. Schöner, S. Dimitriev, K.-Y. Cheong, V.V. Afanas’ev and G. Wagner; Mater. Sci. Forum 433-436 (2002), 551-554.

5. Hall Scattering Factor of Holes and Shallow Defect Centers in Aluminum-doped SiC, G. Pensl, F. Ciobanu, M. Krieger, M. Laube, S. Reshanov, F. Schmid, G. Wagner, H. Nagasawa, A. Schöner; 2002 Mat.Res.Soc.Symp.Proc 742 (2003), K3.2.(163-174).

6. Mecanism responsible for improvement of 4H-SiC/SiO2 interface properties by nitridation, V.V. Afanas’ev, A. Stesmans, F. Ciobanu, G. Pensl, K.Y. Cheong and S. Dimitriev; Appl.Phys.Lett. 82 (2003) 568-570.

7. Al2O3 prepared by atomic layer deposition as gate dielectric on 6H-SiC(0001), K.Y. Gao, Th. Seyller, L. Ley, F. Ciobanu, G. Pensl, A. Tadich, J.D. Riley and R.G.C. Leckey; Appl. Phys. Lett. 83 (2003) 1830-1832.

8. Band alignment and defect states at SiC/oxide interfaces, V V Afanas’ev, F Ciobanu, S Dimitriev, G Pensl and A Stesmans, J. Phys: Condens Matter 16 (2004), S1839-S1856.

9. Electronic properties of SiON/HfO2 insulating stacks on 4H-SiC (0001), V. V. Afanas’ev, S. A. Campbell, K. Y. Cheong, F. Ciobanu, S. Dimitrijev, G. Pensl, A. Stesmans, L. Zhong, Mater. Sci. Forum 457-460 (2004), 1361-1364.

10. Structural and electronic properties of the 6H-SiC (0001) / Al2O3 Interface prepared by atomic layer deposition, Th. Seyller, K.Y. Gao, L. Ley, F. Ciobanu, G. Pensl, A. Tadich, J.D. Riley and R.G.C. Leckey; Mater. Sci. Forum 457-460 (2004), 1369-1372.

11. Contributions to the density of interface states in SiC MOS structures, V.V. Afanas’ev, F. Ciobanu, G. Pensl, A. Stesmans, Silicon Carbide: Recent Major Advances, W.J. Choyke, H. Matsunami, G. Pensl (eds.), Springer Verlag, Berlin, 2004, p343-371.

136

137

12. ALD Deposited Al2O3 Films on 6H-SiC (0001) after Annealing in Hydrogen Atmosphere, K.Y. Gao, Th. Seyller, K. Emtsev, L. Ley, F. Ciobanu and G. Pensl; Mater. Sci. Forum 483-485 (2005), 559-562.

13. SiC/SiO2 Interface States: Properties and Models, V.V. Afanas’ev, F. Ciobanu, S. Dimitriev, G. Pensl and A. Stesmans; Mater. Sci. Forum 483-485 (2005), 563-568.

14. Low Density of Interface States in n-type 4H-SiC MOS Capacitors Achieved by Nitrogen Implantation, F. Ciobanu, G. Pensl, V.V. Afanas’ev, A. Schöner; Mater. Sci. Forum 483-485 (2005), 693-696.

15. SiC material Properties, G. Pensl, F. Ciobanu, T. Frank, M. Krieger, S. Reshanov, F. Schmid, M. Weidner; SiC materials and devices, eds. S. Shur, M. Levinshtein and S. Rumyantsev, published in I.J. High Speed Elec. Sys. (2005) in press.

16. Electrical and optical characterization of SiC, G. Pensl, F. Ciobanu, T. Frank, D. Krimse, M. Krieger, S. Reshanov, F. Schmid, M. Weidner, T. Oshima, H. Itoh, W.J. Choyke; ICMAT Proceedings (2005), in press.

17. Defect-engineering in SiC by ion implantation and electron irradiation, G. Pensl, F. Ciobanu, T. Frank, D. Kirmse, M. Krieger, S. Reshanov, F. Schmid, M. Weidner, T. Oshima, H. Itoh, W.J. Choyke; Microel. Eng., in press.

18. Nitrogen implantation - an alternative technique to reduce traps at SiC/SiO2- interfaces, F. Ciobanu, T. Frank, G. Pensl, V. Afanas'ev, S. Shamuilia, A. Schöner, T. Kimoto; Mater. Sci. Forum (2006), in press.

Acknowledgment

I wish to express my gratitude to all the persons who helped me finishing

this work. Especially the following persons are acknowledged:

- Dr. Gerhard Pensl for giving me the opportulity to start the PhD in

Erlangen, for his support and kind supervising. Not last, for teaching

me the colloquial written English and, sometimes, the secrets of the

semiconductor phyisics.

- Prof. Dr. Max Sxhulz, former head of the department, and Prof. Dr.

Heiko Weber, the actual one, for the possibility to carry out the PhD

stage at the Institute of Applied Physics in Erlangen.

- Prof. Dr. Martin Hundhausen for co-reffering the present work.

- Prof. Dr. Valeri Afanas’ev (University of Leuven, Belgium) for the

inspiring and constructive discussion about the MOS structure, for

all the friendly advices and for the fruitfull collaboration. Also for

supplying me with material for part of the results in this work.

- Dr. Adolf Schöner (ACREO, Sweden), Prof. Dr. L. Ley, Dr. Thomas

Seyller, Dr. K.Y. Gao (Uni-Erlangen), Prof. Dr. Andre Stessmans

(University of Leuven, Belgium) Prof. Dr. Sima Dimitrijev and Dr.

Kwan Yew Cheong (Brisbane University, Australia), Prof. S.

Campbell (University of Minnesota, Minneapolis-USA) Prof. H.

Nagasawa (HAST Co., Japan) and Prof. Dr. Tsunenobu Kimoto

(Kyoto University, Japan) for providing me with samples and for

collaboration.

- Dr. Michael Baßler, Dr. Michael Weidner, Dr. Oliver Kletke, Dr.

Michael Krieger, Dr. Thomas Frank, Hicham Chariffi, Dr. Kin-Kiong

Lee and Dr. Negoro, for being, at time, friendly and stimulative

roommate and for all their help and willingness.

- The colleagues Dr. Dieter Karg, Dr. Changquing Chen, Dr. Kai

Christiansen, Jürgen Gajowski, Dr. Holger Grünleitner, Dr. Hans

Heißenstein, Dr. Christian Manke, Dr. Horst Sadowski, Dr. Konrad

Schneider, Dr. Norbert Schulze, Dr. Kurt Semmelroth, Dr. Sergey

Reshanov, Dr. Frank Schmid, Daniel Secker, Dr. Svetlana

138

139

Beljakova for the pleasant co-work, support and sharing of their life-

experience during the coffe breaks, etc.

- Willi Rösch, for the “fast” and precise impplatation of samples, Fritz

Hofmann, for providing the cooling liquids, and for advice on fixing

bicycle-stuff, work-shop master Roland Sagner, Bernd Prrtz and the

co-workers, for fast and competent execution of various part for the

experimental set-ups.

- The secretaries Gabrielle Loy, Angelika Karmann and Elke

Reinhard for all the assistance and support, for the management of

the Institute’s complex tasks.

- Cleanning-ladies Petra Pawlicki, Rosemarie Nüssel and Ute Bader,

for the (literally) clean atmosphere in the Institute.

- My parents who encouraged me permanently to pursue and go on

to the target.

- Especially my wife Laura for all the love, patience and

understanding.

I thank to all the others, not mentioned here, who contributed to my work.

Last but not least, the financial support for my PhD stage in Erlangen from

various German institutions, foundation or ministeries is gratefully acknowledged.

Lebenslauf

Name Florentin Marian Ciobanu

Geburtsdatum 30. April 1971

Geburtsort Bukarest

Familienstand verheiratet, keine Kinder

Schulbildung:

1977-1985 Elementarschule Nr. 143, Bukarest

1985-1989 GHEORGHE LAZAR Gymnasium Bukarest

Juni 1989 Allgemeine Hochschulreife

Okt. 1989- Wehrdienst

März 1990

Hochschulstudium:

1990-1995 Studium der Physik an der Universität Bukarest

Juni 1995 Lizenzprüfung

2000-2005 Promotionsstudium Physik und Tätigkeit als wissenschaftlicher

Angestellter am Lehrstuhl für Angewandte Physik, Universität

Erlangen-Nürnberg

Documents

Determination of electrically active traps at the