Digital Signal Processing, Cellular Automata, and Parallelism

Digital Signal Processing DevicesBy : M.R. ChitSaz S.Instructor: Dr. S.M. FakhraiSpring 91

TI int. TI DSP DSP DSP 2DSP [1] Digital Signal Processing Real Time ( ) :

3Off-line processingThe entire input signal resides in the computer as the same time.All of the information is simultaneously available to the processing program. Example : medical imaging, such as computed tomography and MRI.PC and mainframes.On-line processingThe output signal is produced at the same time that the input signal is being acquired. E.g. telephone, radar, hearing aids.Real-time applications must be have the information immediately available,although it can be delayed by a short amount.Real-time applications is input a sample, perform the algorithm, and output a sample, over-and-over.This is the world of Digital Signal Processors.The difference between DSP and CPU: DSP processor is possible to do several accesses to memory in a single instruction cycle. i.e., DSP processor have a relatively high bandwidth between their Core CPU and memory.DSP processor are optimized to cope with repetition or looping of operations common in signal processing applications.DSP allows specialized addressing modes, such as indirect,circular, and bit reverse addressing. These are efficient addressing mechanisms to implement many signal processing algorithms.

3 [4]DSP

4A Typical DSP System[1] DSP () DSPMEMORYADCPORTSDAC

55[1] DSPA = B*C + DMultiply, Add, and AccumulateE = F*G + A... MAC1+2 = 3+0001001000115*3 = 15 70 . MAC0101xxxx84210011001100110011xxxx0000 0011 0000 0011=53

Architecture:MAC: Circular buffer: RISC based: single clock per instructionHarvard Architecture: separate instruction & data

6Architecture features added to speed up this problemMAC: multiply & accumulator, speedup FIR tapCircular buffer: speedup shifting FIR delay registersRISC based: single clock per instructionHarvard Architecture: separate instruction & dataWord orientatedDisadvantages (not a general purpose computer)slow character processingNo multi-user operating system supportNo virtual memory, no translate look side tablesNo memory page protection (Read, Write, Execute)6[1] MRI

7[5]

8 [3]

9[3] (ANC) DSP

10 [3]Noise sourceANCPrimary noise3. ErrorMicrophone 2. CancelingLoudspeaker1. ReferenceMicrophonee(n)y(n)x(n)

11 [3]

12TI in Europe[1]

European Business CentersManufacturing SitesEuropean Distribution CenterCustomer SupportALMELOFREISINGNICENORTHAMPTONIsraelTel Aviv

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TemperaturePressurePositionSpeedFlowHumiditySoundLightIdentificationThe RealWorld

Amplifier# 1

DataConverter# 2

Power Management# 1

Logic# 1

EmbeddedProcessing# 3

Amplifier# 1

DataConverter# 2

Interface# 1

Low Power RF

TI supports the entire signal chain[1]

14DSP[1] TI DSP SOC Leadership CMOS Process & Manufacturing TechnologyChip CreateC2000 DSPMotor Control DSP

C5000 DSP

Personal DSPBroadband Infra-structure DSPC6000 DSP

eXpressDSP Real-Time Software TechnologyWirelessBroad-bandEEEs

(EmergingEndEquipments)

15TMS320 Family[1]16-Bit Fixed Point Devices

C1xHard-Disk Controllers

C2xFax Machines

C2xxEmbedded Control

C5xVoice Processing

C54xDigital CellularPhones

C6x

32-Bit Floating Point Devices

C3xVideophones

C4xParallel Processing

Other Devices

C67xAdvanced VLIW Processor Wireless Base Stations/Pooled Modems/DSLBest DSP of 2001

C8xVideo Conferencing

C8x multiprocessor DSPs

16VLIW (very long instruction word)Advantages of VLIW architecturesIncreased performance.Better compiler targets. Potentially scalable.Disadvantages of VLIW architecturesIncreased memory use.High power consumption.Misleading MIPS ratings.

TMS320C6000 familyFixed-Point C6X DSP:TMS320C62X,TMS320C64X.Floating-Point C6X DSP:TMS320C67X.TMS320C6418Up to 4800 Million Instructions Per Second (MIPS) at a clock rate of 600 MHzCan produce 4 16-bit Multiply Accumulates (MACs) per cycle, making 2400 Million MACs per Second (MMACS) OR8 8-bit MACs per cycle for a total of 4800 MMACSPooled ModemsWireless local loop base stationsRemote Access Servers(RAS);Digital Subscriber Loop (DSL) systemsCable modemsMultichannel telephony systems

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DSP Texas Instruments : Spring 89+++++++++++++++++++++++++++++++++++++++++

16 DSP C64x [1]

C62x Fixed-PointDSP GenerationC64x Fixed-PointDSP GenerationC67x Floating-PointDSP GenerationClock Rate(MHz)MIPS/MFLOPS16-bit MMACS8-bit MMACSBroadbandCommunicationsImaging150-300600-1100150-1671200-2400 MIPS4800-8800 MIPS600-1000 MFLOPS300-6003400-4400300-333300-600GeneralGeneral4800-8800Special-purposeInstructionsSpecial-purposeInstructions300-333GeneralGeneral17millions of operations per second (MOPS) millions of floating-point operations per second (MFLOPS)17C64x [1]

18[1] The tools for three stages:1.Algorithms development:Textual-based tools:C and Assembly.MATLAB with DSP toolboxes.2.System-level design:MATLAB and simulink DSP toolboxes.RIDE or VAB rapid tool. 3.Hardware and embedded software implementation:Code Composer Studio (CCS) with developers kit for TI C6x EVM.RIDE with DSP board from third-party of DSP venders.VAB with TI or third-party DSP board.

19[2]

20 [2] 587MHz at 1.0V (113mW) 3.6MHz at 0.34V (720W) C64x (in last gen. Peak Power (0.13micron):12.38W at 1.2 GHz)28nm SOC 32bit ULP cell

21The ultra-low-K dielectric dual damascene metal stack includes athick top Cu level and an Al level that can be used for power and signal routing.Soc=> multi-Vt, multi-channel length, analog and I/O transistors, capacitorsand diodescustom 0.12m2 6T SRAMLow vdd, Vt variation is important---------------------------------------NEW LOW POWER C64XProcessor MHz W MEM INTEGER MEM/W INT/WTMS320C6474 (one core only) 1000 2.05 5.758 7.281 2.803 3.545TMS320C6472 (one core only) 500 0.60 2.880 3.634 4.776 6.027MPC8560 (PQ3) 660 6.40 2.869 2.012 0.448 0.314Intel Celeron (Coppermine) 638 20.00 2.922 2.515 0.146 0.126------------------------------------------------------

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[2]22- a custom digital cell library is developed- Selective adjustment of transistor sizes( beta ratio)- ULV SRAM with 6T bit-cell, hierarchical sensing, wordline boosting, and pre-readduring writeall clock cells are restricted to drive strengths of 8 or higher. The area impact ofthese drive-strength increases was less than 5%.

22 www.ti.com Nathan Ickes,Gordon Gammie, Mahmut E. Sinangil,Rahul Rithe, A 28 nm 0.6 V Low Power DSP for Mobile Applications , IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 1, JANUARY 2012DESIGN OF SINGLE-CHANNEL FEEDFORWARD ACTIVE NOISE CONTROL SYSTEM, United Arab Emirates UniversityCollege of EngineeringGraduation Projects Unithttp://bear.ces.cwru.edu/ecmp_488/ berkeley uni. DSP markethttp://www.byclb.com/TR/Tutorials/dsp_advanced/ch4_1.htm

2323

Input Mic

Error Mic

Disturbance Speaker

Control Speaker

Amplifier

A/D

Power Amplifier

D/A

DSP

Amplifier

A/D