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Ph. D. DISSERTATION
Analysis of Random Telegraph
Noise Characteristics in Memory
Devices (SRAM, DRAM, Flash)
여러 가지 메모리 소자에서의 RTN 특성 분석
(SRAM, DRAM, Flash)
BY
Youngsoo Seo
August 2019
DEPARTMENT OF ELECTRICAL AND
COMPUTER ENGINEERING
COLLEGE OF ENGINEERING
SEOUL NATIONAL UNIVERSITY
Analysis of Random Telegraph
Noise Characteristics in Memory
Devices (SRAM, DRAM, Flash)
여러가지 메모리 소자에서의 RTN 특성 분석
(SRAM, DRAM, Flash)
지도 교수 신 형 철
이 논문을 공학박사 학위논문으로 제출함
2019 년 8 월
서울대학교 대학원
전기컴퓨터공학부
서 영 수
서영수의 공학박사 학위논문을 인준함
2019 년 8 월
위 원 장 김 상 범 (인)
부위원장 신 형 철 (인)
위 원 임 준 희 (인)
위 원 홍 규 식 (인)
위 원 강 명 곤 (인)
ABSTRACT
In this thesis, Random Telegraph Noise (RTN) effect, which is one kind of device noise,
is analyzed in various memory devices (SRAM, DRAM, Flash). Basically, RTN is caused
by trapping/de-trapping phenomenon of electron in the trap of the device over time,
causing a change in current and threshold voltage of the device. This phenomenon causes
various reliability problems in the memory device. In particular, it reduces noise margin
in SRAM, causes the Variable Retention Time (VRT) phenomenon in DRAM, and
changes the threshold voltage in Flash.
In a six-transistor of SRAM, the noise margin is defined as the maximum square size in
the butterfly curve in Read operation. This noise margin is determined by subthreshold
swing and VT mismatch of Pull UP (PU) and Pull Down (PD), and resistance difference
between Pass Gate (PG) and PD. In the case of RTN trap in any combination of SRAM
devices, we analyzed whether the VT mismatch and the resistance difference were the
largest and the noise margin was reduced to the maximum. In addition, we analyzed the
RTN effect with various variability sources.
The retention time of the DRAM cell is affected by the gate induced drain leakage
(GIDL) current generated in the overlap region of the gate and the drain. This GIDL
current changes with time due to the RTN phenomenon, which causes the VRT of the
DRAM cell. In order to understand the VRT phenomenon accurately, understanding the
physical characteristics of the trap that causes the GIDL RTN must be understood, and
researches have been carried out in many groups. However, in various papers, it could not
consider the electric field and analyzed the trap characteristics using the wrong formula.
ii
In this paper, we have studied the characteristics of the traps more accurately by
considering the electric field enhancement factor. This study will be helpful for
understanding the VRT phenomenon of DRAM.
In the 3D NAND, since the channel material is formed of polysilicon, the reliability
problem of the device due to arbitrarily formed Grain Boundary Trap (GBT) is a big issue.
Especially, because the channel current does not flow uniformly, the RTN effect becomes
more important reliability problem in the continuously decreasing device structure. In this
thesis, we analyze the effect of RTN on various situations (RTN trap location,
temperature, device miniaturization, GBT density, etc.) and help to predict RTN effect on
VT fluctuation in macaroni-type 3D NAND Flash memory.
Keywords : RTN, Trap, Read Static Noise Margin (RSNM), SRAM, Variable Retention
Time (VRT), DRAM, 3D NAND.
Student number : 2013-20799
iii
CONTENTS
Abstract ------------------------------------------------------------------------ i
Chapter 1. Introduction
1.1. What is Random Telegraph Noise? -------------------------------1
1.2. Impact of RTN in memory devices ---------------------------------3
Chapter 2. Impact of RTN in Bulk FinFET on the Stability of
SRAM Cells [SRAM]
2.1. Introduction ------------------------------------------------------------6
2.2. Results and Discussion -----------------------------------------------7
2.3. Summary -------------------------------------------------------------- 13
Chapter 3. Extraction of Distance between Interface Trap and
Oxide Trap from RTN in Gate-Induced Drain Leakage [DRAM]
3.1. Introduction ---------------------------------------------------------- 14
3.2. Results and Discussion --------------------------------------------- 15
3.3. Summary ------------------------------------------------------------- 27
iv
Chapter 4. Prediction of RTN Effect on VT Fluctuation in
Macaroni-type 3D NAND Flash Memories [Flash]
4.1. Introduction ---------------------------------------------------------- 29
4.2 Simulation Structure and Methodology --------------------------- 32
4.3. Results and Discussion --------------------------------------------- 35
4.4. Summary ------------------------------------------------------------- 47
Chapter 5. Conclusion------------------------------------------------------ 50
Appendix A. Improving BSIM Flicker Noise Model -----------------
A.1. Introduction --------------------------------------------------------- 52
A.2. Advanced Flicker Noise Model ---------------------------------- 53
A.3. Results and Discussion -------------------------------------------- 56
A.4. Conclusion ---------------------------------------------------------- 64
Abstract in Korean -------------------------------------------------------- 65
List of Publications -------------------------------------------------------- 68
-1-
Chapter 1
Introduction
1.1 What is Random Telegraph Noise?
Random Telegraph Noise (RTN) is a type of electronic noise that occurs in
semiconductor device. It is also called burst noise, popcorn noise, impulse noise, bi-stable
noise, or random telegraph signal (RTS) noise. In Fig. 1, when one trap captures electrons
from the inverted channel, the electrons involved in the current flow are reduced by one.
The trap also becomes charged and reduces channel carrier mobility due to the effect of
coulomb scattering. Due to the capture and emission of the charge, both carrier number
and mobility are fluctuated. In particular, there is only one active trap at a given bias
condition in a device with very small length and width. In this case, the drain current
fluctuates between high and low current levels with a certain average period as shown in
Fig. 2.
Fig. 1.1. Capture/emission of single electron in mosfet device and energyband diagram.
- 2 -
Fig. 1.2. RTN waveform in time domain by single trap.
The RTN phenomenon can be observed not only in the oxide trap but also in the silicon
insdie trap, and is a very important factor in analyzing the device variation due to the
randomly generated trap in the process and after the stress. Fig. 3 shows the drain current
with time when there are multiple rtn traps. As the number of traps increases, the current
level increases.
Fig. 1.3. RTN waveform in time domain by multiple traps.
- 3 -
1.2 Impact of RTN in memory devices
The RTN phenomenon causes current and threshold voltage fluctuations of the device,
which causes various reliability problems of the memory device. In SRAM, the noise
margin is affected by the VT mismatch of the pull up and pull down transistor and the
resistance difference of the pass gate and pull down transistor. Fig. 4 shows the SRAM
butterfly curve and noise margin. Because the noise margin is degraded by the RTN trap,
the RTN characteristics should be considered when designing the VT of transistors in
SRAM cell.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Trap empty
(RSNM : 134.5 mV)
Worst-Case
(RSNM : 127.5 mV)
VDD
= 0.7 V, b = 2
@ 375K
Vout [V
]
Vin [V]
Fig. 1.4 Butterfly curves without trap and with trap, the VT design window considering
RTN phenomenon.
- 4 -
Fig. 1.5 Retention time with respect to time
In DRAM cell which consists of 1 access transistor and 1 storage capacitor, the
retention time should be longer than standard refresh time. However, the retention time of
the DRAM cell is not constant but varies with time as shown in Fig. 5, and this
phenomenon is a very important reliability problem in a DRAM cell called variabile
retention time. The cause of the VRT phenomenon is the variation of the GIDL current of
the device in the off state by the RTN trap. The mesurements of RTN waveform can be
used to analyze the characteristics of traps affecting GIDL current and to extract the
parameters using various equations.
- 5 -
Fig. 1.6 1-Cumulative probability of ΔVT by randomly located RTN trap.
For the normal operation of 3D NAND flash memory, an important factor to consider
is the VT distribution of the devices. Among the various factors, VT fluctuation by the
RTN trap has a time-dependent characteristic, so it has a great influence even after
reduction of VT distribution by ISPP. Fig. 6 shows the 1-cumulative probability of ΔVT
depending on the location of the RTN trap randomly distributed in the channel/oxide
inteface of the 3D NAND. After analysis of the relationship between the RTN effect and
the current percolation path due to the grain boundary, temperature, and the device
scaling, the VT distribution of the next generation can be predicted.
- 6 -
Chapter 2
Impact of RTN in Bulk FinFET on the Stability of
SRAM Cells [SRAM]
Mixed mode TCAD simulation using hydrodynamic transport model was performed
for SRAM cell composed of 90Å silicon Bulk-FinFET. In case of worst-case trapping
combination in SRAM, read static noise margin (RSNM) is reduced by 4.3% @300K and
5.2% @375K compared to the case with empty trap. In addition, the RTN effect on
SRAM is analyzed considering statistical variability including work function variation
(WFV), random dopant fluctuation (RDF), and line-edge roughness (LER).
2.1 Introduction
Recently, FinFET device has been researched as an alternative to planar device
because of its good gate controllability. Especially, Bulk-FinFET is better than SOI
FinFET due to lower wafer cost & substrate defect density, higher performance & heat
transfer rate and scalability [1-2]. Besides, as device size is scaled down, the effect of
random telegraph noise (RTN) becomes more significant in determining the device
performance and reliability [3]. In addition, work function variation (WFV), random
dopant fluctuation (RDF), and line-edge roughness (LER) variations have strong effect on
- 7 -
the stability of SRAM cell [4]. Because of VT mismatch between NFET and PFET due to
these issues, static noise margin(SNM) of SRAM is reduced, and minimum voltage for
stable SRAM operation is also reduced. This thesis investigates minimum operation
voltage of 6T-SRAM composed of 90Å Bulk-FinFET considering RTN effect,
temperature effect, and variability.
2.2 Results and Discussion
2.2.1 Device setup
Fig. 1 shows the schematic of a conventional 6T SRAM cell. Device dimensions for
90Å Bulk-FinFET from ITRS 2012 were used [5]. Optimization of device parameters was
performed to maximize RSNM. The S/D doping is 5x1019 cm-3 and channel doping is 1017
cm-3. And local doping of 1018 cm-3 is assumed to obtain better sub-threshold slope for
higher SNM. The width of pull down transistor is two times larger than other transistors
(β=2). With adjusting gate work function, each VT of NFET and PFET was set to be 0.35
V. Fig. 2 shows the mobility, electron density, electric field and I-V curve without trap
and with trap for 90Å Bulk-FinFET. When the RTN trap is filled, the mobility, electron
density, current decrease and the threshold voltage increases.
- 8 -
FinTraps
Bulk FinFET
Lg 9 nm
EOTSiO2 0.6 nm / HfO2 1 nm
Hfin 12.5 nm
Wfin (bottom/ middle/top)
5/4/3 nm
Channel Doping
1017 cm-3
S/D Doping 5x1019 cm-3
LDD Doping 1019 cm-3
Local Doping 5x1018 cm-3
Fig 2.1. 6T-SRAM cell and each transistor’s Fin shape.
VGS = 0.25 VZT = 0.5 nm
y
z
Hfin
Wfin
Without trap
Sliced at the middle region between S/D
With trap
5 4 3 2 1 010
-2
10-1
100
101
102
Trap Filled
Trap Empty
E-F
ield
[M
V/c
m]
Distance from Trap [nm]5 4 3 2 1 0
106
108
1010
1012
1014
1016
Trap Filled
Trap Empty
e-d
ensi
ty [
/cm
3]
Distance from Trap [nm]
VGS
= 0.25 V
ZT = 0.5 nm
5 4 3 2 1 010
0
101
102
103
104
VGS
= 0.25 V
ZT = 0.5 nm
Trap Filled
Trap Empty
e-m
obility [
cm2/V
s]
Distance from Trap [nm]
ü E-Field, e-Mobility, Carrier number, VT, ID
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710
-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
Trap Filled
Dra
in C
urre
nt [m
A]
VGS
[V]
Dra
in C
urr
ent
[A]
Trap Empty
VDS
= 0.05 V
ZT = 0.5 nm
0
2
4
6
8
10
Fig 2.2. The mobility, electron density, electric field and I-V curve without trap and
with trap
- 9 -
2.2.2 RSNM Considering Oxide Trap and Temperature
After device optimization, the RSNM extracted from butterfly curve in Fig. 3 is 152
mV at VDD=0.7 V & 300K. Fig. 4 shows change in butterfly curve when electrons are
trapped in the gate oxide of FinFETs in SRAM. Considering symmetry, four worst-case
traps are listed in the table [6]. For these four worst-cases, RSNM is 145.5 mV which
corresponds to 4.3% reduction compared to the case with an empty trap. The temperature
characteristic in SRAM must be considered. Fig. 5 shows RSNM at different
temperatures for empty trap and worst-case trapping. As temperature increases, RSNM is
reduced since the characteristic of sub-threshold slope gets worse. As for worst-case trap
at 375K, RSNM is 127.5 mV which corresponds to 5.2% reduction compared to the case
with an empty trap.
Fig 2.3. Butterfly curve in read mode. The threshold -voltage of NFET and PFET are
same.
- 10 -
Fig 2.4. Butterfly curves without trap and with trap. The combinations of trap are
shown in table for worst -case RSNM.
- 11 -
Fig 2.5. RSNM at different temperatures. The minimum RSNM is 127.5 mV.
2.2.3 Variability (WFV, RDF, LER)
Fig. 6 shows butterfly curves with WFV+RDF+LER for 1000 samples. As for
WFV(grain size=20Å ), models for TiN(4.4~4.6 eV) and TiN+Al(4.64~4.84 eV) were
applied to each NFET and PFET [7], and Gaussian correlation function(λ=100 Å , 3σ=7.2
Å ) was used for LER model. Fig. 6 shows the histograms of RSNM at VDD=0.7 V with
worst-case trap & at 375K & with WFV+RDF+LER.
- 12 -
40 80 120 160 200 2400.00
0.05
0.10
0.15
0.20
s(RSNM_Trap Empty
)=21.6 mV
s(RSNM_Worst-Case
)=21.0 mV
With WFV+RDF+LER
@ VDD
=0.7 V, b=2, 375 K
m(RSNM_Trap Empty
)
= 100.7 mV
m(RSNM_Worst-Case
)
= 93.2 mV
Pro
babilitie
s
RSNM (mV)
Trap empty
Worst-Case
Fig 2.6. Butterfly curve variation and probabilities of RSNM with WFV, RDF, LER for
1000 samples.
- 13 -
2.3 Conclusion
This chapter investigated the RTN effect on RSNM of 6T-SRAM composed of 90Å
Bulk-FinFET. Considering worst-case trapping combination RSNM is reduced by 4.3% at
300K and 5.2% at 375K. In addition, when variability sources such as WFV, RDF and
LER are considered, the RTN effect on RSNM of SRAM still remains.
References
[1] C.R Manoj, et al., “Device Design and Optimization Considerations for Bulk
FinFETs” IEEE TED, vol.55, pp.609-615, 2008.
[2] K. Okano, “Process integration technology and device characteristics of CMOS FinFE
T on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length” IEDM, 2005.
[3] Campbell, J.P, et al., IEEE IRPS, pp.382-388, 2009.
[4] Natalia S, et al., IEEE TED, “Random Dopant, Line-Edge Roughness, and Gate
Workfunction Variability in a Nano InGaAs FinFET” vol.61, pp466-472, 2014.
[5] International Technology Roadmap for Semiconductors (ITRS2012):www.itrs.net/Lin
ks/2012ITRS/Home2012.htm
[6] M.L Fan, “Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET
Devices, 6T SRAM Cell, and Logic Circuits” IEEE TED, vol.59, pp.2227-2234, 2012.
[7] H.W Cheng et al., “3D device simulation of work function and interface trap
fluctuations on high-κ/metal gate devices” IEDM, 2010.
- 14 -
Chapter 3. Extraction of Distance between
Interface Trap and Oxide Trap from RTN in Gate-
Induced Drain Leakage [DRAM]
3.1 Introduction
As the size of an electronic device is scaled down, the effects of the random telegraph
noise (RTN), which is caused by a single oxide trap, seriously affects the reliability of the
device. In particular, the RTN in the gate-induced drain leakage (GIDL) produces a
variable retention time (VRT), which has a considerable influence on the retention
characteristics of dynamic random access memory (DRAM) cells.1 In DRAM cell
transistors, RTN occurs as a result of the variation in the electric field at the Si/SiO2 as
electrons are trapped and de-trapped at the oxide trap.2_ 3 The GIDL current mostly
occurs via band-to-band (BTB) or via trap-assisted tunneling (TAT).4 As operation
voltage is scaled down, the TAT mechanism which is dominant in low field region is
being more important to analyze than the BTB mechanism. The TAT current can be
modeled at a low field (F < 0_9 MV/cm) and at a high field (F > 0_9 MV/cm).5 However,
most of the previous research on the characterization of the TAT GIDL has been
- 15 -
performed considering only the low field model, even when the field is larger than 0.9
MV/cm. Therefore, an accurate equation must be used to conduct a precise analysis of the
TAT mechanism related to the RTN. This paper presents the equations that were used to
analyze the leakage current fluctuations in a high field TAT region. We accurately
extracted the distance r between the interface trap and the oxide trap by using the
equations and the measured data from the MOSFET device, considering the correct field
enhancement factor __F _ that depends on the field at the Si/SiO2 interface. These
analyses offer an understanding of the physical characteristics and of the relationship
between the two traps that cause an RTN in the TAT GIDL.
3.2 Results and Discussion
For the experiment, a MOSFET device with an oxide thickness of 6.9 nm and a gate
length of 250 nm was used. We monitored the currents of all the terminals both in the
time and frequency domains. The experimental set-up used to measure the RTN is
comprised of an SR570 low noise amplifier (LNA), B1500A semiconductor parameter
analyzer, and an HP35670A dynamic signal analyzer. The SR570 LNA amplifies the
drain current and converts it to a voltage. We then used the HP35670A to observe the
behavior of the low-frequency noise both in the time and in the frequency domains. For
this measurement, all of the terminals except for the drain were biased to 0 V. This bias
- 16 -
condition was selected in order to ignore leakage currents other than the gate-induced
drain leakage (GIDL) current.
SiO2
Si
er
g-r site(fast state)
capture-emission site (slow state)
Fempty
ΔF
Ffilled
n n
p
gate
xT
3.10 3.15 3.20 3.25 3.30-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
ln (
t c/t e
)
VDG
[V]
Slope = 13.11
(a)
(b)(c)
0
1
1
1
1
2
1
2 VDG
= 3.3 V
VDG
= 3.25 V
VDG
= 3.2 V
VDG
= 3.15 V
GID
L C
urr
en
t [p
A]
Time [5 sec/div]
VDG
= 3.1 V@ 318K
@ 318K
@ 318K
@ 318K
@ 318K
(a)
SiO2
Si
er
g-r site(fast trap)
capture-emission site (slow trap)
Fempty
ΔF
Ffilled
n n
p
gate
xT
Fig. 3.1 (a) Cross section of the n-MOSFET with two traps interacting with each other.
(b) Measured time-domain drain leakage current at 318 K with an increase in VDG. (c)
Ratio of τe ,τc with an increase in VDG.
- 17 -
Fig. 1(a) shows the cross section of the n-MOSFET. The two traps interact with each
other and generate the RTN. The fast trap is a generation-recombination site. On the other
hand, the slow trap is an electron capture-emission site. In this figure, Fempty represents the
electric field for the fast trap due only to the device bias, and ΔF represents the additional
field due to electron trapping in the slow trap.
When the slow trap is filled with an electron, the field at the fast trap increases from
Fempty to Ffilled, and the TAT leakage current increases. Fig. 1(b) shows the RTN measured
in the drain leakage current with an increase in VDG. Fig. 1(c) shows the ratio of the
emission time (τe) to the capture time (τc) as a function of VDG. With the slope of the line,
we can calculate the distance between the slow state and Si/SiO2 interface (xT) and
ECox-ET by using the extracting method described in [6]. The extracted value of xT is
0.68 nm and ECox-ET is 3.9 eV.
In addition, the activation energy of the TAT current was extracted to be 0.54 eV, as
shown in Fig. 2. This value was used to obtain the energy level of the fast trap (EC-ET),
which is equal to 0.45 eV7. These values can then be used to obtain the distance between
the fast state and the slow state (r). The measured current mainly flows through the TAT
mechanism because the activation energy of GIDL is large and the electric field is just 1.5
MV/cm which corresponds to VDG=3.2 V. Therefore the BTB mechanism is negligible.
- 18 -
Fig. 3.2. The TAT GIDL current with 1/kT. The activation energy of the TAT current was
extracted as 0.54 eV.
))F(Γ+1(I=I SRHTAT (3.1)
)kT
EEexp(nσqv=I
itithSRH
- (3.2)
- 19 -
In Hurkx model5, the TAT current is calculated by Eq. (1). The field enhancement
factor Γ(F) is calculated by Eq. (3) or Eq. (4) according to the amplitude of electric field.
However, in previous studies7,8, the TAT current (Eq. 1) was described according to the
Γ(F)Low_Field in Eq. 3, covering all of the electric field to extract the inter-trap distance.
If we use the low field equation (Eq. 3) for all of the electric field, large error can be
generated, especially above 0.9 MV/cm. Therefore, the Eq. (4) in Hurkx model should be
used when the field is larger than 0.9 MV/cm. ΔE is fast trap’s energy level(EC-ET)
which is equal to 0.45 eV
])F
Fexp[(
F
Fπ32=)F(Γ 2
ΓΓField_Low (3.3)
hq
(kT)24mF
3*
Γ =
)a
berfc(c)
a
bexp(
a
π
kT
ΔE
2
1=Γ(F)
2
High_Field - (3.4)
,hq
ΔE2m
3
4 ,
kT
ΔE-
F
1αc ,
F
10.75α-
2kT
ΔEb,
F
10.375a
3*
=a==a=
- 20 -
0.0 0.5 1.0 1.5 2.0 2.5 3.010
0
101
102
103
104
105
106
107
Cross Point (F=0.9 MV/cm)
m=0.34mo, DE=0.45eV
G(F)Low Field eq.
G(F)High Field eq.
G(F
)
Field [MV/cm]
Fig. 3.3. Γ(F) equation plot. The low & high field Γ(F) are crossed at F=0.9 MV/cm.
Fig. 3 shows the Γ(F) using a low field and a high field equation as a function of the
field. The two curves are crossed at F=0.9 MV/cm. When the field is lower than 0.9
MV/cm, Γ(F)Low_F should be used, and when the field is larger than 0.9 MV/cm, Γ(F)High_F
should be used. Fig. 4 shows the electric field Ffilled as a function of r with different xT,
and Ffilled can be calculated by using Eq. (5)8.
r
xFΔF2+)FΔ(+)F(=)F( T
empty22
empty2
filled (5)
- 21 -
(b)
1.0 1.5 2.0 2.5 3.0 3.5
0.6
0.8
1.0
1.2
1.4 Fempty=0.75 [MV/cm]
xT=0.5 nm
xT=1.0 nm
xT=1.5 nm
Ffi
lle
d [
MV
/cm
]
r [nm]
use G(F)Low Field eq.
use G(F)High Field eq.
1.0 1.5 2.0 2.5 3.0 3.5
0.6
0.8
1.0
1.2
1.4
use G(F)High Field eq.
use G(F)Low Field eq.
Fempty=0.6 [MV/cm]
xT=0.5 nm
xT=1.0 nm
xT=1.5 nm
Ffi
lled [
MV
/cm
]
r [nm]
(a)
Fig. 3.4. Field at the interface with respect to the distance between the oxide trap and
the interface trap. (a) Fempty=0.6 MV/cm (b) 0.75 MV/cm.
- 22 -
Even when Fempty is lower than 0.9 MV/cm, Ffilled can be larger than 0.9 MV/cm if the
slow trap becomes close to the fast trap. In this case, Ifilled should be calculated with
Γ(F)high_F even though Iempty is calculated with Γ(F)Low_F. Fig. 4 shows that the value of r
that makes Ffilled be larger than 0.9 MV/cm increases with a larger Fempty and xT.
Eq. (6) are the equations for Ifilled/Iempty for a different field. Each equation is modeled
by using the Eq. (3,4) considering the amplitude of electric field.
MV/cm)0.9F&(F
)F
FFexp(
F
F
)Γ(F
)Γ(F
I
I
filledempty
emptyfilled
empty
filled
empty
filled
empty
filled
<
=»G
-
(6.a)
MV/cm)0.9F&(F
e)3e(1
)3e(1
a'
a
I
I
filledempty
(c'-c)-
/3a)2(-b
)/3a'2(-b'
empty
filled
>
+
+=
(6.b)
])F
Fexp[(
)e3e(1
F
F
a'
1
kT324
ΔE
I
I
2
Γ
empty
c'-)/3a'2(-b'Γ
empty
filled +=
(6.c)
MV/cm)0.9>(F
MV/cm)0.9<(F
filled
empty
- 23 -
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
0
20
40
60
80
100
120
140
r =xT
xT=0.68nm, m=0.34m
o, DE=0.45eV
open: Fempty
= 0.6 MV/cm
close: Fempty
= 1.5 MV/cm
G(F')/G(F) F' >0.9 MV/cm - eq. 6(c) F' <0.9 MV/cm - eq. 6(a)
G(F')/G(F) - eq. 6(a)
G(F')/G(F) - eq. 6(a)
G(F')/G(F) - eq. 6(b)
I fille
d/I
em
pty
r [nm]
Eq. (6) is the result of approximating the error function in Eq. (4) to the exponential
function using Eq. (7)9.
/3a)24b(/a)2b( e2
1e
6
1)
a
berfc( -- +=
(7)
Fig. 3.5. Ifilled/Iempty vs. the distance between the oxide trap and the interface trap.
There is a great difference between the low and the high field Γ(F) when Fempty=1.5
MV/cm.
- 24 -
0.5 1.0 1.5 2.0 2.5 3.0 3.51E-7
1E-6
1E-5
1E-4
1E-3
0.01
0.1
1
error function exponential function
ab /
Fig. 3.6. Comparison of error function and exponential function in Eq. 7.
Fig. 5 shows Ifilled/Iempty as a function of r with a different Femtpy. The parameter values
for xT and ΔE that were extracted from the measured data were used in Eq. (6). When
Fempty is 1.5 MV/cm, the value of Ifilled/Iempty is definitely different when using Γ(F)Low_F
and Γ(F)High_F. This is very important because the extracted r value is different depending
on which enhancement factor is chosen between Γ(F)Low_F and Γ(F)High_F. When the
distance r is smaller than 2 nm, Ffilled is larger than 0.9 MV/cm for Fempty = 0.6 MV/cm.
Therefore, Ifilled/Iempty should be calculated by using Eq. 6(a) when r > 2 nm and Eq. 6(c)
when r < 2 nm. The extracted r value should be larger than xT, as can be expected from
- 25 -
Fig. 1(a). When the value of Ifilled/Iempty is larger, the value of r that is close to xT is also
extracted when using Γ(F)High_F. However, even when Ifilled/Iempty is very large, the value of
r can’t be extracted to be close to xT when using Γ(F)Low_F. Therefore, Γ(F)high_F should be
used when Fempty > 0.9 MV/cm or Ffilled > 0.9 MV/cm.
In Fig. 7(a), the 1.5 MV/cm value for Fempty, which corresponds to VDG=3.2 V at
T=318K is obtained from TCAD simulation and was confirmed by using an analytical
equation6. The structure of device designed in simulation is equal to the measured device,
and the electric field is the value checked in the gate-drain-overlap region. The distance
between the two traps is extracted in Fig. 7(b), and in the figure, the red line represents
Ifilled/Iempty, which is equal to 4.8 when calculated using the measured data. The value of r
that corresponds to and Ifilled/Iempty of 4.8 is 1.31 nm from Eq. 6(a) and 2.16 nm from Eq.
6(b). The two values of r that are extracted have an error of 34%. Since Fempty is larger
than 0.9 MV/cm in this case, the value of 1.31 nm extracted from Eq. 6(b) is considered
to be the correct one.
- 26 -
Fig. 3.7(a). Fempty extraction using the equation6 and the device simulator. (b)
Extraction of the distance between the two traps at Fempty=1.5 MV/cm, T=318K,
xT=0.68nm, and ΔE=0.45 eV. The distance extracted from two equations has an error of
34%.
- 27 -
3.3 Summary
The measured data and the analytical equations were used to obtain the parameter
values of xT and ΔE. These values were used to find the distance between the two traps.
For the first time, the high field enhancement factor Γ(F) was considered in order to
accurately calculate Ifilled/Iempty. When calculating the r distance, it is important to use
different field enhancement factors Γ(F) depending on the field at the Si/SiO2 interface
because the value for r that is extracted is completely different depending on which factor
is used. In our case, the results of the extracted distance have an error of 34%. This
analysis provides more accurate extraction of the distance between two traps. The
amplitude of RTN which is one of the important phenomena in DRAM retention time
distribution can be predicted.
- 28 -
References
[1] M. Yuki, O. Kiyonori, O. Kensuke, Y. Ren-ichi, IEEE Electron Device Meeting, 2005.
[2] Zhongming Shi, Jean-Paul Mieville and Mi chel Dutoit, IEEE Transactions on
Electron Devices, vol. 41, no. 7, pp. 1161-1168, Jul. 1994.
[3] M. J. Kirton and M. J. Uren, Adv. Phys., vol. 38, no. 4, pp. 367-468, 1989.
[4] Minchen Chang, Jengping Lin, Steven N. Shih, Tieh-Chiang Wu, Brady Huang, Jen
Yang, and Pei-Ing Lee, IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 1036-
1041, Apr. 2003.
[5] G.A.M. Hurkx, D.B.M. Klaassen, and M.P.G Kunvers, IEEE Transactions on
Electron Devices, vol. 39, no. 2, Feb. 1992.
[6] Byoungchan Oh, Heung-Jae Cho, Heesang Kim, Younghwan Son, Taewook Kang,
Sunyoung Park, Seunghyun Jang, Jong-Ho Lee, and Hyungcheol Shin, IEEE
Transactions on Electron Devices, vol. 58, no. 6, pp. 1741-1747, Jun. 2011
[7] Heesang Kim, Byoungchan Oh, Younghwan Son, Kyungdo Kim, Seon-Yong Cha,
Jae-Goan Jeong, Sung-Joo Hong, and Hyungcheol Shin, IEEE Transactions on Electron
Devices, vol. 58, no. 6, pp. 1643-1648, Jun. 2011.
[8] Joonha Shin, Sangbin Jeon, Hyun Suk Kim, and Sung-Won Yoo, Jpn. J. Appl. Phys.,
2015
[9] Chiani, M., Dardari, D., Simon, M.K, IEEE Transactions on Wireless
Communications, vol. 2, no. 4, July. 2003.
- 29 -
Chapter 4
Prediction of RTN Effect on VT Fluctuation in
Macaroni-type 3D NAND Flash Memories [Flash]
The effect of Random Telegraph Noise (RTN) on the variation of threshold voltage in
macaroni-type 3D NAND Flash Memories was analyzed using poly-silicon based 3D
TCAD. Due to the charged traps in the grain boundary of poly-silicon channel, the current
percolation paths are formed. For this reason, the impact of RTN on crystalline silicon and
poly-silicon channel is different. As the temperature decreases or the grain boundary trap
density increases, the RTN effect increases because the trap occupancy in grain boundary
increases and the current percolation becomes stronger. Also, new facts related to RTN
characteristics of 3D NAND has been revealed. First, the RTN effect when the trap is in
the middle of the channel is greater than that at the channel/ oxide interface. The second,
as the grain boundary trap density increases, the VT fluctuation by the RTN trap increases
because the current percolation becomes stronger. In particular, the traps at deep energy
levels significantly affect the current percolation path at VG≈ VT. Finally, as the gate
length, spacer length, and channel thickness decrease, the VT fluctuation by the RTN trap
increases. As the filler oxide thickness decreases, the RTN effect increases because the
area ratio of grain boundary to channel increases.
- 30 -
4.1 Introduction
andom Telegraph Noise (RTN) in 3D NAND significantly affects the VT distribution
[1-4]. The charged trap changes the VT of the device as shown in Fig. 1(a). When the
charged trap is closer to the current percolation path formed by the grain boundary traps,
the VT changes significantly and causes a reliability problem. This effect can be severe by
large number of traps [5-7]. In particular, the poly-silicon channel with non-uniform
current density due to the randomly located grain boundary traps is affected more by the
RTN trap rather than crystalline silicon channel [8-12]. In addition, since the RTN
phenomenon is time-dependent, it has different characteristics from other variability
sources such as structure variation. The RTN effect on the VT distribution persist or
becomes even stronger when the deviation of VT is reduced after incremental step pulse
programming (ISPP) as shown in Fig. 1(b). Also, for the 3D NAND with a high number
of layers and density, the scaling of the device is essential and the variation of hole CD
must be considered. In single crystal channel, as the channel thickness decreases, the
impact of the single trap on the channel increases. However, in the case of poly-silicon
channel, as the channel thickness decreases, the area of the grain boundary also decreases,
so the RTN effect does not increase unconditionally. Recently, the RTN effect has been
studied extensively [13-14]. However, there are insufficient studies to describe the RTN
effect in macaroni-type 3D NAND based on physical mechanisms. This study analyses
the RTN effect on the VT distribution based on the trap position, the grain boundary trap
R
- 31 -
density, and the device scaling through 3D TCAD simulation.
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0
0.0
0.2
0.4
0.6
0.8
1.0
w/o RTN trap with RTN traps
Cu
rre
nt
[mA
]
Gate Voltage [V]
Cu
mu
lati
ve P
rob
ab
ilit
y
Electrontrapping
ΔVT - Single trap
Total ΔVT
(a)
0.01
0.1
1
RTN trap Empty
Filled
Cu
mu
lati
ve
Pro
ba
bil
ity
Threshold Voltage
InitialAfterISPP
(b)
P=0.01
P=0.1
Fig. 4.1. (a) The drain current for the gate voltage in the 96WLs stacked 3D NAND string.
The VT of the device is changed by the RTN traps. (b) Cumulative distribution of the VT
with and without the RTN trap.
- 32 -
4.2 Simulation Structure and Methodology
percolation
Single Trap
Current density (RTN Trap filled)
Current density
Single Trap
Single Trap
PercolationPercolationPercolation
(a)
(b)
Tfiller
LG
Tch
Fig. 4.2. Schematic of multiple WLs stacked 3D NAND flash memory. Cross-section
view of the current density when (a) the RTN trap empty, (b) the RTN trap filled.
- 33 -
(b)(a)
Si/SiO2
Grain Boundary
1-C
um
ula
tvie
Pro
ba
bil
ity
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1
1011
1012
1013
1014
1015
1016
GB
tra
p d
ensi
ty [
cm-2/e
V]
E-Ec [eV]
Deep states
Tail states
Si/SiO2 states
(EF @VG=VT)
(b)
Fig. 4.3. (a) Schematic of grain boundary in poly-silicon channel. (b) Grain boundary and
interface trap density.
Fig. 2 shows the schematic and cross-sectional view of stacked 3D NAND flash memory
- 34 -
used in 3D TCAD simulation. The current percolation path is formed by the grain
boundary traps. Fig. 2(b) shows that the current density is degraded around the RTN trap
when the single electron trapping occurs in the main current path. The reduced current
due to the RTN trap changes the VT of the device. Fig. 3 shows the schematic of grain
boundaries in the poly-silicon channel. The grain boundary trap and interface trap density
are shown in Fig. 3(b) [8]. The grain boundary trap is represented by the two exponential
functions with tail state at energy levels near the conduction band and deep state at energy
levels far away from the conduction band. Table 1 shows the device parameters for
simulation.
TABLE I Device Parameters
Device parameters Value Device parameters Value
Filler Oxide Thickness (Tfiller) (nm) 30 Channel doping (cm-3) 1016
Channel Thickness (Tch) (nm) 10 Grain Size (nm) 30
Gate Length (LG) (nm) 28 Tunneling Oxide Thickness (nm) 5
Spacer Length (LS) (nm) 28 Nitride Thickness (nm) 5
Metal Thickness (Tmetal) (nm) 40 Blocking Oxide Thickness (nm) 6
- 35 -
4.3 Results and Discussion
Fig. 4 and Fig. 5 show the 1-cumulative distribution (1-F) of ΔVT by the RTN trap for
different grain boundary trap density. The RTN trap was located 5 nm away from the
source-gate edge, which had the largest effect on the VT. Also, the RTN effect at the filler
oxide/channel interface is larger than that at the channel/gate oxide interface because the
electron density at VG=VT has a higher value inside the channel. Fig. 4(a) and Fig. 5(a)
show the 1-F of ΔVT when the RTN trap was at the filler oxide/channel interface, and Fig.
4 (b) and Fig. 5 (b) show the 1-F of ΔVT when the RTN trap was in the middle of the
poly-silicon channel. Due to the differences in the RTN trap position and the dielectric
constant between the silicon and the oxide, the graph waveforms are divided into two
types. The values of trap density specified in each figure are the maximum values of the
trap density of each state. In the case of the deep state trap density, the RTN effect
becomes larger with increased density. However, the change of the tail state trap density
does not affect the RTN effect and the 1-F of ΔVT are almost the same regardless of the
tail state trap density.
- 36 -
(b)
(a)
0 5 10 15 20 25 30
0.01
0.1
1 RTN trap @ 5nm from filler
Deep state trap
1x1012
cm-2
5x1012
1x1013
[Ref]
5x1013
1-C
um
ula
tive P
rob
ab
ilit
y
DVT [mV]
0 5 10 15 20 25 30
0.01
0.1
1 RTN trap @ filler/channel
Deep state trap
1x1012
cm-2
5x1012
1x1013
[Ref]
5x1013
1-C
um
ula
tive P
rob
ab
ilit
y
DVT [mV]
Fig. 4.4. 1-Cumulative distribution of the ΔVT by the RTN trap according to the
various deep state trap density. (a) When the RTN trap at the filler/channel interface, (b)
the RTN trap in the middle of the channel.
- 37 -
(b)
(a)
0 5 10 15 20 25 30
0.01
0.1
1
Tail state trap
1x1013
cm-2
1x1014
8x1014
8x1015
[Ref]
RTN trap @ filler/channel
1-C
um
ula
tiv
e P
rob
ab
ilit
y
DVT [mV]
0 5 10 15 20 25 30
0.01
0.1
1 RTN trap @ 5nm from filler
Tail state trap
1x1013
cm-2
1x1014
8x1014
8x1015
[Ref]
1-C
um
ula
tiv
e P
rob
ab
ilit
y
DVT [mV]
Fig. 4.5. 1-Cumulative distribution of the ΔVT by the RTN trap according to the
various tail state trap density. (a) When the RTN trap at the filler/channel interface, (b) the
RTN trap in the middle of the channel.
- 38 -
1013
1014
1015
1016
14
16
18
20
22
24
26
28
Open : P=0.01, Close : P=0.1
, RTN trap @ filler/channel
, RTN trap @ 5nm from filler
DV
T [
mV
]
Tail state trap density [cm-2]
(b)
(a)
1012
1013
1014
14
16
18
20
22
24
26
28
DV
T [
mV
]
Deep state trap density [cm-2]
, RTN trap @ filler/channel
, RTN trap @ 5nm from filler
Open : P=0.01, Close : P=0.1
Fig. 4.6. The ΔVT by the RTN trap with (a) the deep state trap density, (b) the tail state
trap density at P=0.01 and 0.1.
- 39 -
Fig. 6 shows the ΔVT values at p=0.01 and 0.1 extracted from 1-F of ΔVT in Fig. 4
and Fig. 5. Regardless of the P level and the location of the RTN trap, the ΔVT increases
with increase in the deep state trap density and is not affected by increase in the tail state
trap density. Because the Fermi energy level at VG=VT is located at 0.22 eV below from
the conduction band edge, the current density distribution at this voltage condition is
mostly affected by the deep state trap density, so the ΔVT distribution by the RTN trap is
more sensitive to changes in the deep state trap density than the tail state trap density.
Fig. 7 and Fig. 8 show the RTN effect with respect to the gate length and the spacer
length. As the device is scaled down, the effect of the single trap continues to increase.
Fig. 8 (b) shows the ΔVT value at P = 0.01. When the gate length and the spacer length
are separately scaled, the RTN effect increases almost similarly, but when the gate length
and the spacer length are simultaneously scaled, the RTN effect is greatly increased. Fig.
9 and Fig. 10 show the RTN effect with respect to the channel and the filler oxide
thickness. Since the influence of the single trap increases as the size of the device is
scaled, the RTN effect also increases as the Tch decreases with the fixed Tfiller. However, if
the total hole CD is fixed and the Tch decreases, the RTN effect decreases. This result is in
contrast to the device with the crystalline silicon channel [15]. In case of the fixed hole
CD, since the effective channel width is fixed even if the channel thickness decreases, the
area ratio of grain boundary to channel decreases and the percolation path due to the grain
boundary trap weakens resulting in decrease in the ΔVT variation due to the single trap.
- 40 -
For the same reason, when the Tfiller is increased while the Tch is fixed, the RTN effect
decreases as shown in Fig. 10 (a). This is important aspect that should be considered
when attempting to increase the memory density by reducing the WL thickness, spacer
thickness and hole CD in the future 3D NAND.
0 5 10 15 20 25 30
0.01
0.1
1
RTN trap @ filler/channelL
G=28 nm
Spacer Length 28 nm [Ref]24 nm 20 nm 16 nm
1-C
um
ula
tive P
rob
ab
ilit
y
DVT [mV]
0 5 10 15 20 25 30
0.01
0.1
1
RTN trap @ filler/channelL
S=28 nm
Gate Length 28 nm [Ref]24 nm 20 nm 16 nm
1-C
um
ula
tiv
e P
rob
ab
ilit
y
DVT [mV](b)
(a)
Fig. 4.7. 1-Cmulative distribution of the ΔVT by the RTN trap according to (a) the gate
length, (b) the spacer length.
- 41 -
16 20 24 2820
22
24
26
28
30
32
34
P=0.01RTN trap @ filler/channel
DV
T [
mV
]
Length [nm]
Gate Length
Spacer Length
Gate & Spacer Length
0 5 10 15 20 25 30
0.01
0.1
1
RTN trap @ filler/channel
Gate &Spacer Length 28 nm [Ref]24 nm 20 nm 16 nm
1-C
um
ula
tive P
rob
ab
ilit
y
DVT [mV](b)
(a)
Fig. 4.8. (a) 1-Cmulative distribution of the ΔVT by the RTN trap according to the gate
& spacer length. (b) The ΔVT by the RTN trap at P=0.01.
- 42 -
0 5 10 15 20 25 30
0.01
0.1
1
2Tch
+Tfiller
= 50 nm
RTN trap @ filler/channel
16 nm(step: 3nm)
1-C
um
ula
tiv
e P
rob
ab
ilit
y
DVT [mV]
Tch= 4 nm
0 5 10 15 20 25 30
0.01
0.1
1
(step : 3nm)16 nm
Tfiller
= 30 nm
RTN trap @ filler/channel
1-C
um
ula
tive
Pro
bab
ilit
y
DVT [mV]
Tch= 4 nm
(b)
(a)
Fig. 4.9. 1-Cmulative distribution of the ΔVT by the RTN trap according to (a) the
channel thickness at the fixed Tfiller, (b) the channel thickness at the fixed Tfiller+2Tch.
- 43 -
0 5 10 15 20 25 30
0.01
0.1
1
Tch
= 10 nm
RTN trap @ filler/channel
1-C
um
ula
tive
Pro
bab
ilit
y
DVT [mV]
(step : 4nm)
Tfiller
= 38 nm
22 nm
4 7 10 13 1612
14
16
18
20
22
24
26
, 2Tch
+Tfiller
= 50 nm
, Tfiller
= 30 nm
Open : P=0.01, Close : P=0.1
DV
T [
mV
]
Channel Thickness [nm]
(b)
(a)
Fig. 4.10. (a) 1-Cmulative distribution of the ΔVT by the RTN trap according to the
filler oxide thickness at the fixed Tch. (b) The ΔVT by the RTN trap with the channel
thickness at P=0.01 and 0.1.
- 44 -
0 2 4 6 8 10 12
0.01
0.1
1Trap position[from filler]
0 nm 2.5 nm 5.0 nm 7.5 nm 10 nm
1-C
um
ula
tive
Pro
ba
bilit
y
DVT [mV]
(a)
(b)
5 10
Filler interface
Single Trap
? =2.5nm
VG=VT
0
Filler Channel Gate Ox
w/o RTN Trap
Fig. 4.11 (a) 1-F of ΔVT for RTN trap locations. (b) Electron density at VG=VT
Fig. 11(a) shows the 1-cumulative distribution of ΔVT. Due to the differences in trap
position and dielectric constant between the silicon and the oxide, the graph waveform is
divided into two types. The worst case occurs when trapping occurs in the middle of the
channel because the area affected by the trap is large. Also, the RTN effect at the
- 45 -
filler/channel interface is greater than that at the channel/gate oxide interface because the
electron density at VG=VT has a higher value inside the channel (Fig. 11(b)). Fig. 12(a ~
c) show the VT distribution according to the temperature. The average and fluctuation of
VT increase as the temperature decreases. Fig. 12(d) shows the electron density for
different temperature. As the temperature is lower, the trap occupancy in grain boundary
increases, so the impact of the randomly formed grain boundary is larger and the VT
scatter becomes larger.
200 250 300 350 400
300
400
500
600
700
800 Macaroni, Trap Empty
@ LG=50 nm, GB=30 nm
Temperature [K]
0
20
40
60
80
100
m(V
T)
[mV]
s(V
T )[m
V]
0 200 400 600 800 10000.0
0.1
0.2
T=300Km(V
T)= 500 mV
s(VT)= 34.5 mV
T=400Km(V
T)= 259 mV
s(VT)= 23.7 mV
T=200Km(V
T)= 752 mV
s(VT)=59.2 mV
Macaroni, Trap Empty @ LG=50 nm, GB=30 nm
Pro
babilitie
s
VT (mV)
200 400 600 800
0.01
0.1
1
250350
Temp.
400 K 300
LG=50 nm
GS =30 nm
Macaroni
200
Cu
mu
lati
ve
Pro
ba
bil
ity
VT [mV]
(a) (b)
(c)
T=200 K T=300 K T=400 K
(d) Source
Drain
Fig. 4.12 (a) Cumulative distribution, (b) histogram, (c) μ(VT) and σ(VT) and (d)
electron density for various temperatures.
- 46 -
200 400 600 800 1000
0.01
0.1
1
400K 300K 200K
LG=50 nm, GS =30 nm
Trap position[from filler]
Empty Filled [0 nm]
Cu
mu
lati
ve P
rob
ab
ilit
y
VT [mV]0 2 4 6 8 10 12 14
0.01 Grain Size =30 nm
Trap position = 5 nm from filler1-C
um
lati
ve
Pro
bab
ilit
y
DVT [mV]
(a) (b)
(c) (d)
12 14
Temperature 200 K 250 K 300 K
Trap position = filler/channel interface
400
Fig. 4.13 (a) Cumulative distribution, and (b, c) its complementary of the ΔVT by RTN
trap, (d) μ(ΔVT) and σ(ΔVT) for various temperatures.
Fig. 13 shows the ΔVT distribution by the RTN trap with the temperature. As the
temperature decreases, the RTN effect increases because the percolation path becomes
stronger.
- 47 -
4.4 Summary
The effect of the RTN trap was analyzed based on the VT distribution considering the
grain boundary trap density and the device scaling in macaroni-type 3D NAND through
3D TCAD simulation. As the current percolation path becomes stronger and the device
size decreases, the device generates larger RTN tail. The RTN effect increases as the deep
state trap density increases, but the tail state trap density has no effect on the ΔVT. In
addition, it was confirmed that as the gate length, spacer length, channel thickness, and
temperature decrease, the effect of the single trap on the device and the VT fluctuation by
the RTN trap also increases. However, if the channel thickness decreases while the total
hole CD is fixed, the current percolation path becomes weaker and the RTN effect
decreases.
- 48 -
References
[1] A. Ghetti et al., “Comprehensive Analysis of Random Telegraph Noise Instability and
Its Scaling in Deca–Nanometer Flash Memories,” IEEE Trans. Electron Devices, vol. 56,
no. 8, pp. 1746-1752 Aug. 2009, doi: 10.1109/TED.2009.2024031
[2] D. Kang et al., “A new approach of NAND flash cell trap analysis using RTN
characteristics” VLSI tech, 206-207, June. 2011.
[3] A. Ghetti et al., “Physical modeling of single-trap RTS statistical distribution in Flash
memories,” in Proc. IRPS, 2008, pp. 610–615, doi: 10.1109/RELPHY.2008.4558954.
[4] E. Nowak et al., “Intrinsic fluctuations in vertical NAND Flash memories,” VLSI tech,
2012, pp. 21–22, doi: 10.1109/VLSIT.2012.6242441.
[5] K. Takeuchi, “Single-Charge-Based Modeling of Transistor Characteristics
Fluctuations Based on Statistical Measurement of RTN Amplitude” VLSI, June. 2009
[6] C.-W. Yang et al., “Simulation and investigation of random grainboundary-induced
variabilities for stackable NAND Flash using 3-D Voronoi grain patterns,” IEEE Trans.
Electron Devices, vol. 61, no. 4, pp. 1211–1214, Apr. 2014, doi:
10.1109/TED.2014.2308951.
[7] J. Franco et al., “Impact of single charged gate oxide defects on the performance and
scaling of nanoscaled FETs,” in Proc. IRPS, 2012, pp. 5A.4.1–5A.4.6, doi:
10.1109/IRPS.2012.6241841.
[8] D. Resnati et al., “Characterization and Modeling of Temperature Effects in 3-D
- 49 -
NAND Flash Arrays—Part I: Polysilicon-Induced Variability” IEEE Trans. Electron
Devices, vol. 65, no. 8, pp. 3199-3206 Aug. 2018, doi: 10.1109/TED.2018.2838524
[9] M. Toledano-Luque et al., “Quantitative and predictive model of reading current
variability in deeply scaled vertical poly-Si channel for 3D memories,” in IEDM Tech.
Dig., 2012, pp. 203–206, doi: 10.1109/IEDM. 2012.6479009.
[10] R. Degraeve et al., “Statistical characterization of current paths in narrow poly-Si
channels,” in IEDM Tech. Dig., 2011, pp. 287–290, doi: 10.1109/IEDM.2011.6131540.
[11] Y. W. John Seto et al., “The electrical properties of polycrystalline silicon films,” J.
Appl. Phys., vol. 46, no. 12, pp. 5247–5254, Dec. 1975, doi: 10.1063/1.321593.
[12] M. Valdinoci et al., “Analysis of electrical characteristics of polycrystalline silicon
thin-film transistors under static and dynamic conditions,” Solid-State Electron., vol. 41,
no. 9, pp. 1363–1369, 1997, doi: 10.1016/S0038-1101(97)00130-5.
[13] R. Degraeve et al., “Statistical poly-Si grain boundary model with discrete charging
defects and its 2D and 3D implementation for vertical 3D NAND channels,” in IEDM
Tech., 2015, pp. 121–124, doi: 10.1109/IEDM.201 5.7409636.
[14] G. Nicosia et al., “Characterization and Modeling of Temperature Effects in 3-D
NAND Flash Arrays— Part II: Random Telegraph Noise” IEEE Trans. Electron Devices,
vol. 65, no. 8, pp. 3207-3213 Aug. 2018, doi: 10.1109/TE D.2018.2839904
[15] M. Fan et al., “Analysis of Single-Trap-Induced Random Telegraph Noise on
FinFET Devices, 6T SRAM Cell, and Logic Circuits” IEEE Trans. Electron Devices, vol.
59, no. 8, pp. 2227-2234 Aug. 2012, doi: 10.1109/TED.2012.2200686
- 50 -
5. Conclusion
In this thesis, the characteristics of RTN effect on RSNM of SRAM, GIDL of DRAM
and VT fluctuation of 3D NAND were analyzed based on 3D TCAD simulation,
measurement data and the proposed equations.
In case of SRAM, we investigated the RTN effect on RSNM of 6T-SRAM composed
of 90Å Bulk-FinFET. Considering worst-case trapping combination and high temperature,
RSNM is reduced by 16.1 %. In addition, the RTN effect on RSNM of SRAM analyzed
regarding variability sources such as WFV, RDF, and LER.
The measured data and the analytical equations were used to obtain the oxide trap
parameter values in DRAM cell. These values were used to find the distance between the
two traps. For the first time, the high field enhancement factor Γ(F) was considered in
order to accurately calculate Ifilled/Iempty. When calculating the r distance, it is important to
use different field enhancement factors Γ(F) depending on the field at the Si/SiO2
interface because the value for r that is extracted is completely different depending on
which factor is used. This analysis provides more accurate extraction of the distance
between two traps. The amplitude of RTN which is one of the important phenomena in
DRAM retention time distribution can be predicted.
The effect of the RTN trap was analyzed based on the VT distribution considering the
grain boundary trap density and the device scaling in macaroni-type 3D NAND through
- 51 -
3D TCAD simulation. As the current percolation path becomes stronger and the device
size decreases, the device generates larger RTN tail. The RTN effect increases as the deep
state trap density increases, but the tail state trap density has no effect on the ΔVT. In
addition, it was confirmed that as the gate length, spacer length, channel thickness, and
temperature decrease, the effect of the single trap on the device and the VT fluctuation by
the RTN trap also increases. However, if the channel thickness decreases while the total
hole CD is fixed, the current percolation path becomes weaker and the RTN effect
decreases.
Future work
A new and exciting future work related to this thesis will include the following topics
- Analyzing the write static noise margin with RTN trap in SRAM.
- Studying the RTN characteristic for another DRAM device such as BCAT.
- Analyzing the memory characteristics (Retention, Endurance, Disturbance, etc.)
with RTN trap in 3D NAND Flash memory device.
- 52 -
Appendix A. Improving BSIM Flicker Noise Model
We modified BSIM flicker noise model and extracted the noise parameters as a
function of gate bias. In the proposed model, three noise parameters (NOIA, NOIB and
NOIC) were found to be proportional to the oxide trap density. The measured flicker
noise of the MOSFET is compared with the existing model and the proposed model, and
it is confirmed that the proposed model has higher accuracy.
A.1 Introduction
Flicker noise or 1/f noise is a major source of MOS drain current noise occurring at
low frequency. The unified flicker model has been used for a very long time [1]. However,
the noise parameters related to the oxide trap density are physically erroneous because
they are treated as fixed constants which are independent of the gate bias. We modified
the existing BSIM unified flicker noise model and developed a new model that expresses
the dependence of the noise parameters on the oxide trap density, which is gate bias
dependent. In the proposed model, these noise parameters are expressed as a function of
DC parameters and the oxide trap density. The extracted oxide trap density was modeled
as a function of gate voltage using two fitting parameters
- 53 -
A.2 Advanced Flicker Noise Model
BSIM flicker noise model is expressed as follows,
dVN
RNREN
fL
KTqI=fS
2Vd
0 efffnt2
effdId ò ± 21- ))(1()( am
g
m
(1)
*t NN
N
δΔN
δΔNR
+-==
(2)
CIT)(Cq
kTN ox2
* +=
(3)
where Sid is the drain noise spectral density, Id is the drain current, L is the channel
length, α is the scattering parameter for the influence of oxide traps charges on mobility,
Nt(Efn) is the oxide trap density, N is the channel carrier density, and 1010γ = is found
via experiments [1-5]. In the derivation process, the equation expressed as a function of
oxide trap density (Nt) and carrier density (N) is simplified to a parabolic function of N
with three parameters as shown in eq. (4).
2
2-1)1
NNOICNNOIBNOIA
NRENEN efffntfnt
´+´+=
±= am)(()(*
(4)
- 54 -
Using the eq. (4), the drain noise spectral density of the existing BSIM model can be
expressed as eq. (5).
úúúúúúú
û
ù
êêêêêêê
ë
é
-
+-
++
+
)NNOIC(N2
1
)NNOIB(N
*NN
*NNlnNOIA
CfLm
μIKTq=fS
2L
20
L0
L
0
ox2
effd2
Idg
)(
(5)
In BSIM, the three noise parameters of NOIA, NOIB, and NOIC are treated as
constants. However, we further derived the above equation to find the bias dependency of
the parameters as following. Eq. (6) is the expansion of Nt* using the eq. (2) without
approximating the oxide trap density like eq. (4). The first term of the eq. (6) corresponds
to NOIA, the coefficient of N in the second term is NOIB, and the coefficient of N2 in the
third term is NOIC.
- 55 -
22eff
2fnt
*2eff
2efffnt
*eff
2*2eff
2fnt
2efffnt
2efffntfn
*t
Nμ)α(EN
)NNμ2αμ)(2α(EN
)Nμ 2αNμα)(1(EN
N*)](Nαμ)[1(EN
)R
Nαμ)(1(EN)(EN
+
++
++=
++=
+=
(6)
úúúú
û
ù
êêêê
ë
é
-+-+
++
+++
´
)N(Nμα2
1)N)(NNμ2αμ(2α
*NN
*NNln)Nμ 2αNμα(1
)(ENCfLmγ
μIKTq=(f)S
2L
20
2eff
2L0
*2eff
2eff
L
0*eff
2*2eff
2
fnt
ox2
effd2
Id
(7)
Eq. (7) is our expression for the drain spectral noise density derived using the eq. (6),
which is proportional to the oxide trap density. The Nt can be extracted by fitting the
measured noise density and the equation [8].
- 56 -
A.3 Results and Discussion
100
101
102
103
104
105
10-21
10-20
10-19
10-18
10-17
10-16
10-15
VG = 0.965 V
VG = 1.165 V
VG = 1.65 V
VG = 3.3 V
Sid
[A2 /H
z]
f [Hz]
100
101
102
103
104
105
10-24
10-23
10-22
10-21
10-20
10-19
10-18
VG = 0.908 V
VG = 1.108 V
VG = 1.65 V
VG = 3.3 V
Sid
[A2/H
z]
f [Hz]
LG =10 μm, VD=3.3 V
LG =0.4 μm, VD=3.3 V
Scatter : MeasurementLine : BSIM4 Model
Scatter : MeasurementLine : BSIM4 Model
(a)
(b)
Fig. A.1. The drain noise spectral density. (a)L=10μm, (b)L=0.4μm
Fig. 1 shows the drain noise spectral density. The gate lengths are 10 m and 0.4 m,
- 57 -
and the drain voltage is 3.3V. At various gate bias conditions, the measured values and
the existing BSIM model are compared. As can be seen in the figure, the existing BSIM
model does not fit well with the measured values because the existing BSIM model
considers the oxide trap density as a constant value which is independent of the gate bias.
0.12 0.09 0.06 0.03 0.00 -0.03
1015
1016
1017
1018
EC
VD=3.3 V
L=0.4 mm L=1 mm L=10 mm
Nt
[cm
-3eV
-1]
EC-EF [eV]
0.5 1.0 1.5 2.0 2.5 3.0 3.5
1015
1016
1017
1018
VD=3.3 V
L=0.4 mm L=1 mm L=10 mm
Nt
[cm
-3eV
-1]
Gate Voltage [V]
(a)
(b)
Fig. A.2. The extracted trap density for (a) VG, (b) EC-EF.
- 58 -
Fig. 2 (a) shows the extracted oxide trap density as a function of the gate voltage and
gate length. We extracted the oxide trap density by fitting the measured drain noise
spectral density and the equation. There is almost no dependence on the gate length, and
it can be seen that the oxide trap density is changed with respect to the gate voltage unlike
the conventional model. Fig. 2 (b) shows the value of Nt according to the energy level.
Oxide ChannelGate MetalOxide ChannelGate Metal
High VGLow VG
EC-EF EC-EF
EF
EV
EC
EF
EV
EC
Fig. A.3. Energy band diagram of MOS structure at low voltage and high voltage.
Fig. 3 compares the energy band diagrams when the gate voltages are low and high. As
the gate voltage increases, the band bending becomes larger and the value of EC-EF
changes. Therefore, if the oxide trap density according to the energy level is not constant,
the effective oxide trap density that causes flicker noise changes according to the gate
bias.
- 59 -
-6 -4 -2 0 2 4 6
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
Source Drain
VG=0.958 V
VG=3.3 V
L=10mmVD=3.3 V
EC-E
F [
eV]
x-aixs [mm]
Source DrainMid
x
(a)
(b)
Fig. A.4. EC-EF value inside channel for gate voltage.
- 60 -
0.5 1.0 1.5 2.0 2.5 3.0 3.5-0.05
0.00
0.05
0.10
0.15
0.20
VD=3.3 V
Average L=0.4 mm L=1 mm L=10 mm
EC-E
F [
eV]
Gate Voltage [V]
Fig. A.5. Effective value of EC-EF for gate voltage and gate length.
Fig. 4 shows the TCAD results of EC-EF for each region according to the gate voltage.
Since the drain voltage of 3.3V is applied, the EC-EF becomes larger toward the drain
side, and it is slightly different depending on the gate length. Average value of EC-EF
was adopted as shown in Fig. 5.
- 61 -
100
101
102
103
104
105
10-23
10-22
10-21
10-20
10-19
10-18
10-17
10-16
10-15
VG = 0.958 V
VG = 1.158 V
VG = 1.65 V
VG = 3.3 V
Sid
[A2/H
z]
f [Hz]
100
101
102
103
104
105
10-21
10-20
10-19
10-18
10-17
10-16
10-15
VG = 0.965 V
VG = 1.165 V
VG = 1.65 V
VG = 3.3 V
Sid
[A2/H
z]
f [Hz]
L =0.4 μmVD=3.3 V
(a)
(b)
L =1 μmVD=3.3 V
100
101
102
103
104
105
10-25
10-24
10-23
10-22
10-21
10-20
10-19
10-18
VG = 0.908 V
VG = 1.108 V
VG = 1.65 V
VG = 3.3 V
Sid
[A2 /H
z]
f [Hz]
L =10 μmVD=3.3 V
(c)
Fig. A.6. The drain noise spectral density fitted with the proposed model using the extracted trap
density.
- 62 -
Fig. 6 shows the fitting of the proposed model and measurement data using the
extracted Nt. Unlike the conventional BSIM model, the measured values and the model
fit well for all gate biases and gate lengths.
0.12 0.09 0.06 0.03 0.00 -0.03
1015
1016
1017
1018
VD=3.3 V
Symbols = DataLine = Model
Nt[c
m-3
eV-1]
EC-E
F [eV]
26B
105A
)]Eexp[B(EA
16
FC
=
´=
-´
0.5 1.0 1.5 2.0 2.5 3.0 3.5
1015
1016
1017
1018
VD=3.3 V
Symbols = DataLine = Model
Nt[c
m-3
eV-1]
Gate Voltage [V]
4B
109A
]exp[B/VA
15
G
=
´=
´
(a)
(b)
Fig. A.7. The simplified model of extracted trap density for (a) VG, (b) EC-EF.
- 63 -
Fig. 7 shows a simplified expression of the extracted Nt from Fig. 2, and since the
extracted Nt has little dependence on the gate length, it is expressed as a function of gate
voltage only.
0.5 1.0 1.5 2.0 2.5 3.0 3.510
-25
10-24
10-23
10-22
10-21
10-20
10-19
10-18
10-17
10-16
10-15
Measurement New model BSIM model
Sid
[A2/H
z]
Gate Voltage [V]
nmosf=128Hz
L=10μm
L=0.4μm
Fig. A.8. Comparison of measure- ment data with the existing BSIM model and the proposed
model.
Fig. 8 compares the measured values with the existing BSIM model and the advanced
model at a fixed frequency of 128 Hz. Since the conventional BSIM model does not
consider the gate voltage dependency of the oxide trap density properly, it has a large
error with the measured data. However, since the proposed model extracts the Nt for each
gate bias, it is well fitted with the measured value.
- 64 -
A.4 Conclusion
We have improved the existing BSIM unified flicker noise model considering the
distribution of the oxide trap density as a function of energy level. The proposed flicker
noise model more accurately represents the drain noise spectral density. The model can
be used for device modeling and circuit design.
References
[1] K.K. Hung, P.K. Ko, and C. Hu, "A unified model for the flicker noise in metal-
oxide-semiconductor field-effect transistors." IEEE Transactions on Electron Devices
37.3 (1990): 654-665.
[2] Ewout P., and Lode K. J, "Critical Discussion on Unified 1=f Noise Models for
MOSFETs." Memory Workshop (IMW), IEEE Transactions on Electron Devices 47.11
(2000): 2146-2152.
[3] L.K.J. Vandamme, Xiaosong Li, and D. Rigaud, "1/f noise in MOS devices, mobility
or number fluctuations?" IEEE Transactions on Electron Devices 41.11 (1994): 1936-
1945.
[4] Thiago H. Both, Gilson I. Wirth, and Dragica Vasileska, “1/f noise simulation in
MOSFETs under cyclo-stationary conditions using SPICE simulator”, Journal of
Computational Electronics 14.1 (2015): 15-20
[5] K.K. Hung, P.K. Ko, C. Hu, and Y.C. Cheng, “A physics-based MOSFET noise
- 65 -
model for circuit simulators” IEEE Transactions on Electron Devices 37.5 (1990): 1323-
1333.
[6] Kimiyoshi Yamasaki, Minoru Yoshida and Takuo Sugano, “Deep Level Transient
Spectroscopy of Bulk Traps and Interface States in Si MOS Diodes”, Japanese Journal of
Applied Physics 18.1 (1979): 113-122
[7] D. A. Buchanan, D. J. DiMaria, “Interface and bulk trap generation in metal oxide
semiconductor capacitors” Journal of Applied Physics 67 (1998)
[8] R. Jayaraman, C.G. Sodini, “A 1/f noise technique to extract the oxide trap density
near the conduction band edge of silicon”, IEEE Transacti -ons on Electron Devices 36.9
(1989): 1773-1782.
- 66 -
초 록
본 논문에서는 소자 잡음의 종류 중 하나인 Random Telegraph Noise
(RTN) 효과를 여러가지 메모리 소자 (SRAM, DRAM, Flash)에서
분석하였다. 기본적으로, RTN은 소자의 트랩에 시간에 따른 전자의
포획/방출 현상에 의해서 나타나고, 소자의 전류 및 문턱 전압의 변화를
야기한다. 이러한 현상은 메모리 소자에서 여러가지 신뢰성 문제의 원인으로
작용하며 특히, SRAM에서의 노이즈 마진 감소, DRAM에서의 VRT 현상
그리고 Flash에서의 문턱 전압 변동의 요인으로 작용한다.
6개의 트랜지스터로 이루어진 SRAM은 Read 동작에서의 버터플라이
곡선에서 최대 정사각형의 크기로 노이즈 마진이 정의된다. 이러한 노이즈
마진은 Pull UP (PU)와 Pull Down (PD)의 Subthreshold Swing 및 VT
mismatch, 그리고 Pass Gate (PG)와 PD의 저항 차이에 의해서 결정된다.
SRAM 소자에 어떠한 조합으로 RTN Trap이 있을 때, VT mismatch 및 저항
차이가 제일 커져서 노이즈 마진이 최대로 감소하는지를 분석하였고
추가적으로, 여러가지 Variability source들과 함께 RTN 효과를 분석하였다.
DRAM cell의 retention time은 게이트와 드레인의 오버랩 영역에서
발생하는 Gate Induced Drain Leakage(GIDL) 전류에 영향을 받는다. 이
GIDL 전류는 RTN 현상에 의해서 시간에 따라 값이 바뀌며, DRAM cell의
- 67 -
variable retention time (VRT) 현상의 원인이 된다. VRT 현상을 정확히
이해하기 위해서 GIDL 전류 RTN의 원인이 되는 트랩에 대한 물리적 특성
이해가 반드시 이루어져야 하고, 현재까지 많은 그룹에서 연구를 진행하였다.
하지만, 여러가지 논문에서 전계의 크기를 고려하지 못하고 잘못된 수식을
사용하여 트랩 특성을 분석하였다. 본 논문에서는 전계의 크기를 고려하여 더
정확하게 트랩의 특성을 분석하는 연구를 진행하였고, 이러한 연구는
DRAM의 VRT현상을 이해하는데 큰 도움이 될 것이다.
3D NAND는 채널 물질이 폴리실리콘으로 형성되어 있어, 임의적으로
형성되는 Grain Boundary Trap (GBT)에 의한 소자의 신뢰성 문제가 큰
이슈이다. 특히 채널의 전류가 균일하게 흐르지 않고, 계속하여 증가하는 단
수 및 줄어드는 소자 구조에서 RTN 효과가 더욱 더 중요한 신뢰성 문제가
되고 있다. 본 논문에서는 여러가지 상황(RTN 트랩 위치, 온도, 소자 축소화,
GBT 밀도 등)에서의 RTN 효과를 분석함으로써 앞으로 3D NAND의 VT
변동에서의 RTN 영향력을 예측하는데 도움을 준다.
주요어 : RTN, Trap, FinFET, RSNM, SRAM, VRT, DRAM, 3D NAND.
학 번 : 2013-20799
- 68 -
List of Publications
Journal
[1] Youngsoo Seo, Sung-Won Yoo, Joonha Shin, Hyunsoo Kim, Hyunsuk Kim, Sangbin Jeon, and Hyungcheol Shin, “Extraction of Distance between Interface Trap and Oxide Trap from Random Telegraph Noise in Gate-Induced Drain Leakage Considering Suitable Field Enhancement Factor” journal of nanoscience and nanotechnology, 2015.
[2] Youngsoo Seo, Shinkeun Kim, Kyul Ko, Changbeom Woo, Minsoo Kim, Jangkyu Lee, Myounggon Kang, and Hyungcheol Shin, “Analysis of electrical characteristics and proposal of design guide for ultrascaled nanoplate vertical FET and 6T-SRAM” Solid State Electronics, 2018.
[3] Youngsoo Seo, Hyunsuk Kim, Myounggon Kang, and Hyungcheol Shin, “Analysis of Current-Boosting Using Trenched Source/Drain in Single and Stacked Nanowire FET”, journal of nanoscience and nanotechnology, 2017.
[4] Youngsoo Seo,Myounggon Kang,Jongwook Jeon,and Hyungcheol Shin, “Prediction of Alpha Particle Effect on 5nm Vertical Field-Effect Transistors”, IEEE TED, 2019.
[5] Sung-Won Yoo, Youngsoo Seo, Hyun Suk Kim, Sang bin Jeon, Joonha Shin, Hyun Soo Kim, and Hyungcheol Shin “Characterizing Traps Causing Random Telegraph Noise during Trap-Assisted Tunneling Gate-Induced Drain Leakage” Solid State Electronics, 2014.
[6] Hyunsuk Kim, Youngsoo Seo, Ilho Myoung, Minsoo Kim, Myounggon Kang, and Hyungcheol Shin, “Comparison for Performance and Reliability Between Nanowire FET and FinFET versus Technology Node”, journal of nanoscience and nanotechnology, 2017.
[7] Kyul Ko, Changbeom Woo, Minsoo Kim, Youngsoo Seo, Shinkeun Kim,Myounggon Kang, and Hyungcheol Shin, “Analysis and Comparison of Intrinsic Characteristics for Single and Multi-channel Nanoplate Vertical FET Devices”, JSTS, 2017.
[8] Hyunsuk Kim, Youngsoo Seo, Ilho Myoung, Myounggon Kang, and Hyungcheol Shin, “Analysis on DC and AC Characteristics of Self Heating Effect in Nanowire”, journal of nanoscience and nanotechnology, 2017.[9] Shinkeun Kim, Youngsoo Seo, Jangkyu Lee, Myounggon Kang, and
- 69 -
Hyungcheol Shin, “GIDL analysis of the process variation effect in gate-all-around nanowire FET”, Solid State Electronics, 2018.
Conference
[1] Youngsoo Seo, Duckseoung Kang, Sungwon Yoo, Dokyun Son, and Hyungcheol Shin, “Minimum Operation Voltage of 6T-SRAM Cell Composed of 90Å Bulk-FinFET Considering Oxide Traps, High Temperature, and Variability.” Silicon Nanoelectronics Workshop, 2014.
[2] Youngsoo Seo, Hyunsoo Kim, Jongsu Kim, and Hyungcheol Shin, “Analysis of hump of Capacitance-Voltage in low and high frequency on SiGe p-FinFET”, IEIE, 2014.
[3] Youngsoo Seo, Hyunsuk Kim, Myounggon Kang, and Hyungcheol Shin, “Analysis of On Current-boosting and Hot Carrier Degradation Considering Trenched Source/Drain in 5nm node Stacked Nanowire FET”, IVC-20, 2014.
[4] Youngsoo Seo, Sung-Won Yoo, Joonha Shin, Hyunsoo Kim, Hyunsuk Kim, Sangbin Jeon, and Hyungcheol Shin, “Extraction of Distance between Interface Trap and Oxide Trap from Random Telegraph Noise in Gate-Induced Drain Leakage” Korean Conference on Semiconductors, 2015.
[5] Youngsoo Seo, Sung-Won Yoo, Hyoungwoo Ko, Hyunok Jeon, Kyul Ko, and Hyungcheol Shin, “Trap Type Dependence of Modulation in TAT Gate-Induced Drain Leakage” ITC-CSCC, 2015.
[6] Youngsoo Seo, Hyunsoo Kim, Jongsu Kim and Hyungcheol Shin, “Analysis of local doping effect in hot carrier degradation on I/O FinFET”, IEIE, 2015.
[7] Youngsoo Seo, Hyunsuk Kim, Myounggon Kang, and Hyungcheol Shin, “Analysis of current-boosting using strain engineering and trenched source/drain in single & stacked nanowire FET”, Nanokorea, 2016.
[8] Youngsoo Seo, Hyunsoo Kim, and Hyungcheol Shin, “Analysis of Hot carrier Degradation according to Contact Resistance in 5nm node Stacked-Nanowire Field Effect Transistor”, SIM, 2016.
[9] Youngsoo Seo, Hyunsoo Kim, Jongsu Kim, and Hyungcheol Shin, “3차원
시뮬레이션을 이용한 FinFET과 Planar FET의 양전압 온도 불안정성
특성비교”, Korean Conference on Semiconductors, 2016.
[10] Youngsoo Seo, Kyul Ko, Changbeom Woo, Minsoo Kim, Shinkeun Kim, Myounggon Kang, and Hyungcheol Shin, “Optimal Integration and Electrical
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Characteristics for Ultra-Scaled Nanoplate Vertical FET, 6T-SRAM”, ICSPD, 2017.
[11] Youngsoo Seo, Shinkeun Kim, Myounggon Kang, and Hyungcheol Shin, “FinFET, Lateral and Vertical Nanowire FET를 이용한 6T-SRAM 특성 비교
분석 및 최적화”, Korean Conference on Semiconductors, 2017.
[12] Youngsoo Seo, Myounggon Kang, and Hyungcheol Shin, “Analysis of Parasitic Capacitance and Performance in Gate-All-Around and Tri-Gate Channel Vertical FET” SNW, 2017.
[13] Youngsoo Seo, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Analysis of Radiation Effect for Vertical Field Effect Transistor”, Korean Conference on Semiconductors, 2018.
[14] Youngsoo Seo, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Analysis of Radiation Effect for Nanoplate Field Effect Transistor”, SNW, 2018.
[15] Youngsoo Seo, Changbeom Woo, Myunghee Lee, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Improving BSIM Flicker Noise Model” EDTM, 2019.
[16] Dokyun Son, Duckseoung Kang, Sungwon Yoo, Youngsoo Seo, and Hyungcheol Shin, “Impact of Line Edge Roughness on RTN in SRAM Cells with 70 Å Nanowire FET” Silicon Nanoelectronics Workshop, 2014.
[17] Hyunsoo Kim, Youngsoo Seo, Jongsu Kim, Hyungcheol Shin, “Comparison of Capacitance-Voltage Characteristic of FinFET and Planar MOSFET”, IEIE, 2014.
[18] Hyunsuk Kim, Youngsoo Seo, Il ho Myoung, Myounggon Kang, and Hyungcheol Shin, “Analysis on Self Heating Effect on Trench Structure in 5 nm node 3D Stacked Nanowire FET”, IVC-20, 2014.
[19] Hyunsoo Kim, Youngsoo Seo, Jongsu Kim and Hyungcheol Shin, “Comparison of Impact Ionization Characteristics according to Spacer Length of n-FinFET and p-FinFET” IEIE, 2015.
[20] Hyunsoo Kim, Youngsoo Seo, Jongsu Kim, and Hyungcheol Shin, “Analysis of Hot Carrier Injection according to Doping Concentration in Channel/Substrate and Spacer Length in Bulk-FinFET”, ITC-CSCC, 2015
[21] Jongsu Kim, Youngsoo Seo, Hyunsoo Kim and Hyungcheol Shin, “Analysis of Capacitance-Voltage Characteristic according to Non-uniform Fixed Charge in SiGe p-FinFET”, AWAD, 2015.
[22] Jongsu Kim, Youngsoo Seo, Hyunsoo Kim, Hyungcheol Shin, “Analysis of Capacitance-Voltage Characteristic according to Variation of Ge portion in SiGe p-FinFET”, IEIE, 2015.
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[23] Jongsu Kim, Youngsoo Seo, Hyunsoo Kim and Hyungcheol Shin, “Comparison of Impact Ionization according to Fin Width between nFinFET and pFinFET”, IEIE, 2015.
[24] Hyunsoo Kim, Sung-Won Yoo, Youngsoo Seo, and Hyungcheol Shin, “Extraction of Location and Energy Level of Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage of p-MOSFET” Korean Conference on Semiconductors, 2015.
[25] Sung-Won Yoo, Youngsoo Seo, Do-Gyun Son, and Hyungcheol Shin, “The Influence of Variability Sources on SRAM Stability in 90A Non-rectangular Bulk FinFET SRAM cell” Korean Conference on Semiconductors, 2015.
[26] Sung-Won Yoo, Youngsoo Seo, and Hyungcheol Shin, “Analysis on Trapping Mechanism of Trap Causing Gate-Induced Drain Leakage Current Random Telegraph Noise” Semiconductor Interface Specialists Conference, 2015.
[27] Kyul Ko, Sung-Won Yoo, Hyunseul Lee, Youngsoo Seo, Sangbin Jeon, Hyungwoo Ko, Jeon-Hyun Ok,and Hyungcheol Shin, “Analysis of TAT Current Variation Induced by the Slow trap in Silicon”, IEIE, 2015.
[28] Hyunseul Lee, Sung-Won Yoo, Youngsoo Seo,, Changhwan Shin and Hyungcheol Shin, “Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor”, AWAD, 2015.
[29] Hyunseul Lee, Sung-Won Yoo, Youngsoo Seo, Sangbin Jeon, Hyungwoo Ko, Jeon-Hyun Ok, Kyul Ko and Hyungcheol Shin, “Analysis on the impact of the oxide trap in MOSFET using device simulation”, IEIE, 2015.
[30] Hyunok Jeon, Sung-Won Yoo, Hyunseul Lee, Youngsoo Seo, Sangbin Jeon, Hyungwoo Ko, Kyul Ko and Hyungcheol Shin, “Extraction of Distance between Interface Trap and Oxide Trap depending on trap type by considering accurate Field Enhancement Factor”, IEIE, 2015.
[31] Sung-Won Yoo, Youngsoo Seo, Hyunseul Lee, SangBin Jeon , Hyunok Jeon, Kyul Ko, Hyungwoo Ko, and Hyungcheol Shin, “Statistical analysis on trap characteristics causing gate-induced drain leakage current random telegraph noise”, IEIE, 2015.
[32] SangBin Jeon , Sung-Won Yoo, Hyunseul Lee, Youngsoo Seo, Hyungwoo Ko, Kyul Ko, Hyunok Jeon, and Hyungcheol Shin, “New method for extracting Gate Induced Drain Leakage (GIDL) at planar MOSFET using new method”, IEIE, 2015.
[33] Jongsu Kim, Youngsoo Seo, Hyunsoo Kim, and Hyungcheol Shin, “Analysis of Capacitance-Voltage Characteristics according to Strain Engineering and Interface State for nFinFET”, IEIE, 2015.
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[34] Sung-Won Yoo, Youngsoo Seo, SangBin Jeon , Hyungwoo Ko, Hyunok Jeon, Kyul Ko, and Hyungcheol Shin, “The Comparison of trap characteristics with trap type under TAT Gate-Induced Drain Leakage Random Telegraph Noise experiment”, AWAD, 2015.
[35] Hyunsoo Kim, Youngsoo Seo, Jongsu Kim, and Hyungcheol Shin, “Analysisof Non-ideal Capacitance-Voltage Characteristics according to Decrease in Gate Length of Si Bulk-FinFET”, IEIE, 2015.
[36] Hyungwoo Ko, Sung-Won Yoo, Youngsoo Seo, Hyunseul Lee, SangBin Jeon , Hyunok Jeon, Kyul Ko, and Hyungcheol Shin, “Electric field variation by single trap considering the relative permittivity variation due to doping concentration”, IEIE, 2015.
[37] Shinkeun, Kim, Youngsoo Seo, Myounggon Kang, and Hyungcheol Shin, “Nanowire FET에서 채널과 기판 사이 산화막두께와 도핑에 따른 GIDL
분석”, IEIE, 2016.
[38] Jongsu Kim, Youngsoo Seo, Hyunsoo Kim, and Hyungcheol Shin, “5 nm 세대 나노 와이어의 기생 커패시턴스 성분 분석 및 추출”, Korean Conference on Semiconductors, 2016.
[39] Hyungwoo Ko, Youngsoo Seo, Hyunsoo Kim, Jongsu Kim, and Hyungcheol Shin, “3D TCAD를 이용한 4층의 Nanowire-FET에서의 sheet 저항 추출
방법”, Korean Conference on Semiconductors, 2016.
[40] Kyul Ko, Changbeom Woo, Minsoo Kim, Youngsoo Seo, Shinkeun Kim, Myounggon Kang, and Hyungcheol Shin, “Analysis and Comparison of Intrinsic Characteristics for Single and Multi-channel Nanoplate Vertical FET Devices”, ICSPD, 2017.
[41] Shinkeun Kim, Youngsoo Seo, Dokyun Son, Myounggon Kang, and Hyungcheol Shin, “Analysis of Process Variation Effect on 6T-SRAM with Gate All Around Nanowire FET”, ICSPD, 2017.
[42] Shinkeun Kim, Youngsoo Seo, Myounggon Kang, and Hyungcheol Shin, “3차원 시뮬레이션을 이용한 Gate-All-Around Nanowire FET의 PVE(Process
Variation Effect)에 의한 GIDL분석”, Korean Conference on Semiconductors, 2017.
[43] Shinkeun Kim, Youngsoo Seo, Dokyun Son, Myounggon Kang, and Hyungcheol Shin, “Analysis of Two Divided Component of NBTI Framework using TCAD Simulation” SNW, 2017.