Dynamic offset compensated CMOS amplifiers

Dynamic Offset Compensated CMOS Amplifiers

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES

Consulting Editor: Mohammed Ismail. Ohio State University

For other titles published in this series, go to www.springer.com/series/7381

Dynamic Offset Compensated CMOS Amplifiers

Delft University of Technology, the Netherlands

SpringerBoston/Dordrecht/London

Johan F. Witte, Kofi A.A. Makinwa, Johan H. Huijsing

Dr. Johan F. Witte Prof. Kofi A.A. MakinwaDelft University of Technology Delft University of TechnologyDept. Electrical Engineering Dept. Electrical EngineeringMekelweg 4 Mekelweg 42628 CD Delft 2628 CD DelftNetherlands [email protected] [email protected]

Prof. Johan H. HuijsingDelft University of TechnologyDept. Electrical EngineeringMekelweg 42628 CD [email protected]

ISBN 978-90-481-2755-9 e-ISBN 978-90-481-2756-6DOI 10.1007/978-90-481-2756-6Springer Dordrecht Heidelberg London New York

Library of Congress Control Number: 2009926941

© Springer Science+Business Media B.V. 2009No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or byany means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without writtenpermission from the Publisher, with the exception of any material supplied specifically for the purpose ofbeing entered and executed on a computer system, for exclusive use by the purchaser of the work.

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Preface ...................................................................................................

Acknowledgements .......................................................................

1. Introduction ......................................................................................... 11.1 Motivation .............................................................................................. 11.2 Offset ...................................................................................................... 3

1.2.1 Drain current mismatch ................................................................. 41.2.2 Folded cascode amplifier offset ..................................................... 51.2.3 Minimizing offset .......................................................................... 6

1.3 Challenges .............................................................................................. 71.4 Organisation of the book ........................................................................ 81.5 References ............................................................................................ 10

2. Dynamic Offset Compensation Techniques ............... 13

2.1 Introduction .......................................................................................... 132.2 Auto-zero amplifiers ............................................................................. 14

2.2.1 Output offset storage ................................................................... 142.2.2 Input offset storage ...................................................................... 162.2.3 Auxiliary amplifier ...................................................................... 172.2.4 Noise in auto-zero amplifiers ...................................................... 19

2.3 Chopper amplifiers ............................................................................... 232.3.1 Noise in chopper amplifiers ......................................................... 252.3.2 Chopped operational amplifier in a feedback network ................ 262.3.3 Charge injection effects in chopper amplifiers ............................ 27

2.4 Chopped auto-zeroed amplifier ............................................................ 292.5 Switching non-idealities ....................................................................... 31

2.5.1 Charge injection reduction tactics ............................................... 332.5.2 Charge injection suppression circuits .......................................... 36

2.6 Conclusions .......................................................................................... 402.7 References ............................................................................................ 40

v

xi

ix

3. Dynamic Offset Compensated Operational Amplifiers .............................................................................................................. 43

3.1 Introduction .......................................................................................... 433.2 Ping-pong operational amplifier .......................................................... 443.3 Offset-stabilized amplifiers .................................................................. 45

3.3.1 Auto-zero offset-stabilized amplifiers ......................................... 473.3.2 Chopper offset-stabilized amplifiers ........................................... 483.3.3 Frequency compensation ............................................................. 503.3.4 Chopper stabilized amplifiers with ripple filters ......................... 553.3.5 Chopper and auto-zero stabilized amplifiers ............................... 58

3.4 Chopper offset-stabilized chopper amplifiers ...................................... 593.4.1 Iterative offset-stabilization ........................................................ 61


4. Dynamic Offset Compensated Instrumentation Amplifiers .............................................................................................................. 67

4.1 Introduction .......................................................................................... 674.1.1 Current-feedback instrumentation amplifiers ............................. 69

4.2 Dynamic offset compensated instrumentation amplifiers .................... 744.2.1 Chopper instrumentation amplifier ............................................. 754.2.2 Auto-zeroed instrumentation amplifier ....................................... 764.2.3 Ping-pong instrumentation amplifier .......................................... 784.2.4 Ping-pong-pang instrumentation amplifier ................................. 784.2.5 Offset-stabilized instrumentation amplifiers ............................... 794.2.6 Chopper offset-stabilized chopper instrumentation amplifier ..... 82


vi

5. Realizations of Operational Amplifiers ........................ 85

5.1 Introduction .......................................................................................... 855.2 Chopper offset-stabilized operational amplifier ................................... 86

5.2.1 Topology ...................................................................................... 865.2.2 Circuits ........................................................................................ 915.2.3 Measurement results .................................................................... 98

5.3 Chopper and auto-zero offset-stabilized operational amplifier .......... 1045.3.1 Topology .................................................................................... 1045.3.2 Circuits ...................................................................................... 1075.3.3 Measurement results .................................................................. 112

5.4 Conclusions ........................................................................................ 1155.5 References .......................................................................................... 116

6. Realizations of Instrumentation Amplifiers ............ 117

6.1 Introduction ........................................................................................ 1176.2 Low-offset indirect current-feedback instrumentation amplifier ....... 118

6.2.1 Introduction ............................................................................... 1186.2.2 Topology .................................................................................... 1186.2.3 Circuits ...................................................................................... 1226.2.4 Measurement results .................................................................. 124

6.3 High-side current-sense amplifier ...................................................... 1296.3.1 Current-sensing .......................................................................... 1296.3.2 Topology .................................................................................... 1336.3.3 Circuits ...................................................................................... 1386.3.4 Measurement results .................................................................. 143

6.4 Conclusions ........................................................................................ 1476.5 References .......................................................................................... 149

7. Conclusions and Future Directions ................................ 151

7.1 Conclusions ........................................................................................ 1517.2 Future directions ................................................................................. 1517.3 References .......................................................................................... 153

vii

viii

A. Layout Issues ................................................................................... 155

A.1 Introduction ......................................................................................... 155A.2 Chopper layout .................................................................................... 157A.3 Clock shielding .................................................................................... 160A.4 Conclusion ........................................................................................... 162A.5 References ........................................................................................... 162

About the Authors ....................................................................... 163

Index ...................................................................................................... 167

Preface

CMOS amplifiers suffer from relatively poor offset specifications. Since the1980s techniques have been explored to calibrate for this offset, or to let theamplifier itself compensate for its offset in some way or another. This latterapproach is often done dynamically during operation of the amplifier, hencethe name “dynamic offset compensation”. This thesis describes the theory,design and realization of dynamic offset compensated CMOS amplifiers.It focuses on the design of general-purpose broadband operational amplifiersand instrumentation amplifiers.

Two distinguishable offset compensation techniques are described inchapter 2: auto-zeroing and chopping. Several topologies are discussed, in chapter3 which can be used to design broadband dynamic offset-compensatedoperational amplifiers as well as instrumentation amplifiers, which are describedin chapter 4. Four implementations are discussed in this book: two low-offsetbroadband operational amplifiers in chapter 5, and chapter 6 discusses alow-offset instrumentation amplifier, and a low-offset current-sense amplifier,which can sense battery currents at a 28V rail.

J.F. WitteK.A.A. MakinwaJ.H. HuijsingDelft, December 2008

ix

Acknowledgements

This book started as a Ph.D. thesis written at the ElectronicInstrumentation Laboratory of Delft university of technology, where I spentan productive, learningfull period of more than 6 years obtaining both myM.Sc. and Ph.D. degrees. I would start by thanking a lot of people, to whom Iam indebted.

Firstly, I would like to thank my inspirators Han Huijsing and KofiMakinwa. I am grateful to Han for introducing me into the field of precisionamplifiers. I want to thank Kofi for giving me good advice and proofreadingmy publications.

Secondly, I would like to thank the people who in my opinion keep theuniversity’s wheels turning. Money makes the world go round and I wouldlike to thank Willem van der Sluys for guiding every person of the laboratorythrough the financial bureaucracy. He even does it with a smile on his face.Without tools an engineer would only be a philosopher, and, therefore, Ithank Antoon Frehe for keeping the computer servers in the air, despitefailing and leaking air conditioners. My thanks also go to Evelyn, Ingeborg,Inge, Trudie, Pia, Helly and Joyce whose administrative support kept thegroup running through the first years of my M.Sc. and Ph.D. projects, and mythanks go to Ilse and Joyce who continue to keep the group running thanks totheir ongoing administrative support.

Thirdly, I would really like to thank all the people who helped meduring the design and measurements of my amplifiers. I want to thank Ger deGraaf, who has also defeated me quite often in our regular tennis matches. Iwant to thank Maureen Meekel, who even saw me crying once. Special

xi

Acknowledgements

thanks go to Piet, Jeff, Jeroen and Zu-Yao for helping me with variousmeasurement problems. I also want to thank Harry Kerkvliet, who sadlyenough passed away during my project, but he used to be a great help when astudent needed equipment.

Special thanks also go to my former roommates Vladimir and Peter, andmy fellow roommates Davina, Gayathri and Eduardo. Thanks also go toMichiel, Martijn, and Paulo with whom I have also enjoyed some vacations aswell as tough technical discussions. I also have to thank the current groupmembers Mahdi Kashmiri, Caspar van Vroonhoven, Rong Wu, and AndreAita for many interesting discussions.

I would also like to thank all the people from Maxim semiconductor,who helped me with the implementation of the current-sense amplifier. Ithank Paul and Bill for getting the project started, Matt Kolluri for helping methrough my first real product design cycle, Jennifer for her layout efforts,Ray, Mike and Brian for their help in testing, and Rich for keeping the projectgoing.

I also thank my former house-mate, Rob. I really thank him formaintaining a social circle. He taught me to drink whisky. We have brewedsome mead and together with Martijn, Bas and Marc we slayed a dragon ortwo. Fun and friendship are necessary parts of life.

I also want to thank my family members. I especially want to thank myfather for supporting me in my education. My aunt Corry for giving meadvice over the years. I also would like to thank my mother. If you are able toraise a child to become an engineer, or even a doctor, then you really haven’tbeen a bad mother after all.

Finally I want to thank my girlfriend Sophie with whom I have struggledthrough the last parts of this long and hard quest. Doing a Ph.D. is also aburden on your most loved ones. She has carried that burden.

J.F. WitteDelft, December 2008

xii

1

1

Introduction 1

1.1 MotivationLow-offset amplifiers are needed in measurement systems. Typical applicationsinclude the read-out electronics of strain gauges, thermocouples, piezoelectricsensors, Hall sensors, or photo diodes. The signals generated by these devices aresmall, sometimes at the microvolt level. From an economical point of view,CMOS is the preferred technology for designing analog circuits, since it isrelatively low cost and it enables the integration of low-power digital signalprocessing. This, in turn, makes the realization of complex mixed-signal systemsfeasible.

However, the input offset of typical CMOS amplifiers is at the millivoltlevel, limiting their accuracy severely. This compromises their usefulness inmeasurement systems. Therefore, techniques have been developed to solvethis input offset problem. The need for precision electronics is the drivingforce behind a continuous effort to reduce the offset of CMOS amplifiers.

Calibration during production or trimming by the user would be theobvious solution to achieve a low offset, however, offset-trimmed CMOSamplifiers still suffer from offset drift over temperature and time. This offsetdrift will be an accuracy limit. Another method is to compensate for the offsetdynamically, by implementing extra on-chip dynamic offset compensation

Introduction

2

circuitry in amplifiers. Because these techniques continue to compensate forthe offset during the lifetime of the device, slow variations of the offset willalso be compensated. Thus, offset drift over time and temperature will bestrongly reduced.

Furthermore, considering the current trend towards lower supply voltages,offset in typical low-voltage CMOS amplifiers is becoming an increasinglymore important limit in accuracy and dynamic range. Moreover, it can bepredicted that knowledge about dynamic offset compensation techniques willbecome a necessity for future analog designers.

There are two different dynamic offset compensation techniques thatcan be distinguished, auto-zeroing and chopping [1.1]. Auto-zeroing is asampling technique in which the offset is measured during one samplingphase and subtracted during another sampling phase. During the measurementphase, the amplifier cannot be used to amplify the input signal, which makesauto-zeroing difficult to implement in a continuous-time amplifier. Chopping,on the other hand, is a frequency modulation technique in which the signaland offset are modulated to different frequencies. In this way the offset can bedistinguished from the signal, after which the offset is filtered out. This filterrequirement makes it difficult to design a broadband amplifier.

The chopping technique was already explored in the late 1940s [1.2],when the signal of an amplifier implemented with vacuum tubes wasmodulated using mechanical switches. The auto-zero technique is probablymuch older. However, it was implemented in a monolithic amplifier in theearly 1970s [1.3]. Both chopping and auto-zeroing techniques can beimplemented in integrated circuits because of the availability of very goodMOS switches. Dynamic offset compensated operational amplifiers becamecommercially available in the early 1980s [1.4] and implementations based onthose early topologies are still available [1.5].

In recent years, many new developments have been made. For instance,a chopper offset-stabilized operational amplifier with a very goodnoise-power ratio has been developed [1.6] and commercialized [1.7], and alow-offset high-voltage device has been commercialized [1.8]. A moredetailed overview of the many developments in this field will be presented inchapters 2, 3 and 4.

This book focuses on dynamic offset compensation techniques used inbroadband CMOS amplifiers. In chapter 3 topologies are shown whereauto-zero and chopping techniques are used in multi-path topologies [1.9].In these topologies a low-frequency path is used to obtain a low offset, while

3

Offset

a high-frequency path is used to obtain a high gain bandwidth product. Thistechnique is called offset-stabilization, because, the offset of the high-frequencypath is stabilized by the low-frequency path. The implementations described inchapters 5 and 6 focus on general-purpose feedback amplifiers with a gainbandwidth product of approximately 1 MHz and an offset in the µV range. Apartfrom operational amplifiers, indirect current-feedback instrumentation amplifiers[1.10] are also discussed. In contrast to traditional three-operational-amplifiersinstrumentation amplifiers, such amplifiers isolate common-mode input andoutput voltages.

1.2 OffsetBefore dynamic offset compensation techniques are discussed, it makes senseto discuss the nature and origins of offset in CMOS amplifiers. Input offset ina system is generally defined as the input level that forces the output level togo to zero. For an amplifier, as shown in figure 1-1, the input offset is thedifferential input voltage that forces the output voltage to go to zero.

Although offset is a DC parameter it can drift over time and temperature.This offset drift is usually specified in datasheets. The DC power supply rejectionratio (PSRR) and common-mode rejection ratio (CMRR) can be defined by:

and . (1-1)

A

Vos

Vin=Vos+

-

Vout=0+

-+ -

A

Vos

Vout=AVos

+

-+ -

(a) (b)

Fig. 1-1 Amplifiers with offset: (a) differential input voltage equal toinput offset voltage forces output to zero, (b) output offset of anamplifier with shorted inputs.

PSRR∆VDD

∆Vos-------------= CMRR

∆VCM

∆Vos--------------=

Introduction

4

Where , , and are the changes in power-supply voltage, inputoffset voltage, and input common-mode voltage, respectively. From theseequations it can be seen that the offset can also change due to changing inputcommon-mode and power supply voltages. A 100 dB CMRR means that theoffset will shift 10 µV when the input common-mode changes by 1V.

It can be assumed that variations in the parameters of MOS transistorscauses their drain current to vary, which ultimately causes input-referredoffset voltage. In the following section, the input offset voltage of thecommonly used folded-cascode operational amplifier is analysed. First, themismatch dependency of the drain current will be derived.

1.2.1 Drain current mismatch

When operating in the strong inversion region, the drain current of aMOSFET can be described by:

, (1-2)

in which µ is the charge carrier mobility, Cox is the normalized oxidecapacitance, W is the channel width and L is the channel length of the MOStransistor, VT is the threshold function, Vgs is the applied gate-source voltageand β is the transconductance factor. The variation in drain current caused bya threshold voltage mismatch will then be given by:

, (1-3)

in which gm is the transconductance of the transistor. The variation in draincurrent caused by a transconductance factor mismatch can be given by:

. (1-4)

∆VDD ∆Vos ∆VCM

ID12---µCox

WL----- Vgs VT–( )2≈ β Vgs VT–( )2=

δID

δVT----------

δID

δVgs---------- g– m=–= 2µCox

WL-----ID– 2– βID=

2ID

Vgs VT–-----------------≈ ≈

δID

δβ-------- Vgs VT–( )2 ID

β-----≈ ≈

5

Offset

When operating in the weak inversion region, the drain current of aMOSFET can be described by

, (1-5)

in which Is is the specific current, n is the weak inversion slope factor, and Vth isthe thermal voltage, which is approximately 25 mV at room temperature. Theimplementations presented in this book were designed with 0.7 and 0.8 µmMOS processes. For these processes, n has a value of approximately 2. Formore advanced submicron processes this value could approach 1.2. In the weakinversion region, the variation in drain current caused by a threshold voltagemismatch will then be given by:

. (1-6)

In weak inversion, the variation in drain current caused by a transconductancefactor mismatch will then be given by:

. (1-7)

From equations (1-4) and (1-7) it can be concluded that the effect of thetransconductance factor mismatch is proportional to the drain current in bothweak and strong inversion. Similarly, the effect of threshold voltage mismatchis proportional to the transconductance of the transistor in both weak and stronginversion.

1.2.2 Folded cascode amplifier offset

In figure 1-2, a folded cascode amplifier is shown. It can be assumed that thecascode transistors M7, M8, M9, and M10 do not contribute to the offset.

ID Ise

Vgs VT–

nVth------------------

≈ 2nµCoxWL-----Vth

2 e

Vgs VT–

nVth------------------

4nβVth2 e

Vgs VT–

nVth------------------

= =

δID

δVT----------

δID

δVgs---------- g– m

ID

nVth----------–≈=–=

δID

δβ-------- 4nVth

2 e

Vgs VT–

nVth------------------ ID

β-----≈ ≈

Introduction

6

When the effects of the transconductance factor mismatch and thresholdvoltage mismatch of the three transistor pairs M1–2, M3–4, and M5–6 aresuperposed, the offset can be expressed as:

, (1-8)

where ∆VT and ∆β are the differences in threshold voltages and transconductancefactors of the indicated transistors respectively. The offset can be minimizedby reducing the transconductance of the current sources M5 and M6 and ofcurrent mirror M3 and M4, meaning that they should work in strong inversion.To obtain an optimal offset the input stage transistors should be given a largetransconductance and their ratio should be as small as possible,meaning that the input transistors M1–2 should work in weak inversion, whichindicates that , which is typically 50 mV at room temperature.

1.2.3 Minimizing offset

Variations in threshold voltages and transconductance factors are caused bymismatch. This is defined as the process of time-independent randomvariations in physical quantities of identical designed devices [1.11].Moreover, it is assumed that the transconductance factors β and the threshold

M10

M1

VDD

VSS

M8M7

M9

Vin

+

-

M2

Vout

M5M6

2IM4M3

VB1

VB2

VB3

II

II

2I2I

Fig. 1-2 Folded cascode operational amplifier.

VOS ∆VT1 2,gm3 4,

gm1 2,-----------∆VT3 4,

gm5 6,

gm1 2,-----------∆VT5 6,

Igm1 2,----------- ∆β1 2,

β1 2,------------

∆β3 4,

β3 4,------------ 2

∆β5 6,

β5 6,------------+ +

+ + +=

ID gm⁄

ID gm⁄ Vthn=

7

Challenges

voltage VT have a stochastic variation due to mismatch. The standarddeviation of the threshold voltage may be approximated by:

, (1-9)

where and are process-related constants and D is the distancebetween two transistors [1.11]. Therefore, it can be seen that thresholdvariations are inversely proportional to the square root of the transistor areaand proportional to the distance between transistors. The relative standarddeviation of the transconductance factor can be written as

, (1-10)

where , , , and are process related constants and [1.11]. In many processes only is specified, but this is not

sufficient to estimate the mismatch of transistors with small W or L in which and are more dominant mismatch sources. The offset of a CMOS

folded cascode gain stage as shown in figure 1-2 is typically 5–10 mV. If, for all transistors in a folded cascode amplifier, ,

%, and , then the obtainedoffset would be . In order to obtain , which isneeded to reach a 4σ value smaller than 0.5 mV, in a 0.7 µm process where

, transistors with an effective area of 6400 µm2 are needed.These can be regarded as very large transistors.

Instead of increasing the transistor size to improve offset behaviour, itcan be considered to add extra circuitry for offset trimming or dynamic offsetcompensation.

1.3 ChallengesThe main topic of this book is to design dynamic offset compensated CMOSamplifiers, with an approximately 1 MHz gain bandwidth product and anoffset in the µV range. This was already done in [1.4], where an auto-zerotechnique was used in a low-frequency path to stabilize the offset of a

σ2 VT( )AVT

2

WL-------- SVT

2 D2+=

AVthSVth

σ2 β( )

β2-------------

AW2

W 2L-----------

AL2

WL2----------

ACox

2

WL---------

Aµ2

WL-------- Sβ

2D2+ + + +Aβ

2

WL--------≈ Sβ

2D2+=

AW AL ACoxAµ Sβ

Aβ2 ACox

2 Aµ2+= Aβ

AW AL

∆VT 0.5 mV<∆β β⁄ 0.15< gm1 2, I⁄ 20 V 1–= gm1 2, 5gm5 6, 10gm3 4,= =

VOS 0.95 mV< σ VT( ) 0.125 mV<

AVT10 mV µm⁄=

Introduction

8

high-frequency path. In this book this technique will be called auto-zerooffset stabilization. It is known that chopper amplifiers have a superior noiseperformance but a limited bandwidth because of the filter requirement [1.1][1.12]. The main scientific challenge, addressed in this book, is to use thechopper technique in a low-frequency path to stabilize the offset of ahigh-frequency path [1.6] [1.13] [1.14], leading to a superior noisespecification. This technique will be called chopper offset stabilization in thisbook.

There are several challenges associated with the design of dynamicoffset compensated amplifiers. The added offset compensation circuitryprobably increases the power consumption, which customers do not like.Secondly, extra circuitry means extra design time, which design managers donot like. Although analog designers are generally intelligent beings, theirintellectual flexibility is still limited, and will stay limited. Thus, the morecomplex the topology, the more mistakes a designer can make, and the longera design cycle takes, or the lower the yield. The die size is somewhat relatedto the complexity of a topology. However, in practice, capacitors and resistorsoccupy large chip areas. Therefore, the number of capacitors and resistorsused in a design should be limited. To keep power consumption within limits,a topology should not have too many current consuming blocks. Therefore, inthis work an attempt has been made to design amplifiers with a reasonable diesize, power consumption and complexity.

An additional challenge, addressed in section 6.3, is to obtain alow-offset voltage for a high-voltage device. In 2003, 5.5 V supply voltagelow-offset wide-bandwidth amplifiers were available [1.5][1.15][1.16].However, a high-voltage low-offset part was not. Although since 2007, alow-offset current-sense amplifier has been commercially available [1.8].

In conclusion, the design of a dynamic offset compensated amplifiershould be relatively simple, while the implementation should use a relativelysmall silicon area and requires low-power consumption.

1.4 Organisation of the bookThis work has been divided into seven chapters and one appendix. Followingthis introduction, chapter 2 describes the two dynamic offset compensationtechniques, auto-zeroing and chopping. These two techniques can be

9

Organisation of the book

considered as the only dynamic offset compensation techniques. However,they have a limited usability in broadband general-purpose amplifiers.Therefore, chapter 3 goes a step further and describes how these techniquescan be used in multi-path operational amplifiers [1.9] creating broadbanddynamic offset compensated operational amplifiers. This theory will beextended to current-feedback instrumentation amplifiers in chapter 4. Twochapters are devoted to the implementation of broadband dynamic offsetcompensated CMOS amplifiers. Chapter 5 describes two designs ofoperational amplifiers, and in chapter 6 two instrumentation amplifiertopologies are described. The book ends with conclusions and somerecommendation for future research.

The first implementation described in chapter 5 is an operationalamplifier designed as a feasibility study for the chopper offset-stabilizationtechnique. It operates with an external clock. This amplifier obtained asubmicrovolt offset with external clock frequencies of 4 kHz.

The second operational amplifier discussed in chapter 6 has an on-boardoscillator and draws 300 µA of current, while obtaining a 30 nV/√Hz noiseand a 1 MHz GBW with a 100 pF load capacitance. Both the auto-zero andchopper technique are used to obtain a low offset. The first instrumentationamplifier implementation in chapter 6 is actually the same operationalamplifier with an extra input stage to support an indirect current-feedbackinstrumentation amplifier topology. It draws 340 µA of current whileobtaining a 40 nV/√Hz noise and a 1 MHz GBW with a 100 pF loadcapacitance.

The last implementation discussed in this book is of a current-senseamplifier [1.17]. Both the auto-zero and chopper technique are used to obtainan offset of less than 5 µV. It has an input common-mode voltage range from1.9 to 30 V and a DC common-mode rejection ratio of 143 dB.

In the process of designing these types of amplifiers, the authorexperienced critical problems with the layout of the amplifiers. In appendix Asome practical layout issues are discussed, which could help future designs tobe more successful.

Introduction

10

1.5 References[1.1] C.C. Enz, G.C. Temes, “Circuit techniques for reducing the

effects of op-amp imperfections: autozeroing, correlateddouble sampling, and chopper stabilization”, Proceedings ofthe IEEE, pp. 1584–1614, Nov. 1996.

[1.2] A.J. Williams, R.E. Tarpley, W.R. Clarck, “D-C amplifierstabilized for zero and gain”, Trans. AIEE, Vol. 67, pp. 47–57, 1948.

[1.3] R. Poujois, B. Baylac, D. Barbier, J. Ittel, “Low-level MOStransistor amplifier using storage techniques”, IEEE ISSCC,pp. 152–153, Feb. 1973.

[1.4] M.C.W. Coln, “Chopper stabilization of MOS operationalamplifiers using feed-forward techniques”, IEEE JSSC, Vol.16, pp. 745–748, Dec. 1981.

[1.5] Intersil, “ICL7650, 2MHz, super chopper-stabilized operationalamplifier”, Datasheet, http://www.intersil.com Mar. 2008.

[1.6] R. Burt, J. Zhang, “A micropower chopper-stabilized operationalamplifier using a SC notch filter with synchronous integrationinside the continuous-time signal path”, IEEE JSSC, pp. 2729–2736,Dec. 2006.

[1.7] OPA333 “1.8V, micropower CMOS operational amplifierszero-drift series”, Datasheet, www.ti.com, May 2007.

[1.8] Linear Technology, “LTC6102”, Datasheet http://www.linear.com,July 2007.

[1.9] R.G.H. Eschauzier, L.P.T. Kerklaan, J.H. Huijsing, “A 100-MHz100-dB operational amplifier with multipath nested Millercompensation structure”, IEEE JSSC, pp. 1709–1717, Dec. 1992.

[1.10] B.J. van den Dool, J.H. Huijsing, “Indirect current feedbackinstrumentation amplifier with a common-mode input range thatincludes the negative roll”, IEEE JSSC, pp. 743–749, July 1993.

[1.11] M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, “Matchingproperties of MOS transistors”, IEEE JSSC, pp. 1433–1439,Oct. 1989.

[1.12] A. Bakker, J.H. Huijsing, “High-accuracy CMOS smarttemperature sensors”, Dordrecht: Kluwer, 2000.

[1.13] J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, “A CMOS chopperoffset-stabilized opamp”, ESSCIRC, pp. 360–363, Sep. 2006.

11

References

[1.14] J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, “A CMOS chopperoffset-stabilized opamp”, IEEE JSSC, pp. 1529–1535, July 2007.

[1.15] Analog Devices, “AD8628”, Datasheet, http://www.analog.com,Mar. 2008.

[1.16] Maxim, “MAX4238”, Datasheet http://www.maxim-ic.com,Mar. 2008.

[1.17] J.F. Witte, J.H. Huijsing, K.A.A. Makinwa, “A current-feedbackinstrumentation amplifier with 5µv offset for bidirectional high-sidecurrent-sensing”, IEEE ISSCC, pp. 74–75, Feb. 2008.

2

13

Dynamic Offset Compensation Techniques 2

2.1 IntroductionIn this chapter, the theory underlying two dynamic offset compensationtechniques, chopping and auto-zeroing [2.1] will be discussed. Thesetechniques can be used in the design of both general purpose amplifiers anddedicated read-out electronics for sensors. By using these techniques theoffset is compensated continuously. Therefore, these also help to reduce offsetdrift over temperature or time. Since low-frequency noise and DC offset cannot be distinguished from each other by the dynamic offset compensationtechniques, both techniques also have an effect on low-frequency noise.

A good rule of thumb is that a dynamic offset compensationtechnique can be expected to reduce the initial offset of an amplifier by afactor of 100 to 1000. When a circuit has a very strict offset specification, acombination of dynamic offset compensation techniques can be used.

Over the years, some confusion has arisen with regard to the namingof the different dynamic offset compensation techniques. In this book twotechniques are distinguished, namely: auto-zeroing and chopping. These twotechniques are described in this chapter. In chapter 3, offset stabilization willbe introduced. In this technique the offset of a main amplifier is measured

Dynamic Offset Compensation Techniques

14

with a low-offset stabilization amplifier, which generates a correction signalto compensate for the offset of the main amplifier.

In this chapter, auto-zeroing is discussed first. This technique can alsobe described as time-domain modulation of offset, since the offset is measuredat one moment in time, and at another moment the signal is measured, and theoffset is subtracted from the signal. Afterwards, chopping is discussed. Thistechnique can also be described as frequency-domain modulation of offset. Theinput offset and input signal are modulated to different frequencies after whichthe modulated offset can be filtered out.

2.2 Auto-zero amplifiersDuring auto-zeroing, two phases in time can be distinguished: one auto-zerophase in which the offset of a system is measured and stored, and one signalphase in which the signal is amplified and the offset is subtracted from thesignal.

2.2.1 Output offset storage

Probably the simplest way to implement dynamic offset compensation is toplace a capacitor at the output of an amplification stage, as shown infigure 2-1. The capacitor C1 is used to store the output referred offset andsubtract it from the signal. Therefore, this technique is called auto-zeroingwith output offset storage [2.2]. In the literature this technique is also knownas open-loop offset cancellation [2.1]. During the sampling phase F2, S1 andS4 are open and S2 and S3 are closed. During the signal phase F1, S1 and S4are closed and S2 and S3 are open.

During the sampling phase F2 the voltage over the auto-zero capacitorC1 can be expressed as:

, (2-1)

where A is the voltage gain of the amplifier, while during the signal phase F1the output voltage can be expressed as:

and . (2-2)

Vout1 Vc AVos= =

Vout1 Vin Vos+( )A= Vout2 Vout1 Vc– AVin= =

15

Auto-zero amplifiers

This means that theoretically all offset is cancelled using this method.However, when the switches are implemented with MOS transistors they willinject charge into the auto-zero capacitance C1. This charge injection will bedescribed in more detail in section 2.5. However, it can be assumed that acharge qinj is produced by the switch each time it closes, and an equalnegative charge –qinj each time it opens.

At the end of the auto-zero phase, switch S3 opens and switch S4closes. Therefore, a charge injection mismatch qinj3–qinj4 is fed into thestorage capacitor. Thus:

. (2-3)

This results in a residual offset of:

. (2-4)

The influence of this mismatch on the residual offset can be reducedby increasing the size of the capacitor. Since the auto-zero capacitor is at theoutput of the amplifier, these effects can be divided by the voltage gain whenreferred to the input. Leakage from capacitor C1 during the amplificationphase also causes residual offset. This effect can also be divided by thevoltage gain.

A disadvantage of auto-zeroing with output offset storage is that theoutput range is reduced by , where is the maximal input

A

Vos

VinVout2

VcS1

S2S3

+

-+

-Vout1

+

-

+ -

+ - C1

F1

F2S4

F1

F2

Fig. 2-1 Auto-zeroed amplifier with output offset storage.

Vout1 Vc AVosqinj3 qinj4–( )

C1----------------------------+= =

Vos res,qinj3 qinj4–( )

AC1----------------------------=

2AVos max, Vos max,


16

offset that can be expected of an uncompensated amplifier. When the voltagegain is 40 dB and , then the output range is reduced by 2 V.Therefore, this technique can only be used in low-gain amplifiers, and not inhigh-gain general purpose amplifiers, but it can be useful in custom read-outelectronics. However, a fully integrated amplifier with three cascadedauto-zeroed amplifiers with output offset storage has been reported in [2.1],these stages were later chopped as well [2.3].

2.2.2 Input offset storage

There is another auto-zeroing technique that is implemented with input offsetstorage [2.2]. This technique is also known as closed loop offset cancellationin the literature [2.1]. An implementation is shown in figure 2-2. During thesampling phase F2, S1 and S4 are open while S2 and S3 are closed. During thesignal phase F1, S1 and S4 are closed while S2 and S3 are open.

During the sampling phase F2, the voltage over the auto-zerocapacitor C1 can be expressed as:

, (2-5)

while during the signal phase F1 the output voltage can be expressed as:

. (2-6)

Vos max, 10 mV=

A

Vos

VinVout

Vc

S1

S2

S3

+

-+

-+

-

+

-

+-

C1

F1

F2

S4

F1

F2

Fig. 2-2 Auto-zeroed amplifier with input offset storage.

VcA

A 1+-----------Vos=

Vout Vin Vos Vc–+( )A Vin1

A 1+-----------Vos+

A= =

17


Apart from the finite gain, charge injection is a source of residual offset. Thechannel charge of switch S3 will again cause a voltage step across the auto-zerocapacitor C1. Considering the same analysis provided in the previous section,this results in a residual offset which can be expressed as:

. (2-7)

The influence of S3 on the residual offset can be reduced by increasing thesize of the capacitor. In addition, the leakage of the capacitor C1 during theamplification phase can cause residual offset. These two effects cannot bedivided by the voltage gain because the auto-zero capacitor is already at theinput. In differential circuits, the residual offset due to charge injection willalso be reduced as will be explained in section 2.5.1.

This technique can be used to auto-zero a high gain operationalamplifier. The residual offset is then dominated by the charge injection.

2.2.3 Auxiliary amplifier

Another technique for auto-zeroing which is less sensitive to charge injectionis depicted in figure 2-3 [2.4]. In many cases, an amplifier will consist of atransconductance G1 with an output impedance Rout. This transconductanceG1 has an offset voltage V1. Phase F1 is the signal phase in which the inputsignal is applied to the amplifier and the output signal is useful. Phase F2shorts the inputs of G1 and its offset Vos causes an output current I1 to flow.This output current is integrated on capacitor C1. This capacitor drives anauxiliary input transconductance G2, which causes an offset compensating

Vos res,Vos

A 1+-----------

qinj3

C1----------+=

G1

V1

VinVout

Vc

F1

F2

+

-+

-

+

-

+

-

+-

C1

F1

G2+

-

F2Rout

I1

I2

V2+ -

S1

S2S3

S4

V1

VinVout

Vc

F1

F2

+

-+

-

+

-

+-

C1

F1

F2

I1S1

S2S3

S4

=G1

+

--

Fig. 2-3 Auto-zeroing with an auxiliary input stage and anintegrator. The right-hand schematic is commonly used.


18

current I2 to flow. The loop gain limits the offset reduction. In steady stateduring auto-zero phase F2 the following equation applies:

thus , (2-8)

while during the signal phase F1 the following equation applies:

. (2-9)

The residual offset due to finite gain can be expressed by:

, (2-10)

where A2 and V2 are the DC voltage gain and offset of G2, which acts as anauxiliary input of G1. Except for the limited voltage gain, additional residualoffset is also caused by the charge injection of switch S3 and the leakage ofthe capacitor C1 during the signal phase. The charge injection causes theresidual offset to become:

. (2-11)

The output of G1 has to switch between the output voltage and the voltage VCover the compensation capacitor C1. This voltage step itself can cause settlingproblems, which cause voltage spikes. To circumvent these problems anothertopology can be used in which C1 can be replaced with an active integrator.This concept is shown in figure 2-4. The amplifier stage G4 used toimplement the active integrator has the same input common-mode voltage asthe output stage G3. The output voltage of G1 is bounded at thiscommon-mode voltage. Capacitor C2b acts as a track-and-hold.

VC V1G1Rout V2 VC–( )G2Rout+= VCV1G1Rout V2G2Rout+

1 G2Rout+------------------------------------------------=

Vout V1 Vin+( )G1Rout VCG2Rout– G1RoutVinV1G1Rout

1 G2Rout+-----------------------+

V2G2Rout

1 G2Rout+-----------------------+= =

Vos res gain, ,V1

1 G2Rout+----------------------- 1

G1Rout----------------

V2G2Rout

1 G2Rout+-----------------------+

V1

A2------

V2

A1------+≈=

Vos res inj, ,G2qinj3

G1C1----------------=

19


Because of the sampling action, auto-zeroing is a technique which isnot suited for continuous time applications. Auto-zeroing itself is mainly usedin switched capacitor circuits, which are already sampled systems [2.1]. Alsowhen continuous-time operation is required, a ping-pong architecture can beused, in which two auto-zeroed amplifiers run parallel to each other, onebeing auto-zeroed and one being used to amplify the signal. This architecturewill be discussed in section 3.2.

2.2.4 Noise in auto-zero amplifiers

The auto-zero technique cannot distinguish low-frequency noise from offset.Therefore, the noise behaviour over frequency of an auto-zeroed amplifier isalso affected. A quantitative calculation of this effect has been provided byEnz [2.1] [2.5].

Intuitively, it can be assumed that when the amplifier depicted infigure 2-2 is auto-zeroed, the broadband noise of the amplifier is projectedonto the capacitor C1. At the end of the sampling phase the input offset andnoise voltage are held on the capacitor, which means that all components ofnoise above the auto-zeroing frequency will fold back due to aliasing. As aresult, the white noise in this band folds back to below the auto-zerofrequency.

G1

V1

Vin

Vout

F1

F2

+

-+

-

+

-

+-

G2+

-

I1

I2

V2+ -

S1

S2

G4+

-

G3

+

-C1

F1

F2 S3

S4

C2a

C2b

Fig. 2-4 Auto-zeroing with an auxiliary input stage and anactive integrator to circumvent voltage steps at theoutput of G1.


20

According to [2.1] an auto-zero amplifier, as depicted in figure 2-2,can be seen as the circuit, shown in figure 2-5. In this circuit, VN representsthe noise at the output of the amplifier in the auto-zero phase. It has beenshown in [2.1] and [2.5] that the noise power spectral density (PSD) for theauto-zero voltage across the switch can expressed as:

, (2-12)

where are transfer functions which model the folding effect of eachband n, is the noise PSD of VN, and Ts is the sampling period. In otherwords infinite noise bands are folded on top of each other to form a new noisecharacteristic. Luckily the bandwidth is limited, otherwise the PSD would beunlimited. The transfer functions can be expressed by [2.1]:

, (2-13)

where d is the duty cycle of hold time in the auto-zero action and for non-zero n

, (2-14)

where Th is the hold time during which there is no sampling action. Withthese equations it has been proven [2.1] [2.5] that auto-zeroing cancels the

R

Vc+ -

C1VN

+

-F1 VAZ

+

-

F1

tTh

Ts

ON

OFF

Fig. 2-5 Equivalent auto-zero circuit.

SAZ f( ) Hn f( ) 2SN f nTs-----–

n ∞–=

∞

∑=

Hn f( ) 2

SN f( )

H0 f( ) 2 d2 12πf Th( )sin

2πf Th---------------------------–

2 1 2πf Th( )cos–

2πf Th-----------------------------------

2+

=Th

Ts----- d=

Hn f( )2 d2 2πdn( )sin

2πdn------------------------

2πf Th( )sin2πf Th

---------------------------–2 1 2πdn( )cos–

2πdn--------------------------------

1 2πf Th( )cos–

2πf Th-----------------------------------–

2+

=

21


offset, or the DC component in the noise, and that the low-frequency noise ofthe resulting auto-zero amplifier is caused by the noise folding. It has alsobeen shown that 1/f noise is effectively compensated for when the 1/f cornerfrequency is lower than the auto-zero frequency.

Since this looks rather complicated, however, it is advisable to spenda day or two working with a mathematical program like Maple, Matlab orExcel, to get a feeling for noise folding before starting a design for anauto-zero amplifier. Consider, for instance, an amplifier with an equivalentnoise bandwidth equal to five times the auto-zero frequency. This has beensketched in figure 2-6, where d =1, i.e. for a sampling time of zero seconds.The side-bands fold back to the DC frequency. In this diagram it can be seenthat the noise is folded nine times, one time for the baseband and four timesfor each side-band.

In figure 2-7a the transfer functions are sketched for d =1. Infigure 2-7b the are sketched for d =0.5. It can be seen that the energyis more spread out over frequency. In figure 2-8 the noise folding has beensketched for d =0.5. The PSD amplitude around DC has been reduced byapproximately d2, and it can be seen that the PSD hits half the white noiselevel at 2fTs. The noise reduction can be explained by the noise powerspreading out over a wider bandwidth. It is essential to note that this is thesimulated noise PSD over the capacitor C1 in figure 2-2, and that the input

012345678901

65432101-2-3-4-5-6-fTs

SAZ

Noi

se p

ower

norm

aliz

ed to

inpu

t noi

se

Fig. 2-6 Sketched noise folding in auto-zeroing d=1.

Hn f( )2

Hn f( )2


22

signal power seen by the amplifier is also multiplied by the duty cycle d.Therefore, the equivalent PSD seen by the input signal at low frequencies canbe expressed as:

. (2-15)

This does not mean that the input noise power is reduced by increasing d.It only means that the noise PSD should be reduced for low frequencies. Fromfigure 2-8, it can be concluded, that around two times the auto-zero frequencythe input referred PSD of auto-zero amplifiers with a 50% duty cycle is equalto the white noise level of the amplifier.

During the auto-zero phase, when the amplifier is in a unity-gainsetting, the equivalent white noise bandwidth is 0.5πgm/C1, where gm is thetransconductance of the amplifier and C1 is the auto-zero capacitor. When allequivalent white noise is folded back to the base-band, then it can be assumedfrom the analysis above that the auto-zero amplifier for low frequencies, i.e.f<0.5/Ts, has a folded white noise floor of:

, (2-16)

Seq AZ, f 1Ts-----<

SAZ f( )d

---------------=

n=0

n=0

n=0 n=1

n=2,4 n=3

(a) d = 1 (b) d = 0.5

0

4 . 0

8 . 0

2 . 1

6 . 1

2 1 0 1 - 2 - 0

4 . 0

8 . 0

2 . 1

6 . 1

2 1 0 1 - 2 -

Fig. 2-7 sketched for n=0,1,2,3,4 with (a) d=1 and (b) d=0.5.H0 f( ) 2

Veqn LF,2 dπ

2---

gm

π2C1------------TsVn th,

2≈dTsgm

4C1--------------Vn th,

2=

23

Chopper amplifiers

This means that the white noise folding can severely harm the low-frequencycharacteristics. For instance, if a transconductance of 200 µA/V is auto-zeroedon a 10 pF capacitor with a duty-cycle of 50%, then the –3dB bandwidth is3.18 MHz, and the equivalent white noise bandwidth is 5 MHz. If theauto-zero frequency is 10 kHz, the noise at low frequencies would be a factor250 larger than the white noise power, and for the noise signal voltage thiswould be a factor . In the next section it will be shown that choppedamplifiers do not have this drawback.

2.3 Chopper amplifiersWhile in auto-zero amplifiers the offset and input signal are time-modulated,in chopper amplifiers they are frequency-modulated. In chopper amplifiersthe signal of interest and the offset signal are shifted to different frequencies.

250 16≈

0

5.0

1

5.1

2

5.2

3

65432101-2-3-4-5-6-fTs

SAZ

Noi

se p

ower

norm

aliz

ed to

inpu

t noi

se

Fig. 2-8 Sketched noise folding in auto-zeroing d=0.5.


24

In figure 2-9 a chopper amplifier is shown [2.1] [2.6]. This amplifierconsists of a frequency modulator, or chopper CH1, a voltage amplifier A1,another chopper CH2, and a low-pass filter (LPF). The chopper symbol is alsodepicted, which is a polarity switch driven by a square wave with a chopperfrequency FC.

The idealised waveforms are depicted in the time domain infigure 2-10. The first chopper is used to modulate the input signal to a higherfrequency. Then the amplifier amplifies the modulated signal superposed onits own input noise sources. Lastly, the second chopper demodulates theamplified input signal, and also modulates the output noise and offset of theamplifier A1.

The limited bandwidth of the amplifier A1 is a fundamental cause ofswitching glitches, because the input signal is modulated almost ideally,while the amplified signal Vb is slightly delayed when it is demodulated,causing high frequency glitches. The combination of non-zero offset and thechopper action also give rise to a chopper ripple, which has the samefrequency as the chopper clock and is proportional to the offset of the

Vout

CH2CH1

+-

Vin+

-A1Va

+-

Vb+-

LPF Vlfp+-

=Fc FcVos+-

Fig. 2-9 Chopper amplifier.

Va VbVin Vout Vlpf

VosA1Vos

Fig. 2-10 Idealised waveforms of a chopper amplifier in the timedomain (gain=A1=3).

25

Chopper amplifiers

amplifier and the –3dB frequency of the LPF. The LPF can also beimplemented with a sample-and-hold [2.7].

2.3.1 Noise in chopper amplifiers

When a low-pass filter is used after the chopper amplifier, the chopper rippleand low-frequency noise can be filtered. CMOS amplifiers usually have ahigh DC input offset voltage and 1/f noise. To reduce the 1/f noise, themodulation or chopper frequency chosen should be higher than the 1/f cornerfrequency [2.1]. This is illustrated in figure 2-11. In this figure it is shown thatthe signal is modulated, and that noise and offset is superposed on thismodulated signal. Afterwards the signal, noise and offset are modulated. Thismeans that the signal is demodulated, after which the signal can be filteredout.

From this analysis it can be concluded that the chopper techniquecompletely reduces the 1/f noise when the chopper frequency is higher thanthe corner frequency of the 1/f noise. In practice the noise level of a chopperamplifier is slightly higher than the thermal noise level. However, the need tosuppress the chopper ripple means that only a low bandwidth is obtainablewith a chopper amplifier.

VaVin

Vout Vlpf

signal

modulatedsignaloffset &

noise

demodulatedsignal

modulatedoffset &noise

white noise

demodulationartifactsnon linearities

Fig. 2-11 Idealised waveforms in the frequencydomain of a chopper amplifier.


26

2.3.2 Chopped operational amplifier in a feedback network

It is helpful in the understanding of chopper amplifiers to examine a choppedoperational amplifier in a feedback network more closely. In figure 2-12, achopped operational amplifier A1 is depicted [2.8]. Resistors R1 and R2 areused as feedback resistors, CH1 and CH2 are the modulators and LPF thelow-pass filter, as discussed in the previous section. The idealised waveformsare depicted in figure 2-13.

In this analysis it is assumed that the gain and bandwidth of theoperational amplifier are infinite. The input of A1 is at virtual ground becauseof the infinite open loop gain. Thus, the offset voltage V1 is visible at theoutput Vd of the input chopper CH1. This offset is modulated towards theinput Vc of chopper CH1, therefore it is actually visible as a square wavewhere, in the case of a normal operational amplifier, a virtual ground would

+-

+- +

-

A1

+

-

V1+ -

VoutVin

R1

R2

FCFC

LPF Vlfp+-

+-Vd

+-Vc

CH2CH1

Fig. 2-12 Chopped operational amplifier in a feedback network.

Vc VdVin Vout Vlpf

signal choppedoffset

offset

Fig. 2-13 Idealised waveforms in the time domain of a choppedoperational amplifier in a feedback network for (gain=3).

27

Chopper amplifiers

be expected. The output Vout of the chopper amplifier can now be expressedby:

. (2-17)

This means that the operational amplifier ripple at the output has an effectiveamplitude of offset V1 times the feedback gain factor.

The conclusion which can be drawn from this analysis is that thechopper ripple of a chopped operational amplifier in a feedback network isvisible at the input of the first chopper. This insight will be used in theexplanation of chopper offset-stabilized chopper amplifiers discussed insection 3.4.

2.3.3 Charge injection effects in chopper amplifiers

The charge injection of chopper amplifiers on a differential chopper amplifierwill be discussed. In these amplifiers the residual offset is mainly caused bythe charge injection mismatch from the clock lines to the input and output ofthe amplifier that is chopped. In figure 2-14 this is modelled with cross talkcapacitors C1 to C4. The resistors R1 and R2 model the on-resistance of theswitches used in the chopper and the source resistance.

First the effect of the mismatch between C1 and C2 will be analysed.When both lines are loaded with identical cross talk capacitors, no residualoffset will occur since it will be a common-mode spike. However, if there is aslight mismatch between the two capacitors, a differential component willalso appear at Va, which will translate into a residual offset, because thesespikes are actually demodulated by the input chopper towards the input [2.6].

Vout VcVin Vc–

R2----------------R1– V– in

R1

R2----- Vc 1

R1

R2-----+

+= =

Vout

CH2CH1

+-

Vin+

-G1Va

+-

Vb+-

LPF Vlfp+-

C1C2

VFC

R1

R2 C4

C3

Fig. 2-14 Charge injection model in a chopper amplifier.


28

This effect is illustrated in figure 2-15.Therefore, each time the chopper clockswitches charge is being injected into the input, this differential charge can beexpressed by:

, (2-18)

where VF is the driving voltage of clock VFC. This charge is applied twotimes the per clock period. This means that a current will run through theresistors R1 and R2. So the residual offset can be expressed by:

, (2-19)

where FC is the chopper frequency. This means that the residual offsetincreases with increasing chopper frequency. However, the chopperfrequency needs to be higher than the 1/f corner frequency to obtain optimalnoise performance.

For example the residual offset per unit of capacitance for a 20 kHzchopper frequency, an on-resistance of 5 kΩ with no source impedance and a5 V driving voltage, would be 2 µV/fF.

Secondly the effect of the mismatch between C3 and C4 will beanalysed. Also the capacitors C3 and C4 depicted in figure 2-14 can causeresidual offset. When C3=C4 no residual offset will occur, since it will be acommon-mode spike. However, if there is a slight mismatch between the twocapacitors, a differential current spike will appear at Vb, and thus a differentialvoltage spike will appear at Va, which will translate into a residual offset,because these spikes are actually demodulated by the input chopper towardsthe input [2.6]. This effect is illustrated in figure 2-16.

VFc VinVa

offset

Fig. 2-15 Illustration of residual offset caused by demodulatedspikes caused by a mismatch between C1 and C2.

qinj C1 C2–( )VF=

Vos res1, 2 R1 R2+( ) C1 C2–( )VFFC=

29

Chopped auto-zeroed amplifier

This leads to an extra residual offset which can be expressed by:

, (2-20)

where G1 is the transconductance of the chopped amplifier. It can be seen thathigher transconductance amplifiers will be less vulnerable to the mismatch ofC3 and C4. For example for a 20 kHz chopper frequency, a 100 µA/Vtransconductance, and a 5 V driving voltage the residual offset per unit ofcapacitance would be 2 µV/fF. The residual offset caused by the chargeinjection can be expressed as:

. (2-21)

This implies that effort has to be put into the layout of differentialchoppers and clock lines when designing a chopper amplifier, because themetal to metal capacitance of signal lines can be in the order of fF’s.

2.4 Chopped auto-zeroed amplifierAs already discussed in section 2.2.1, a fully integrated amplifier with threecascaded auto-zeroed amplifiers with output offset storage has been reported[2.9]. Subsequently, these stages were also chopped [2.3]. This implementationachieved an input referred offset of less than 5 µV. Theoretically, the combinationof auto-zeroing and chopping would have a better offset performance because theresidual offset of the auto-zero amplifier is being chopped. Practically in some

VFc VinVa

offset

Ib

Fig. 2-16 Illustration of residual offset caused by demodulatedspikes caused by a mismatch between C3 and C4.

Vos res2,2 C3 C4–( )VFFC

G1------------------------------------=

Vos res, Vos res1, Vos res2,+=


30

applications the charge injection of the chopper is the dominant source ofresidual offset, and auto-zeroing will only have a small effect on the residualoffset.

However, there is also an effect of the noise, because the folded whitenoise can be modulated as well. This reduces the effect of folded white noise.In figure 2-8 it is shown that an auto-zero amplifier with a 50% duty cycle hasa minimum in the noise PSD at two times the auto-zero frequency. Thismeans that if an auto-zero amplifier running with a 50% duty cycle is choppermodulated with the double auto-zero frequency, that the noise around DCwould then be optimal. This has been sketched in figure 2-17. Note that in animplementation, the chopper and the switches driven by F1 can be combined.The reduction in noise at low frequencies as well as the rise in noise towardsthe chopper frequency is sketched in figure 2-18.

A

Vos

Vin Vout

+

-

+

-

+

-

+-

C1

F1 F1C1

F1

F1

FC FC

F1

F1

F1F1

FC

off

on

off

on

Fig. 2-17 A chopped auto-zero amplifier, with an auto-zero duty cycle of50% and a chopper frequency two times higher than theauto-zero frequency.

noisePSD

f(Hz)

noisePSD

f(Hz)FC

noisePSD

f(Hz)FAZ

noisePSD

f(Hz)FC=2FAZ2FAZNo dynamic offset compensation

Chopping Auto-zeroing Chopped auto-zeroing

Fig. 2-18 General output PSD of different kind of dynamic offsetcompensation techniques [2.10].

31

Switching non-idealities

The folded noise can be modulated to even higher frequencies byusing a higher chopper frequency. During each signal phase the polarity ofthe chopper should be positive and negative for an equal time, to average outthe noise contribution, that is sampled during each auto-zero phase.Therefore, optimal noise at low frequencies will be achieved when:

and ... (2-22)

The technique of using both an auto-zero and a chopper technique was used in[2.10].

2.5 Switching non-idealitiesAll the dynamic offset compensation techniques presented in this work haveone thing in common: CMOS transistors are used as switches. Therefore, thenon-ideal behaviour of CMOS switches needs to be discussed.

An ideal switch is an element that does or does not allow a signalthrough depending on the driving signal. In other words, when it is open oroff the impedance is infinite, and when it is closed or on the impedance iszero. Furthermore, there is no delay between the driving signal and the switchaction.

In reality a CMOS switch has a non-infinite impedance Roff when it isoff and a non-zero Ron impedance when it is on. This Roff is typically100 MΩ while Ron can be as high as 10 kΩ for minimum size switches.A voltage drop will thus occur when current is flowing through an open switch.In these cases the Ron needs to be taken into account.

Secondly, there is a small time delay between the signal driven to thegates of the switch and the switching action. The main cause of delay is therelatively big capacitance of the clock line. To avoid delay time differencesbetween lines it is better to balance the clock-line capacitances, i.e. to makeclock lines the same size.

However, the main problem for dynamic offset compensation circuits is theso-called charge injection. This charge injection is caused by two phenomena:parasitic capacitive feed-through and the redistribution of channel charge.

FCnd--- F1= n 1 2 3, ,=


32

In figure 2-19 the channel charge injection and parasitic capacitivefeed-through are modelled. When the transistor is open, a layer of minoritycarriers exists under the gate between the source and drain of the transistor.This charge can be expressed for a NMOS switch as:

. (2-23)

For a minimum size switch in a 0.7µm process, the values that can be foundare W=1 µm, L=0.7 µm, VT=0.7 V and Vgs=5.5 V Cox=2 fF/µm2, whichleads to . This charge can cause a 6.72mV voltage step on a 1pFcapacitor.

This channel charge has to go somewhere when the transistor isturned off. Depending on the structure of the switch and the loads at the drainor source, it will partly flow into the load of the drain and partly into the loadof the source. The charge currents Iinjd and Iinjs disturb the drain and thesource respectively.

The parasitic capacitive feed-through can be modelled bygate-to-source Cgs, gate-to-drain Cgd, and gate-to-bulk capacitances Cgb,which means that the gate signal not only drives the on or off state of thetransistor but it also disturbs the drain, source and bulk of the transistor. Thegate-source capacitance charge injection can be expressed by:

, (2-24)

poly gate

drain diffusion

source diffusion

alu drain connection

alu source connection

alu gate connection

channel charge

Well

alunimum bulk connection

diffusion

IsId

Cgd CgsCgs

Fig. 2-19 Charge injection model.

qinj ch, Vgs VT–( )WLCox=

qinj ch, 6.72 fC=

qinj C, ∆VgsCgs=

33


where ∆Vgs is the voltage swing over the parasitic capacitance. Note that Cgsis the sum of all capacitances from driving (gate) lines to signal (source) lines.Both the capacitive feed-through and the redistribution of channel chargeeffects have a linear dependency on Vgs. This also means that changes in thesource and gate voltage have an effect on the residual offset, which impliesthat charge injection is also a limit to the DC power supply rejection ratio(PSRR) as well as the DC common-mode rejection ratio (CMRR).

From a designer’s point of view the two effects are notdistinguishable from each other since they both happen at the moment ofopening or closing of the transistor. Therefore, they are both considered to becharge injection. In this work some practical layout issues are discussed inappendix A to avoid disastrous clock feed-through effects.

2.5.1 Charge injection reduction tactics

As already mentioned in the analysis of the residual mismatch due tomismatch in section 2.2, an effective method to reduce residual offset causedby charge injection is to use bigger capacitors as auto-zero capacitors.Another similar way is to minimize the charge injection by using minimumsize transistors as switches. However, in some applications a minimum sizeswitch will have a too high Ron. In this section some other ways to cope withthe charge injection challenge are presented.

Dummy switchesCharge injection of a main transistor (M1 in figure 2-20) can be removed bymeans of a second dummy transistor (M2 in figure 2-20). Generally, there aretwo ways to implement a dummy switch [2.11]: It can be connected in serieswith the switch or in parallel. This is shown in figure 2-20, where CH ismodelled to be charged with the charge injection of the switches.

In figure 2-20a this is done by putting a second transistor of half thewidth in series with the main transistor. The idea is that, when closing M1,half the charge injection would go towards CH and Vout, and that the other halfwould go towards Vin. A transistor of half the size driven by the oppositeclock signal would remove the charge injection going into CH.

Unfortunately, because of asymmetry in the layout of the switch andthe unequal load impedances at the drain and source, the assumption of equalsplitting of charge between source and drain is generally not true [2.11].


34

In figure 2-20b a second transistor is used in parallel to the maintransistor. The idea is that while the main transistor M1 closes, also the secondtransistor M2 closes, and that the PMOS charge injection consisting of holescompensates for the charge injection of the NMOS switch consisting ofelectrons. The PMOS transistor in figure 2-20b will, in first order, onlyremove the channel charge injection component at one Vin voltage. Thisvoltage can be expressed by solving the following equation:

, (2-25)

which leads to . (2-26)

Furthermore, the parasitic capacitive feed-through overlap capacitancesof NMOS and PMOS are not equal. As a result, the total charge injection effectwill differ from equation (2-25). In conclusion, the use of dummy switches willnever totally cancel charge injection. Nevertheless, it does reduce chargeinjection.

Differential circuitsAnother way to deal with charge injection is to use differential circuits. Thecharge injection in a fully differential structure is, first of all, a common-modeissue. Only the charge injection mismatch will cause a differential signal. Thishas already been discussed section 2.3.3.

M1

W1/L1

M2

M2

M1

CH CH

VinVin Vout Vout

FCFC FC

a b/W1/L11

2

FC

Fig. 2-20 Charge injection cancellation of a NMOS switch withdummy switches. (a) Half width NMOS in series (b)PMOS in parallel.

VFC Vin opt, VT n,––( )WLCox Vin opt, VT p,––( )– WLCox=

Vin opt,VFC VT n,– VT p,–

2-----------------------------------=

35


In figure 2-21 a differential sampling circuit is depicted. In this figurewhen both qinj1 and qinj2 are equal, they do not have a consequence on thedifferential charge and thus do not influence the differential voltage over CH.Only the differential charge injection or charge injection mismatch will havean effect. This charge injection mismatch is expected to be much smaller thanthe absolute charge injection.

From equation (2-23) it can already be concluded that a differentialinput voltage would already lead to a charge injection mismatch, since the Vgsof M1 is not equal to the Vgs of M2 [2.11]. This charge injection can beexpressed as:

. (2-27)

This also implies that an auto-zero or chopper amplifier with a higheroffset has an increased charge injection problem. Therefore, a combination ofdynamic offset compensation techniques would lead to lower residual offsets.

Mismatch of the parasitic capacitances from gate lines to source linesis critical. Any systematic parasitic capacitance due to layout asymmetrywould lead to residual offset. This has already been analysed for a chopperamplifier in section 2.3.3.

When equation (2-23) is investigated, it can be concluded that the W,L, Cox and threshold mismatch leads to channel charge mismatch. Mismatchcharacteristics of minimum size or small MOS switches are usually notavailable. However, if the charge injection of a MOS transistor is proportionalto the area [2.12], then it can be assumed that the mismatch is proportional to

M1

CH

Vin1

FC

M2

Vout1

qinj2

qinj1

Vin2 Vout2

M1

Vin1

FC

M2

Vout1qinj1

Vin2 Vout2

CH1

CH2

qinj2

=

Fig. 2-21 Differential sampling circuit with charge injection.

∆qinj Vin, qinj1 qinj2– WLCox Vin2 Vin1–( )= =


36

the square root of the area. This would imply that minimum size switches arethe best choice to minimize channel charge injection.

The use of dummy transistors in differential dynamic offsetcompensated circuits does not reduce residual offset, because dummyswitches will only compensate for the absolute charge injection, which causescommon-mode charge injection. However, dummy switches do cause morecharge injection mismatch, because their use increases the effective area of aswitch, which causes more residual offset.

Fixed voltage swingThe most straight forward approach is to use digital signals to operate theswitches of dynamic offset compensated circuits. However, in equations(2-23) and (2-24) it can be seen that the charge injection is dependent on thevoltage swing with which the switch is driven.

This would mean that if the switch were driven with a digital signal,then the DC PSRR and DC CMRR would roughly be limited from around100–120 dB. There are ways to implement circuits that limit the voltage swingdriving the switches independently from the power supply voltage. In thisbook the implementation of a dynamic offset compensated current-senseamplifier is described in section 6.3. The input common-mode (CM) voltageVinCM ranges from 2 to 28 V. The input PMOS switches are driven fromVinCM to VinCM–2 V by a level shift circuit. This technique achieves a 143 dBCMRR over the full input CM range and it even achieves a 152 dB CMRRwhen the CM ranges from 5 to 28 V. The same amplifier also has a referenceinput, which has a common-mode range from 0 to VDD-1.5 V. This input ismodulated with a normal digital signal from 0 to VDD. The CMRR from thisinput voltage is 120 dB.

2.5.2 Charge injection suppression circuits

In this section three circuits will be discussed, in which charge injectionreduction techniques are used. These techniques are: nested chopping, spikefiltering, and the use of dead band. All these techniques have beenimplemented in chopper amplifiers.

37


Nested chopperFrom equation (2-19) it can be seen that the residual offset due to mismatchis proportional to the chopper frequency. In the nested chopper technique thisresidual offset is also chopped.

In figure 2-22 the nested chopper amplifier principle is shown. Theinner choppers CH1H and CH2H run at a frequency FCH. This frequency canbe chosen optimally for noise, i.e. FCH should be chosen higher than the 1/fcorner frequency. This high frequency will lead to a relatively high residualoffset. The nested choppers CH1L and CH2L modulates this residual offset ata low frequency FCL, which strongly reduces the offset. The frequency FCLcan be chosen optimal for the input signal. Thus, the nested choppers reducesthe charge injection of the inner choppers. With this technique a 100 nVoffset was obtained with FCH=2 kHz and FCL=15,6 Hz [2.13].

This amplifier now has two ripples at the output. One ripple is causedby the offset of the amplifier A1, which is modulated with the frequency FCH.The other ripple is caused by the residual offset, which is modulated atfrequency FCL. To filter this ripple a LPF is needed with a –3 dB frequencysmaller than FCL. This makes this technique useful in low frequencyapplications, like custom sensor read out electronics, such as implementationsof fully integrated Hall-sensors [2.14] and temperature sensors [2.15] [2.16],but not for general purpose amplifiers.

Spike filteringWhen it is assumed that charge injection causes residual offset, and thatcharge injection is an effect which occurs during the switching action of aswitch, then it can also be assumed that the charge injection causes voltagespikes with high frequency. It can be assumed that the spikes have spectral

Vout

CH2H CH2LCH1HCH1L

+-

Vin+

-A1Va

+-

Vb+-

LPF Vlfp+-

C1C2

VFCH

R1

R2

VFCL

Fig. 2-22 Nested chopper amplifier principle.


38

components on the odd harmonics of the chopper frequency [2.5]. This issketched in figure 2-23, which implies that the spikes can be filtered bymaking the amplifier A1 in figure 2-9 selective for specific frequencies.

An amplifier using this technique is illustrated in figure 2-24. Alow-pass filter was used in [2.17]. A thorough analysis of this technique canbe found in [2.5], in which it is concluded that the optimal choice is a secondorder low-pass or band-pass filter with a cut off frequency of two times thechopper frequency. An implementation with a band-pass filter can be foundin [2.1]. This implementation was improved in [2.18], where a band-passfilter was matched with the chopper frequency generator so that the inputoffset voltage could be reduced to 0.54 µV.

This technique leads to amplifiers having a bandwidth equal to thechopper frequency or less. This is useful for custom amplifiers in sensor readout circuits.

Vamodulatedsignal

0 FC 3FC 5FC

filter

spike harmonics

Fig. 2-23 Modulated signal and spike harmonics.

Vout

CH2CH1

+-

Vin+

-A1 A2Va

+-

Vb+-

LPF Vlfp+-

C1C2

VFC

R1

R2

LPForBPF

Fig. 2-24 Chopper amplifier with a frequency selective amplifier toimprove residual offset by filtering spikes.

39


Delayed modulation and guard bandInstead of putting effort into filtering the spikes in the frequency domain, it isalso possible to filter the spikes in the time domain. In figure 2-25a, amodulated amplifier is shown consisting of a modulator M, amplifier A1, anddemodulator D.

In figure 2-25b, a delayed demodulation scheme is shown. The idea isthat when the shape of the voltage spike is known, a fixed delay can be usedto allow the demodulated spike to have an average value of zero. Thus, thespike is used to compensate for itself. This has been successfullyimplemented [2.19] by using a low-pass filter behind the amplifier to shapethe spikes. It achieved a 1 µV offset with a 6 kHz modulator frequency.However, a mismatch between the shape of the spike and the delay stillcauses residual offset.

Another approach, which is simpler to implement, is shown infigure 2-25c. In this dead-band or guard-band approach, the output voltage isnot modulated while the spike is present. This technique has been used in[2.20] [2.21] and [2.14] for custom read out electronics for sensors. In oneimplementation [2.21], an amplifier with an average 200 nV input offset wasrealised.

In [2.14] a nested chopper technique was used. This implementationused a guard-band for the inner chopper and a partially digitally-implemented

Vout

+-

Vin+-

A1

Va+-

Vb+-

FM

FDVout

Va

FM

FD

Vout

Va

FM

FD

t t

M

D

b a c

10-1

10-1

10-1

10-1

Fig. 2-25 (a) Modulated amplifier, (b) delayed demodulation clockdiagram, (c) dead band clock diagram.


40

nested chopper to obtain a 3.65 µT 3σ offset Hall sensor, which is equivalentto an input voltage offset well below 200 nV.

2.6 ConclusionsIn this chapter, two offset compensation techniques have been described:Auto-zeroing and chopping. The first one can be described as a time domaintechnique, the latter as a frequency domain filtering technique. They lead to asignificantly different noise performance for low-frequency noise.

In addition, switch non-idealities of MOS transistors were discussed,since both techniques use MOS switches. The major cause of residual offsetis charge injection, and design tactics as well as a couple of circuit-level tominimise the charge injection were discussed. Making use of differentialcircuits seems the best design tactic to reduce charge injection effects.

2.7 References[2.1] C.C. Enz, G.C. Temes “Circuit techniques for reducing the

effects of op-amp imperfections: autozeroing, correlateddouble sampling, and chopper stabilization”, Proc. IEEE, pp.1584–1614, Nov. 1996.

[2.2] B. Razavi, B.A.Wooley, “Design techniques for high-speed,high-resolution comparators”, IEEE JSSC, pp. 1916–1926,Dec. 1992.

[2.3] R. Poujois J. Borel, “A low drift fully integrated MOSFEToperational amplifier”, IEEE JSSC, pp. 499–503, Aug. 1978.

[2.4] M. Degrauwe, E. Vittoz, I. Verbauwhede, “A micropowerCMOS-instrumentation amplifier”, IEEE JSSC, pp. 805-807,June 1985.

[2.5] C.C. Enz, “High precision CMOS micropower amplifiers”,Ph.D. Thesis, These No. 802, Ecole Polytechnique Federale deLausanne, http://library.epfl.ch/en/theses/?nr=802, 1989.

[2.6] A. Bakker, J.H. Huijsing, “High-accuracy CMOS smarttemperature sensors”, Dordrecht: Kluwer, 2000.

41

References

[2.7] A. Bakker, J.H. Huijsing, “A CMOS chopper opamp withintegrated low-pass filter”, Proc. ESSCIRC, pp. 200–203, Sep.1997.

[2.8] K.C. Hsieh, P.R. Gray, D. Senderowicz, D.G. Messerschmitt,“A low-noise chopper-stabilized differential switched-capacitor filtering technique”, IEEE JSSC, pp. 708–715, Dec.1981.

[2.9] R. Poujois B. Baylac, D. Barbier, J. Ittel, “Low-level MOStransistor amplifier using storage techniques”, IEEE ISSCC,pp. 152–153, Feb. 1973.

[2.10] A.T.K. Tang, “A 3µV-offset operational amplifier with input noise PSD at DC employing both chopping

and autozeroing”, IEEE ISSCC, pp. 386–387, Feb. 2002.[2.11] B. Razavi, “Design of analog CMOS integrated circuits”,

McGraw-Hill, International edition, 2001.[2.12] M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers,

“Matching properties of MOS transistors”, IEEE JSSC, pp.1433–1439, Oct. 1989.

[2.13] A. Bakker, K. Thiele, J.H. Huijsing, “A CMOS nested-chopperinstrumentation amplifier with 100-nV offset”, IEEE JSSC, pp.1877–1883, Dec. 2000.

[2.14] J.C. van der Meer, F.R. Riedijk, E. van Kampen, K.A.A.Makinwa, J.H. Huijsing, “A fully integrated CMOS hall sensorwith a 3.65µT 3σ offset for compass applications”, IEEEISSCC, pp. 246–247, Feb. 2005.

[2.15] M.A.P. Pertijs, K.A.A. Makinwa, J.H. Huijsing, “A CMOSsmart temperature sensor with a 3σ inaccuracy of 0.1ºC from–55ºC to 125ºC”, IEEE JSSC, pp. 2805–2815, Dec. 2005.

[2.16] K.A.A. Makinwa, M.F. Snoeij, “A CMOStemperature-to-frequency converter with an inaccuracy of lessthan 0.5ºC 3σ from 40ºC to 105ºC”, IEEE JSSC, pp. 2992–2997,Dec. 2006.

[2.17] C.C. Enz, E.A. Vittoz, F. Krummenacher, “A CMOS chopperamplifier”, IEEE JSSC, pp. 335–342, June 1987.

[2.18] C. Menolfi, Q. Huang, “A fully integrated, untrimmed CMOSinstrumentation amplifier with submicrovolt offset”, IEEEJSSC, pp. 415–420, Mar. 1999.

20nV Hz⁄


42

[2.19] C. Menolfi, Q. Huang, “A chopper modulated instrumentationamplifier with first order low–pass filter and delayedmodulation scheme”, Proc. ESSCIRC, pp. 54–57, Sep. 1999.

[2.20] A. Bilotti, G. Monreal, “Chopper-stabilized amplifiers with atrack-and-hold signal demodulator”, IEEE Trans. Circuits andSystems I, pp. 490–495, Apr. 1999.

[2.21] Q. Huang, C. Menolfi, “A 200nV offset noise PSD5.6kHz chopper instrumentation amplifier in 1µm digitalCMOS”, IEEE ISSCC, pp. 362–363, Feb. 2001.

6.5nV Hz⁄

3

43

Dynamic Offset Compensated Operational Amplifiers 3

3.1 IntroductionTypical sensor output signals are in the microvolt range and have bandwidthsranging from DC up to a few kilohertz. Boosting such signals to levelscompatible with typical analog-to-digital converters requires low-offsetoperational amplifiers with gain-bandwidth (GBW) products of a fewmegahertz. For example, implementing an amplification of 40 dB with a gainaccuracy of 1% and a bandwidth of 1 kHz calls for a low-offset operationalamplifier with a GBW of at least 10 MHz. Achieving such GBW products incombination with a microvolt-level input offset voltage is not straightforward.

In the previous chapter, two dynamic offset compensation techniqueswere discussed: chopping and auto-zeroing. Chopping is a frequencymodulation technique, which requires low-pass filters in the signal path tofilter chopper ripple out. Therefore, chopping alone is not suitable forbroadband applications. Auto-zeroing is a time domain technique in whichthe offset is measured and afterwards subtracted from the signal. Therefore,this technique alone is not suitable for continuous-time operation. However,in this chapter it will be shown that, by using these techniques in multi-pathtopologies, broadband continuous-time amplifiers can be realized.

Dynamic Offset Compensated Operational Amplifiers

44

3.2 Ping-pong operational amplifierAs described in the previous chapter, the auto-zero technique is not directlysuitable for use in a continuous-time general purpose amplifier. During thesampling of the offset, it is necessary to take the amplifier out of the signalpath. Therefore, implementations of amplifiers have been developed whichsample the offset during start-up or at the request of a user [3.1] [3.2]. Thishas the advantage that there is no signal aliasing effect, because duringoperation there is no switching action. However, there is also no effect on 1/fnoise and offset drift due to temperature changes during operation.

Another way to make a continuous-time amplifier by using theauto-zero technique is the ping-pong technique [3.3]. A ping-pong auto-zerooperational amplifier uses two auto-zero amplifiers, which run in parallel toeach other. While one is being auto-zeroed the other one is used to amplifythe signal (figure 3-1). This way a continuous-time broadband operationalamplifier is created by time-domain multiplexing two auto-zero amplifiers.One of the amplifiers is always present to allow accurate and stable feedback.This technique was used to implement a rail-to-rail input [3.4]. This techniquewas also implemented with a SAR ADC and digital offset storage [3.5].

A combination of this ping-pong technique together with the choppertechnique has been used to obtain a 20 nV/√Hz noise PSD for <1 kHzoperational amplifier [3.6] [3.7]. A disadvantage of the ping-pong techniqueis that spikes are caused because the voltages Vb1 and Vb2 at the output of the

G1

V1

VinVout

Vc1

F1

F2

+

-+

-

+

-

+

-

+-

C1

F1

G2+

-

F2

I1

I2

V2+ -

G3

V3

Vc2

F2

F1

+

-

+

-

+-

C2

F2

G4+

-

F1

I3

I4

V4+ -

G5

+

-

VaVb1

Vb2

Fig. 3-1 Concept of a ping-pong amplifier.

45

Offset-stabilized amplifiers

input amplifiers have to switch between the offset compensating voltages Vc1and Vc2 and the voltage required at the input of the output amplifier Va. Thisresults in spikes at the output. This effect can be reduced by replacing C1 andC2 with active integrators with the same input common-mode voltage as theoutput stage G5. Nevertheless, spikes still remain because switching occurswithin the signal path. This effect can be reduced by using a multi-pathtechnique in which a signal path does not have any switches. Thesetechniques will be discussed in the next section.

Implementations of ping-pong amplifiers with a multi-path structureare also commercially available [3.8]. In these amplifiers the ping-pongamplifier works in a low-frequency path and a high-frequency path is neverdisconnected from the signal path [3.9].

3.3 Offset-stabilized amplifiersOffset-stabilization is another technique with which a dynamic offsetcompensated broadband amplifier can be designed. In this technique anauxiliary amplifier is used to compensate for the offset of a main amplifierwhich is never disconnected from the signal path. In figure 3-2 the basicconcept of offset-stabilization is sketched. A main operational amplifier Gmwith an offset Vm, is being offset-stabilized by a stabilizing amplifier Gn witha hypothetical offset of 0 V. Stage Gm2 acts as an auxiliary input of the mainamplifier. Stabilizing amplifier Gn applies a voltage to the inputs of Gm2,which drives a current to the output of Gm to compensate for its input offset

+-

Gn

GmVin

Vm

R1

R2

+

-+ -

+

- +-

+ +-

Vout

+-Va

Gm2+-

+

Fig. 3-2 Offset-stabilized amplifier concept, where Gncompensates for the offset Gm via Gm2.


46

voltage. The resistors R1 and R2 have been added to indicate a feedbacknetwork

It is important to note that this technique only works in negativefeedback amplifiers. In a feedback configuration the differential input voltageVa of Gn, is substantially equal to the offset Vm. The amplifier Gn measuresthis voltage and drives it to zero by applying a signal to Gm2, that acts as theauxiliary input of Gm. The residual offset due to finite gain of the combinedamplifier can then be expressed as:

, (3-1)

where An, Am, and Am2 are the DC voltage gains of the stabilizing amplifierGn, the main amplifier Gm, and the auxiliary input of the main amplifier Gm2,respectively. It can be concluded from this that the combined voltage gain ofthe stabilizing amplifier and the auxiliary input of the main amplifier has to bemuch larger than the voltage gain of the main amplifier. Reducing a 10 mVworst-case offset voltage to a 1 µV residual offset, while the voltage gain ofauxiliary input of the main amplifier is ten times lower than the voltage gainof the main amplifier itself, would require a minimum voltage gain of thestabilizing amplifier of 100 dB.

This topology can also be seen as a multi-path amplifier in which thecascade of the stabilizing amplifier and the auxiliary input of the mainamplifier form the high-gain low-frequency path, and the main amplifier itselfis the high-frequency path. Low-frequency characteristics will, therefore, bedetermined by the stabilizing amplifier. In that case, for instance, the lowfrequency noise is determined by the noise of the stabilizing amplifier Gn,while the unity gain frequency is determined by the main amplifier Gm.

Since the low-frequency path has a certain bandwidth, theoffset-stabilization loop cannot distinguish 1/f noise from offset. Therefore,the stabilizing loop of an offset-stabilized amplifier will also reduce the 1/fnoise of the main amplifier.

The stabilizing amplifier has to be a low offset amplifier. Therefore, itcan either be implemented by using the auto-zero or chopper technique.Therefore, two offset-stabilization methods can be distinguished: auto-zerooffset-stabilization and chopper offset-stabilization. Combinations of thesetechniques can also be used. These will be discussed in the next sections, and

Vos res gain, ,Am

AnAm2----------------Vos≈

47


implementations of offset-stabilized amplifiers are presented in chapters 5and 6.

3.3.1 Auto-zero offset-stabilized amplifiers

A diagram of a system using auto-zero offset-stabilization is shown infigure 3-3. During phase F2 the stabilizing amplifier Gn samples its ownoffset voltage. In this phase stabilizing amplifier Gn measures its own offsetvoltage and stores an offset compensating voltage on capacitor C1. Accordingto the theory discussed in section 2.2.3, the residual offset due to finite gain ofGn can then be expressed as:

, (3-2)

where An2 is the DC gain of Gn2, which acts as an auxiliary input of thestabilizing amplifier Gn. During phase F1, the stabilizing amplifier measuresthe offset voltage of the main amplifier Gm, and stores an offset compensatingvoltage on capacitor C2. The resulting residual input referred offset due tofinite gain can be expressed as:

, (3-3)

where An, Am, An2 and Am2 are the DC voltage gains of the stabilizingamplifier, the main amplifier, and the gains from their auxiliary inputs stages

+-

Vin

Vm

R1

R2 + -

+-

Vout

Gn+

-+-

Gm+

-++

Vn+ -

+-Va

C2C1

F1

F1

F2

=+-

Vin

Vm

R1

R2 + -

+-

Vout

Gn+

-+

Gm+

-+

Vn+ -

+-Va

C2C1

F1

F1

F2

F2

Gm2+-

+Gn2+

-+

F2

Fig. 3-3 Auto-zero offset-stabilization. The right-hand schematicis commonly used.

Vosn res gain, ,Vn

1 An2+----------------=

Vos res gain, ,Am

AnAm2----------------Vm

Vn

1 An2+----------------–≈


48

Gn2 and Gm2. Compared to the ideal circuit, an additional source of residualoffset is the finite gain An2 and the offset Vn of the stabilizing amplifier.

Furthermore, the noise aliasing associated with auto-zeroing will giverise to a higher input-referred noise voltage at low frequencies, as discussedin section 2.2.4 [3.10]. A detailed empirical analysis of the noise behaviour ofthese kind of amplifiers can be found in [3.11]. Another drawback of thiscircuit is that, as with all capacitive auto-zeroed techniques, the chargeinjected by the switches is also stored on the offset compensating capacitorsC1 and C2. Therefore, these capacitors need to be relatively large. Anotherdrawback is that the open-loop gain of the whole amplifier is significantlydifferent in the phases F1 and F2. This can be a cause of aliasing for signalsabove the clock frequency. Probably for this reason multi-path ping-pongamplifiers have also been implemented [3.8] [3.9].

In the literature this topology is known as chopper stabilized [3.12],[3.13] or continuous-time auto-zero [3.10]. Devices with this topology arecommercially available [3.12] [3.14], and achieve typical input offsetvoltages of 1 µV. This topology is also used in a device which could operateup to 200ºC [3.15].

3.3.2 Chopper offset-stabilized amplifiers

Some so-called chopper-stabilized amplifiers [3.12] [3.13] use auto-zeroedstabilizing amplifiers and are, therefore, auto-zero offset-stabilized amplifiers.A true chopper offset-stabilized amplifier, which uses a chopper compensationamplifier, has been proposed in [3.16]. A chopper offset-stabilized amplifier hasbeen presented [3.17] using only 17 µA of supply current.

+-

Gn

GmVin

Vm

R1

R2

+

-+ -

+

- +-

+ +-

VoutVn+ -CH2 CH1

LPF

+-Va

Gm2+-

+

Fig. 3-4 Chopper offset-stabilization.

49


In the chopper offset-stabilized amplifier shown in figure 3-4, thechopper amplifier composed of chopper CH2, stabilizing amplifier Gn, andchopper CH1, senses the offset of the main amplifier Gm. A low-pass filterLPF removes the chopper residuals that are caused by the offset Vn ofstabilizing amplifier Gn. The residual offset due to finite gain is thenexpressed by equation (3-1).

The effects of noise in chopper offset stabilized amplifiers is sketchedin figure 3-5. The offset and 1/f noise of the stabilizing amplifier itself aremodulated to the chopping frequency Fc, and are removed by the low passfilter. For effective suppression of 1/f noise, the bandwidth of the stabilizingloop as well as the chopper frequency should, therefore, be larger than themain 1/f noise corner frequency of the main amplifier. Thus, for optimal noisebehaviour, the –3 dB frequency of the LPF should be chosen higher than the

corner frequency of the main amplifier Gm, and the chopper frequencyshould be high enough to properly filter out the chopper residuals.

When the bandwidth of the stabilizing loop and the chopper frequencyare chosen optimally, the white noise level of the stabilizing amplifier Gn willbe equal to the low frequency noise. In contrast, the white noise at lowfrequencies of a similarly dimensioned auto-zero offset-stabilized amplifierwould be significantly higher due to noise aliasing.

In conclusion, compared to the use of auto-zero offset-stabilization, theuse of chopper offset-stabilization should lead to better performance withrespect to noise and offset. Therefore, this topology is used in theimplementations discussed in chapter 5.

noisePSD

f(Hz)

noisePSD

f(Hz)FC

noisePSD

f(Hz)Noise of Gm Noise of Chopped

Gn and LPFNoise of chopper offset stabilized amplifier

FC

Fig. 3-5 Noise in chopper offset stabilized amplifiers.

1 f⁄


50

3.3.3 Frequency compensation

In figure 3-6 a chopper offset-stabilized amplifier is depicted as a multi-pathamplifier [3.16]. In this circuit, G2 and G1 form a high-frequency path, whileG4, G3, and G1 form a chopped low-frequency path. Stage G3 is effectivelythe auxiliary input of G2. The Miller capacitors C11, C12, C31, and C32 form amulti-path nested Miller frequency compensation network [3.18]. A problemwith this circuit is that the offset V4 of G4 together with the choppers give riseto a chopper ripple. The circuit itself lacks a low-pass filter except for theMiller capacitors, which limit the unity gain frequency of the whole amplifier.

An improved design of this circuit is shown in figure 3-7. Anintegrator composed of transconductor G5 and capacitors C51 and C52 hasbeen added to the low frequency loop. This has the advantage that theintegrator acts as a low-pass filter and limits the chopper ripple. The circuitshown in this figure can be considered a multi-path amplifier in which thecascaded transconductances G2 and G1 form the low-gain/high-frequencypath, while the cascaded transconductances G4, G5, G3, and G1 form thehigh-gain/low-frequency path. Instead of multi-path nested Millercompensation, multi-path hybrid-nested Miller compensation has beenimplemented [3.19] [3.20]. If the topologies are designed to have a smooth

+-

+-

G4 G3

V4+ -

V3+ -

C32

C31

G2 G1 Vout

C11

C12

Vin

V2

R1

R2 + -

FCFC

+-Vb

++

-+

-

+

-

+

-

+

-

+

-

+

-

Fig. 3-6 Conceptual chopper offset-stabilized multi-path nestedMiller compensated operational amplifier.

51


roll-over of both paths, then the unity gain frequency of both topologies canbe given by:

, (3-4)

where C3 and C1 are the values of capacitors C31 and C32, and, C11 and C12,respectively. The modulated offset V4 of G4 is now filtered by the integrator.However, it still gives rise to chopper ripple in the form of a triangular waveat the output Vb of the integrator, which in turn gives rise to a triangular waveat the input of the whole amplifier. The input referred peak-to-peak voltage ofthis triangular wave of the topology shown in figure 3-7 is given by:

, (3-5)

where FC is the chopper frequency and C5 is the value of the integratorcapacitors C51 and C52.

Compared to the compensated high-frequency path, this path containsan extra low-frequency pole due to the presence of the integrator. Therefore,without the presence of capacitors C31 and C32, the open loop frequency ofthe amplifier response will have a –40 dB/decade roll-off at low frequencies.

f0dBG4

2πC3------------

G2

2πC1------------= =

Vin pp–V4G4G3

2FCC5G2----------------------=

+-

+-

G5 G3

V4+ -

V5+ -

C32

C31

C52

C51

I3

G2 G1Vout

C11

C12

Vin

V2

R1

R2 + -

FCFC

G4+-Vb+

- +

-

++

-+

-

+

-

+

- +

-

+

-

+

-

Fig. 3-7 Chopper offset-stabilization using an active integrator andmulti-path hybrid-nested Miller compensation.


52

As a result, the amplifier is only conditionally stable. This means that in orderto ensure stability without external frequency compensation, the closed loopgain must be limited to below a certain value, which is not desirable in ageneral purpose operational amplifier. Bode plots of the amplifier depicted infigure 3-7 are illustrated in figure 3-8.

The topology shown in figure 3-7 can be seen as a four-stagelow-frequency path and two-stage high-frequency path. The frequencycompensation can also be extended to more stages, as shown in figures 3-9and 3-10. The benefit of the topology shown in figure 3-9 is that the two-stage

without C31 &C32 with C31 &C32

40dB/dec

20dB/dec

|H|

f

|H|

f

gain limit

Fig. 3-8 Sketched bode plot of the amplifier topologydepicted in figure 3-7 with and withouthybrid-nested Miller capacitors C31 and C32.

+-

+-

G5+

- +

-G3

C32

C31

C52

C51

I3

G2 +G1Vout

C11

C12

Vin

R1

R2

G4

G6

C61

C62

+

-+

-

+

-

+

-

+

-

+

- +

-

+

-

+

-

Fig. 3-9 Chopper offset-stabilization using an active integrator andmulti-path hybrid-double-nested Miller compensation.

53


output stage consisting of G6 and G1 can be easier to implement. A benefit ofa two-stage integrator consisting of G7 and G5 as shown in figure 3-10 is theadditional voltage gain of the low-frequency path, which according toequation (3-1) leads to a lower residual offset due to finite gain.

The unity gain frequency of the topologies shown in figures 3-9 and3-10 can be expressed by:

, (3-6)

where C6 is the value of capacitors C61 and C62. The operational amplifierimplementation discussed in the next chapter uses the topologies of figures3-7 and 3-10. Referring to figure 3-7, it can be noticed that the offset voltageV5 of the integrator appears as a square wave voltage over the capacitor Cp4.

f0dBG4

2πC3------------

G2

2πC6------------

G6

4πC1------------= = =

+-

+-

G5+

- +

-G3

C32

C31

C52

C51

I3

G2 +G1Vout

C11

C12

Vin

R1

R2

G4

G6

C61

C62

+

-+

-

+

-

+

-

+

-

+

- +

-

+

-

+

-G7

C72

C71

+

-

+

-

Fig. 3-10 Chopper offset-stabilization using an active two-stage Millercompensated integrator and multi-path hybrid-double-nestedMiller compensation.


54

Charging and discharging this capacitor leads to an alternating output currentat the output of G4, which effectively leads to a residual offset at the input ofthe whole amplifier. The residual offset due to this parasitic capacitance canbe expressed as:

. (3-7)

This means that either the parasitic capacitance needs to be minimized or theoffset of the integrator can be minimized, for instance by using nestedoffset-stabilization techniques, as will be shown in all the implementationspresented in chapters 5 and 6.

The multi-path hybrid-nested Miller frequency compensation can alsobe used in auto-zero offset-stabilized amplifiers. An example of such atopology is given in figure 3-11. In phase F2 the offset V5 of G5 causes acurrent, which is integrated by the integrator composed of G6 and capacitorsC61 and C62. The integrator produces a voltage at the input of G7, which acts

+-

+-

C31

G2 G1Vout

C11

C12

Vin

V2

R1

R2 + -

V5+ -

G4

C32

C42

C41

I3

G6G7

G5

C61

C62

F1 F1

F2

F2 G3

Fig. 3-11 Auto-zero offset-stabilization using an active integratorand multi-path hybrid-nested Miller compensation.

Vos res par, ,4V5FCCp4

G4------------------------=

55


as an auxiliary input stage for G4 and compensates for the offset, as discussedin section 2.2.3. In phase F1 the offset voltage V2 is measured by G5 andcompensated for via the integrator, which is composed of G4 and capacitorsC41 and C42, which applies a voltage to G3. Stage G3 acts as an offsetcompensating auxiliary stage. This topology works exactly like the onedepicted in figure 3-3, except that the multi-path hybrid-nested Millercompensation is used by applying capacitors C32 and C31. This version is notpreferred, as the auto-zeroed amplifier stage G5 determines the low-frequencynoise, including the folded noise associated with auto-zeroing.

3.3.4 Chopper stabilized amplifiers with ripple filters

A chopper ripple is still present in the output signal of a hybrid-nested Millercompensated chopper offset-stabilized operational amplifier. This chopperripple can be reduced by applying both auto-zeroing and choppingtechniques, as will be shown in the next section.

There are also methods that use a sample and hold, which samples thechopper ripple at the output of the integrator. Two examples will be given inthis section.

In figure 3-12 an implementation of the nested Miller compensatedtopology shown in figure 3-6 is depicted. An extra low-pass filter isimplemented with a switched capacitor notch filter, which is composed of the

+-

+-

V4+ -

C52

I3

G2 G1Vout

C11

C12

Vin

V2

R1

R2 + -

FCFC

G4

++

-+

-

+

-

+

-

+

-

C32

C31

C3 G3+

- +

-

C53

C54

F2F1

F2F1

F2

F1F2

F1

C51

CH1CH2

Cp4

Fig. 3-12 Chopper offset-stabilized operational amplifier with SCnotch filter and synchronous integration and multi-pathhybrid-nested Miller compensation [3.17].


56

switches driven by F1 and F2 and the capacitors C51 and C52 [3.21]. Thisnotch filter also acts as a passive integrator. To compensate for the extra poleintroduced by this integrator, the capacitors C51 and C52 are introduced forthe same reason as the hybrid-nested Miller compensation, as shown in theprevious section. Therefore, in fact it is a hybrid-nested Miller compensatedcircuit. Capacitors C31 and C32 help to maintain local loop stability. Thecapacitor C3 helps to limit the bandwidth of the low-frequency path such thatthe delay caused by the notch filter does not cause instabilities [3.17]. Theadvantage of this topology is that it uses a minimum of gain stages, which canlead to an amplifier that only consumes 17 µA of power [3.22] whileobtaining a 55 nV/√Hz input referred white noise and a GBW of 350 kHz.

To compensate for the offset V2 of G2, a DC voltage has to be presentat the input of G3. This voltage is proportional to the offset V2. A voltage atthe output of chopper CH1 together with a parasitic capacitor at the input ofCH1 would lead to a residual offset. This residual offset due to the parasiticoutput capacitance Cp4 of G4 can be expressed as:

, (3-8)

which means that an optimal residual offset is obtained when G3 > G2. This astrange requirement for an auxiliary input, because any switching noise of thenotch filter would be amplified towards the input by a ratio G3/G2.

Another disadvantage of this topology is that the residual offset due tofinite gain is limited by the voltage gain of the gain stage G4. Since theresidual offset due to finite gain can be expressed as:

, (3-9)

where A2, A3 and A4 are the voltage gains of the respective gain stages G2,G3 and G4. The transconductances G2 and G3 share the same outputimpedance. If G2=G3, this implies that A2=A3. In this case, all offsetcompensation comes down to the DC voltage gain of G4. Despite this, animplementation of this topology has a typical offset of 2 µV, and a maximumoffset of 10 µV [3.22]. This is achieved with A2=A3 and A4=86 dB, and theparasitic capacitor Cp4 being minimized [3.17]. A disadvantage is that anyswitching noise of the notch filter would directly be visible at the input. This

Vos res par, ,4FCCp4

G4------------------

V2G2

G3------------=

Vos res gain, ,A2

A3A4-------------V2≈

57


would generate a ripple since each sample would have an error caused by thekT/C noise of the sampling capacitors.

The topology shown in figure 3-13, has been implemented [3.23] andwill be discussed in section 5.2. In this topology the functions of theintegrator and the notch filter are not combined. The integrator is composedof G5, C51 and C52. The sample-and-hold circuit is composed of the switchesdriven by F1 and F2 and the capacitors CS1 and CS2. Clearly, the benefit ofthis topology is that the residual offset due to finite gain can be expressed as:

. (3-10)

This relaxes the voltage gain specifications of G4. The residual offsetdue to the parasitic output capacitance Cp4 of G4 can be expressed byequation (3-7), which means that in this design the ratio A2/A3 can be chosenlarger than 1 without compromising any residual offset. This also suppressesthe kT/C noise of the sample-and-hold toward the input, achieving betterripple behaviour.

+-

+-

G5

C32

C31

C52

C51

G2 G1Vout

C11

C12

Vin

R1

R2

FCFC

G4+

- +

-

++

-+

-

+

-

+

-

+

-

CS1

CS2

F1F2

F1F2

F1

F2F1

F2

I3

G3+

- +

-

V2+ -

Fig. 3-13 Chopper offset-stabilized operational amplifier with hybrid-nested Miller compensation and a sample-and-hold after anactive integrator G5 [3.23].

Vos res gain, ,A2

A3A4A5-------------------V2≈


58

A possible clock diagram is depicted in figure 3-14. In this diagram thechopper ripple is sampled at half the chopper frequency and with a quarterchopper period delay. With this clock scheme the output range of theintegrator is used optimally.

3.3.5 Chopper and auto-zero stabilized amplifiers

Another possibility which leads to a strongly reduced chopper ripple is toauto-zero the chopper amplifier. This has been shown in the topologydepicted in figure 3-15. During phase F1 the chopper amplifier G4 isauto-zeroed by the integrator composed of G6 and C61 and C62. While inphase F2 the chopper amplifier is in the loop.

This implementation is quite powerful because the auto-zeroing of G4strongly reduces chopper ripple. While the folded noise associated withauto-zeroing is modulated to higher frequencies, as sketched in figure 2-18 insection 2.4, at higher frequencies the high-frequency path dominates thenoise, and effectively filters out most of the noise. This has been sketched infigure 3-16.

An disadvantage however is that when G4 is auto-zeroed it is notconnected to the input signal. When auto-zeroing with a duty cycle of 50%this means that the input signal is only applied for half of the time. Thisdecreases the signal-to-noise power at frequencies below the auto-zerofrequency by a factor two.

chopper clock FC

integrator output

S&H clock FS

output S&Ht

Csh1 Csh1 Csh1Csh2 Csh2 Csh2

Fig. 3-14 Clock diagram of the topology depicted in figure 3-13.

59

Chopper offset-stabilized chopper amplifiers

3.4 Chopper offset-stabilized chopper amplifiers

Until now the offset-stabilizing technique has been discussed. But what if anoffset-stabilized amplifier itself would be chopped? Or in other words, what ifa chopper amplifier would be offset-stabilized? As concluded in section 2.5.1,a dynamic offset compensated differential amplifier with a low offset has a

FCFC

+-

+-

C31

G2 G1Vout

C11

C12

Vin

V2

R1

R2 + -

++

-+

-

+

-

V4+ - G3

V5+ -

C32

C52

C51

I3+

- +

- +

- +

-

G6+

-+

-

G5+

-

+

-G4

F1

F2

F1

F2

t

FC

F2

F1

C62

C61

Fig. 3-15 Chopper and auto-zero offset-stabilizedoperational amplifier.

noisePSDLFP

f(Hz)FC=2FAZ

PSD low frequency path

noisePSDAMP

f(Hz)FC=2FAZ

noisePSDHFP

f(Hz)FC=2FAZ

PSD high frequency path PSD total amp

Fig. 3-16 General output PSD of a chopped and auto-zeroedoffset-stabilized operational amplifier.


60

lower charge injection problem, than that of an amplifier with higher offset.As a result, a chopper amplifier itself would benefit from a stabilized offset.

In figure 3-17 a chopper amplifier consisting of chopper CH2,amplifier stage G2, chopper CH1, and output stage G1 is shown. The offset ischopper offset-stabilized by chopper CH4, stabilize stage G5, chopper CH3,an integrator around G4, and an auxiliary input stage G3.

The choppers CH2 and CH4 can be combined by placing the inputs ofG5 at the input of the amplifier. In section 2.3.2 it was shown that themodulated offset appears at the inputs of a chopper amplifier. Therefore, it isnot necessary to create a modulated offset two times with CH2 and CH4. The

-

+-

+V4+ -

C32

C31

C42

C41

I3

+

-G2+

-+G1

+

-

Vout

C11

C12

Vin

V2

R1

R2 + -

FCFC FC

+

-G5+

-

V5-

+

-G3+

-

FC

CH2 CH1

CH4 CH3

G4+

-+

-

+

Fig. 3-17 Chopper offset-stabilized chopper amplifier.

+-

+-

G4+

-+

-

+V4+ -

C32

C31

C42

C41 I3

+

-G2+

-+G1

+

-

Vout

C11

C12

Vin

V2

R1

R2 + -

FC

FC FC

+

-G5+

-

V5-

+

-G3+

-

CH2 CH1

CH3

+-Va

Fig. 3-18 Chopper offset-stabilized chopper amplifier with a combinedchopper CH2.

61

Chopper offset-stabilized chopper amplifiers

resulting amplifier is shown in figure 3-18 [3.24]. This benefits the residualoffset due to charge injection, because the amount of switches is reduced.

The frequency behaviour is more difficult to explain than the behaviourof the offset-stabilized amplifier. Amplifier stage G5 senses the voltage Va at itsinput. This contains the modulated offset V2 of G2. The voltage Va is convertedinto a current by G5. This current is modulated by CH3. The modulated currentnow contains DC current information of the offset V2. Integrating this currentinto the integrator composed of G4, C41, and C42 leads to an offset reducingcurrent I3. However, for the input signal the combination of choppers CH3 andCH1 and the integrator G4 acts as a bandpass filter around the chopperfrequency. This means that the low-frequency behaviour is determined by G2instead of G5.

The hybrid-nested Miller frequency compensation capacitors are stillnecessary to ensure that the roll-off remains 20 dB per decade around theclock frequency. The capacitors need to be placed at the left of CH3 toprovide negative feedback for the compensation capacitors.

This topology modulates the residual offset of the chopper stabilizedoperational amplifier depicted in figure 3-7, which would lead to a betteroffset specification. However, there are choppers introduced into the mainsignal path, and the complexity is increased.

However, the chopper ripple caused by the modulated offset of G5remains. Only its shape changes from a triangular wave into a saw-toothwave, i.e. a chopped triangular wave. This ripple can again be suppressed byauto-zeroing the input stage or placing a sample-an-hold behind theintegrator. A quest to obtain a low offset and low ripple resulted in theamplifier topology discussed in the next sub-section.

3.4.1 Iterative offset-stabilization

All the techniques discussed so far can be applied to operational amplifiers.Numerous combinations can be made with chopper, auto-zero andoffset-stabilized amplifiers. In figure 3-19 a three-stage chopper amplifier isshown that consists of output stage G1, intermediate stage G2, and choppedinput stage G3.

The input stage is both chopper and auto-zero offset-stabilized. Thetransconductance stage G5, and the integrator around G4 offset-stabilized G3,while the integrator around G6 is used to auto-zero G5. The offset ofintegrator G4 limits the ripple reduction by crosstalk through Cp5 to the


62

output. To circumvent this around G4 a nested chopper offset-stabilizationloop is added consisting of transconductance G8, and an integrator around G7.The integrator around G6 is also chopper stabilized by transconductance G10,and an integrator around G9. The intermediate stage G2 is also chopper andauto-zero offset-stabilized by transconductance stage G12, the integratoraround G11, while the integrator around G13 is used to auto-zero G12 [3.24].

FM

+-

+-

G4

C42

C41

G3 G1Vout

Vin

R1

R2

FC

FC FC

G5

G2

C72

C71

FC

G8

G6

C62

C61

G10

C91

FC

C92FC

G11

C112

C111

FC

G12

G13

C132

C131

G7 =

=

FCFC

FM

FM

Cp5

G9

Fig. 3-19 Chopper amplifier with iterative offset-stabilization [3.24].

63

Conclusions

The resulting amplifier has 13 stages, or 19 it the necessary 6 auxiliarystages are counted. A clear disadvantage is the complexity of the topology.This topology has potentially a very low offset, since every source of offsethas been offset-stabilized.

3.5 ConclusionsIn this chapter several topologies have been discussed that can be used to obtainbroadband dynamic offset compensated operational amplifiers. In table 3-1 theproperties of the different topologies are summarized. The first topology is theping-pong topology, where one amplifier is auto-zeroed while another amplifieris used to amplify a signal. It doesn’t display a chopper ripple, although it doesdisplay switching spikes due to the switches in the signal path. Its residual offsetis limited by the gain of the amplifier. The auto-zeroed offset-stabilizedtopology (AZOS), is less complex than the ping-pong topology, although thelow-frequency (LF) noise increases by a factor √2. The chopperoffset-stabilized (CHOS) topology has a superior LF noise, although itexhibits a chopper ripple. Two techniques were discussed to reduce this rippleat the cost of complexity: chopper offset-stabilization with ripple filters with asample-and-hold (CHOS+S&H), and chopper and auto-zero offset-stabilized(CH&AZOS) operational amplifiers. A way to obtain a lower residual offset

Table 3-1. Comparison of the different broadband dynamic offset compensated topologies.

Topology Ripple LF noise

Residualoffset

Complex-ity

Ping-pong + - +/- -AZOS ++ -- +/- +CHOS -- ++ + +

CHOS+S&H + ++ + +/-CH&AZOS + + + +/-CHOSCH -- ++ ++ -

Iter + ++ +++ --


64

is to use a chopper offset-stabilized chopper topology (CHOSCH). In thistopology the residual offset of a chopper offset-stabilized amplifier is chopped,reducing the offset further. However, the topology complexity increases and thechopper switches in the signal path exhibit switching spikes. Finally theiterative (ITER) topology could lead to a very low residual offset at the cost ofan increased topology complexity.

Of these topologies, the chopper offset-stabilized (CHOS) operationalamplifier offers the best option for obtaining a low-noise amplifier with areasonable topology complexity. However, chopper ripple remains a problem.Therefore, chopper offset-stabilization with ripple filters, and chopper andauto-zero offset-stabilized topologies will be used in the implementationsdiscussed in chapters 5 and 6.

3.6 References[3.1] F. Krummenacher, R. Vafadar, A. Ganesan, V. Valence, “A

high-performance autozeroed CMOS opamp with 50µVoffset”, IEEE ISSCC, pp. 350–351, Feb. 1997.

[3.2] Texas Instruments, “Family of self-calibrating (self-cal)precision CMOS rail-to-rail output op amps (rev. B)”,Datasheet TLC4501, www.ti.com, Apr. 2001.

[3.3] C.G. Yu, R.L. Geiger, “An automatic offset compensationscheme with ping-pong control for CMOS operationalamplifiers”, IEEE JSSC, pp. 601–610, May 1994.

[3.4] I.E. Opris, G.T.A.A. Kovacs, “Rail-to-rail ping-pong op-amp”,IEEE JSSC, pp. 1320–1324, Sep. 1996.

[3.5] M. Kayal, R.T.L Saez, M. Declercq, “An automatic offsetcompensation technique applicable to existing operationalamplifier core cell”, CICC, pp. 419–422, May 1998.

[3.6] A.T.K. Tang, “A 3µV-offset operational amplifier with input noise PSD at DC employing both chopping

and autozeroing”, IEEE ISSCC, pp. 386–387, Feb. 2002.[3.7] Analog devices, “Zero-drift, single supply, rail-to-rail, input/

output operational amplifier, AD8628/8629/8630”, DatasheetRef F, http://www.analog.com, Feb. 2008.

20nV Hz⁄

65

References

[3.8] Texas Instruments, “0.05uV/C max, single-supply CMOS opamps zero-drift”, Datasheet, Rev. D, OPA335, www.ti.com,June 12, 2003.

[3.9] Thomas Kugelstadt, “Auto-zero amplifiers ease the design ofhigh-precision circuits”, Texas Instruments, focus.ti.com/lit/an/slyt204/slyt204.pdf, 2005.

[3.10] C. C. Enz, G. C. Temes, “Circuit techniques for reducing theeffects of op-amp imperfections: autozeroing, correlateddouble sampling, and chopper stabilization”, Proc. IEEE, pp.1584–1614, Nov. 1996.

[3.11] I.G. Finvers, J.W. Haslett, F.N. Trofimenkoff, “Noise analysisof a continuous-time auto-zeroed amplifier”, IEEE Trans. onCircuits and Systems II, pp. 791–800, Dec. 1996.

[3.12] Intersil, “2MHz, super chopper-stabilized operationalamplifier”, FN2920.10, Datasheet ICL7650S, http://www.intersil.com, Apr. 2007.

[3.13] M.C.W. Coln, “Chopper stabilization of MOS operationalamplifiers using feed-forward techniques”, IEEE JSSC, pp.745–748, Dec. 1981.

[3.14] Analog devices, “Zero-drift, single-supply, rail-to-rail input/output operational amplifier, AD8551/8552/8554”, datasheet,Ref C, http://www.analog.com, Mar. 2007.

[3.15] I.G. Finvers, J.W. Haslett, F.N. Trofimenkoff, “A hightemperature precision amplifier”, IEEE JSSC, pp. 120–128,Feb. 1995.

[3.16] C.I. Menolfi, “Low Noise CMOS Chopper InstrumentationAmplifiers for Thermoelectric Microsensors”, 1st ed.Konstanz, Germany: Hartung-Gorre Verlag, chapter 5, 2000.

[3.17] R. Burt, J.A. Zhang, “Micropower chopper-stabilizedoperational amplifier using a SC notch filter with synchronousintegration inside the continuous-time signal path”, IEEEJSSC, pp. 2729–2736, Dec. 2006.

[3.18] R.G.H. Eschauzier, L.P.T. Kerklaan, J.H. Huijsing, “A100MHz 100-dB operational amplifier with multipath nestedMiller compensation structure”, IEEE JSSC, pp. 1709–1717,Dec. 1992.


66

[3.19] R.G.H. Eschauzier, R. Hogervorst, J.H. Huijsing, “Aprogrammable 1.5V CMOS class-AB operational amplifierwith hybrid nested Miller compensation for 120dB gain and6MHz UGF”, IEEE JSSC, pp. 1497–1504, Dec. 1994.

[3.20] J.H. Huijsing, M.J. Fonderie, B. Shahi, “Frequencystabilization of chopper-stabilized amplifiers”, US patent Nr.7,209,000, Apr. 24, 2007.

[3.21] A. Bakker, J.H. Huijsing, “A CMOS chopper opamp withintegrated low-pass filter”, Proc. ESSCIRC, pp. 200–203, Sep.1997.

[3.22] Texas Instruments, “1.8V, micropower CMOS operationalamplifiers zero-drift series”, Datasheet OPA333, Rev. C, May1, 2007.

[3.23] J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, “A CMOS chopperoffset-stabilized opamp”, IEEE JSSC, pp. 1529–1535, July2007.

[3.24] J.H. Huijsing, M.J. Fonderie, “Chopper chopper-stabilizedoperational amplifiers and methods”, US patent Nr. 6,734,723,Nov. 7, 2004.

4

67

Dynamic Offset Compensated Instrumentation Amplifiers 4

4.1 IntroductionIn many sensor systems there is a need to amplify a weak differential signal,which is often accompanied by a strong common-mode signal. Amplifiersdesigned to handle such tasks are known as instrumentation amplifiers. Thereare three general approaches to design instrumentation amplifiers.

The first approach involves the use of operational amplifiers andresistive feedback. The simplest example is the differential amplifier shownin figure 4-1a. This amplifier suffers from unequal and low input impedances.Thus its gain is dependent on the source impedances. To solve this problem,the famous three operational amplifiers instrumentation amplifier has beendeveloped, as shown in figure 4-1b [4.1]. In this topology, two operationalamplifiers are used to implement a fully differential buffer that precedes adifferential amplifier. This topology has a much higher input impedance butstill suffers from a not very high common-mode rejection ratio (CMRR) dueto resistor mismatch. Therefore, commercially available instrumentationamplifiers are often designed with the help of laser trimmed resistors. Toobtain low-offset in a resistive feedback instrumentation amplifier, theoperational amplifiers which are used in the implementation can be designedwith dynamic offset compensation techniques, as discussed before.

Dynamic Offset Compensated Instrumentation Amplifiers

68

The second approach involves using a flying or switched capacitortopology to overcome the large common-mode voltage [4.2] [4.3] [4.4]. Asimplified version of a switched capacitor differential amplifier is shown infigure 4-2. To obtain low offset for switched capacitor circuits, the auto-zeromethods can be used because the switches and capacitors are already presentin the implementation.

Current-feedback instrumentation amplifiers offer another option, inwhich the CMRR is determined by isolation and balancing techniques. This isthe subject of the next section.

(a)

R3

R1

Vin+

-A1+-

(b)

R2

R3

R1

A1+-

R2A2+-

A3+-

R5Vin+

-

R4R4

VoutVout

VrefVref

Fig. 4-1 (a) Differential amplifier and (b) resistive feedbackinstrumentation amplifier.

C3

C1

Vin+

-

C2

C4

A1+-

Vout+

-

F1

F2

F1

F1

F1

F1

F1

F2

F2

Fig. 4-2 Switched capacitor instrumentation amplifier.

69

Introduction

4.1.1 Current-feedback instrumentation amplifiers

Since the 1970s, various instrumentation amplifier topologies have beendeveloped for current-feedback or current balancing instrumentation amplifiers.For historical reasons, these topologies are shown implemented with bipolartransistors in this section.

The first monolithic current-feedback instrumentation amplifier [4.5]used the topology shown in figure 4-3. It uses two voltage amplifiers A1 andA2 and two transconductance amplifiers, namely an input transconductanceimplemented with transistors Q1 and Q2 and resistor R1, and a feedbacktransconductance implemented with Q3, Q4 and R2.

This circuit works as follows. The input transconductance is unbalancedby the input voltage Vin, which causes the current through current sources I1 andI2 to be unequal. Voltage amplifier A1 drives the output voltage Vout andconsequently the feedback voltage Vfb. The feedback transconductance isunbalanced by this feedback voltage, which causes the current through currentsources I3 and I4 not to be equal. Loop amplifier A2 drives the two currentmirror pairs I1, I4 and I2, I3 to be equal. The loop amplifiers A1 and A2 help tomaintain constant currents through I5, I6 and I7, I8, respectively. By keeping the

Q1 Q2R1

A1

I1

R3

R4

Vin

Vref

Vout

VDD

Vgnd

+

-

-+

Q3 Q4

R2Vfb

+

-

A2-+

+-

I2 I3I4

I5 I6 I7 I8

Fig. 4-3 Current-feedback instrumentation amplifier with twofeedback amplifiers.


70

collector currents of Q1,2 and Q3,4 equal, their base-emitter voltages are equal.As a result the voltages over R1 and R2 accurately represent Vin and Vfb. Thus,the next equations hold:

, (4-1)

, (4-2)

and , (4-3)

Thus and . (4-4)

The settling time of this topology was rather poor, because during anoverload condition, the whole amplifier needs to settle [4.6]. The feedback loopincludes the input transconductance, voltage amplifier A1, the feedbacktransconductance and the voltage amplifier A2. The use of multiple feedbackloops also leads to stability issues. The two topologies discussed next overcomethese issues, by using only one feedback loop.

Indirect current-feedback instrumentation amplifierThe indirect current-feedback topology is shown in figure 4-4 [4.5]. It wasfirst used [4.7] to implement a method for frequency compensation and later[4.8] to implement an instrumentation amplifier. The idea is that I1 to I4 areequal, and that I5 and I6 are equal. The loop amplifier A1 then forces thedifferential collector current from Q1 and Q2 into Q3 and Q4, by driving therequired voltage Vfb at the inputs of Q3 and Q4.

Another way of looking at this circuit is that the feedback transconductanceamplifier, implemented with Q3, Q4 and R2, together with the loop amplifier A1,form a two-stage operational amplifier. For this circuit the frequency compensationis well-known [4.9]. A replica transconductance amplifier implemented with Q1, Q2and R1 is added to this operational amplifier and is used as a new input stage toimplement the indirect current-feedback.

A disadvantage of this however, is that the collector currents of Q1 andQ2 and of Q3 and Q4 are not a linear function of Vin and Vfb, respectively.

I1 I2– 2Vin R1⁄=

I4 I3– 2Vfb R2⁄=

I1 I4= I2 I3=

Vfb

Vin-------

R1

R2------=

Vout

Vin---------

R1

R2------

R3 R4+

R4----------------=

71

Introduction

These non-linearities are cancelled in first order when the transistors matchand [4.10]. Equation (4-4) then becomes:

(4-5)

The input stages can also be linearized by using gain-boostedtransistors [4.8]. In CMOS design, where mismatch is a bigger problem, theuse of composite transistors might be necessary to obtain a better gainaccuracy and linearity [4.11].

Direct current-feedback instrumentation amplifierFor biomedical applications, which demand low power, another topology wasinvestigated [4.12]. This topology is shown in figure 4-5. In this topology theinput and feedback transconductance amplifiers are cascoded. This way thesupply current is reduced. This topology was later used in CMOSimplementations [4.13] [4.14]. A disadvantage of this topology in comparisonwith the indirect current-feedback approach is the increase in minimumsupply voltage and decrease in the common-mode voltage range. Another

Q1 Q2

R1

A1

R3

R4

Vin

Vref

Vout

VDD

Vgnd

+

-

+-

Q3 Q4R2

Vfb

+

-

I6I5

I2I1 I4I3

Fig. 4-4 Indirect current-feedback.

R1 R2=

Vout

Vin---------

R3 R4+

R4----------------=


72

disadvantage is that Q1 and Q2 always carry the same current, whereas Q3 andQ4 carry a signal dependent current. This can be a cause of non-linearity.

A distinction can be made between direct and indirect current-feedbackinstrumentation amplifiers [4.10], where the input and feedback transconductancesare cascoded and cascaded respectively. The direct current-feedback is better forlow-power applications, while the indirect current-feedback approach is better forgain accuracy and for low-voltage applications, where the relatively highercommon-mode input voltage range is also beneficial. The implementationspresented in chapter 6 focus on wide-bandwidth offset-stabilized indirectcurrent-feedback instrumentation amplifiers.

The indirect current-feedback instrumentation amplifier can be seen asan operational amplifier with a replica input pair. In figure 4-6 an example isgiven of a two-stage Miller compensated operational amplifier that consists ofstages G1 and G2 with an additional replica input stage G3 to implement acurrent-feedback instrumentation amplifier.

The gain accuracy of the instrumentation amplifier depends on theequality of G2 and G3. With ordinary differential pairs of the same type

Q3 Q4R2

Q1 Q2R1

A1

R3

R4

Vin

Vref

Vout

VDD

Vgnd

+

-

+-

Vfb

+

-

I4I3

I2I1

Fig. 4-5 Direct current-feedback instrumentationamplifier.

73

Introduction

working in weak inversion, and well matched tail currents, a 1% gainaccuracy can be obtained. The gain can be expressed as:

. (4-6)

A strange feature with respect to operational amplifier design is thatthe input stages have to be able to handle a finite input voltage, since thevirtual ground concept is not applicable. However, the differential input rangeof ordinary differential pairs is effectively limited to about 50 mV, becausethe differential pairs will saturate. This input range can be improved withdegeneration resistors. An implementation of an accurate transconductanceamplifier is presented in section 6.3.3.

For this reason the input stages of the designs shown in figures 4-3 to4-5 are all shown with degeneration resistors. Another odd feature is that thepolarity of G3 does not have an effect on the stability of the circuit, since G3 isnot part of the feedback network.

In figure 4-7 a multi-path current-feedback instrumentation amplifieris depicted. What is interesting is that in a multi-path current-feedbackinstrumentation amplifier the polarity of the input replica stages G4 and G6can be chosen arbitrarily. For instance a positive gain for the low-frequencypath and a negative gain for the high-frequency path. An amplifier like thiscan be used as an all-pass filter, since it has a phase shift of 180º between low

Vout Vref–

Vin---------------------

R1 R2+

R2----------------

G2

G3------=

+-

G2 G1Vout

C11

C12

Vref

R1

R2 ++

-+

-

+

-

G3 I3+

- +

-

+-

Vin

+-

Vfb+-

I2

Fig. 4-6 Two-stage operational amplifier with an additionalfeed-forward input stage to implement a current-feedbackinstrumentation amplifier.


74

and high frequencies. However, generally this is unwanted behaviour whichcan surprise a designer.

The CMRR of this instrumentation amplifier is now dependent on theCMRR of the input stages which can be designed to be very high. Apart fromthe dependency of the offset on CM voltage, there is also common-modevoltage dependency of the voltage gain, because, the transconductances of theinput stages have a common-mode voltage dependency. The offset of such anamplifier is equal to the sum of the input offset voltages of the input stage andthe replica stage, this is 2–20 mV for typical CMOS implementations. Thegain accuracy is limited by the matching of the input and replicatransconductance which leads typically to a 1% gain accuracy.

4.2 Dynamic offset compensated instrumentation amplifiers

In this section some topologies of dynamic offset compensated current-feedbackinstrumentation amplifiers are presented. In section 4.2.1 the chopping andauto-zero techniques discussed in chapter 2 will be extended to the discussion ofcurrent-feedback instrumentation amplifiers. From section 4.2.3 onwards thefocus will be on broadband dynamic offset compensated instrumentation

I3

I2

I7

I6

G3

C31

C32

G2

C21

C22

+

-

+

-

+

-

+

-G4

G5+

-

G6

G7

+-

Vin+

Vfb

-

+

-

+

-

+-

G1 Vout

C11

C12

++

-

Vfb

+-Vref

+

-

Fig. 4-7 Four-stage multi-path current-feedback instrumentation amplifier.

75

Dynamic offset compensated instrumentation amplifiers

amplifiers. The ping-pong amplifier discussed in section 3.2 will be extended to adiscussion on ping-pong-pang amplifiers in section 4.2.3. The offset-stabilizedoperational amplifiers discussed in section 3.3 will be extended in section 4.2.5.The chopper offset-stabilized chopper amplifiers discussed in section 3.4 will beextended in section 4.2.6.

4.2.1 Chopper instrumentation amplifier

A chopper current-feedback instrumentation amplifier topology is shown infigure 4-8. Generally it can be assumed that the offset is two times worse thanfor a chopper operational amplifier, because the replica input stage also hasoffset and an additional chopper is also needed. The CMRR of such anamplifier is very high for signal frequencies below the chopping frequency.

As shown in section 2.5.2 the charge injection is a function of the inputsignal. This means that charge injection varies slightly over the input voltagerange. This is a cause of gain non-linearity. For an input range of 50 mV and adecent chopper layout with minimum size switches, the non-linearity causedby this effect can be in the order of 0.1%, which is in the same order as that ofthe non linearity of V-to-I convertors.

The gain accuracy of the instrumentation amplifier caused by amismatch of G2 and G3 can also be reduced by dynamic matching of the inputstages. If there is a mismatch of ∆ between G2 and G3, the gain error wouldthen average over time as can be expressed by:

, (4-7)

+-

G1 Vout

C11

++

-

Vfb+-Vref

+-

+

-G2+

-Vin

+-Vfb

+

-G3-

+

FCFC

FC

C12

R2

R1

Fig. 4-8 Indirect current-feedback chopperinstrumentation amplifier.

εgain mismatch,1 ∆+

2----------- 1

2 2∆+--------------+

1– 2 2∆ ∆2+ +2 2∆+

------------------------ 1 ∆2

2-----≈–= =


76

which would mean that a 1% mismatch would only cause a 0.005% gainerror. This dynamic element matching would be relatively easy to implement,because both switches and the logic to drive them are already present.However, the inputs have to switch from the input common-mode to thereference common-mode. When those common-modes differ too much, thiscould cause nasty spikes, which means that the dynamic matching of the inputstages cannot be applied to general purpose instrumentation amplifiers.

4.2.2 Auto-zeroed instrumentation amplifier

An auto-zeroed current-feedback instrumentation amplifier topology isshown in figure 4-9. In this figure the auto-zeroing with an auxiliary inputstage G4 is used. In phase F1 the offset voltages V2 and V3 cause a currentIoffset=V3G3–V2G2. This current is integrated by the integrator around G5until I4=Ioffset. Thus, after a few auto-zero cycles the offsets V2 and V3 will becompensated for by an offset compensating current I4. During phase F2 theamplifier amplifies the input signal.

An auto-zeroed current-feedback instrumentation amplifier with inputoffset storage is shown in figure 4-10. In phase F1 the offsets V2 and V3 arestored on capacitors CA1 to CA4. With respect to the topology shown infigure 4-9, this amplifier will probably have a higher residual offset due to thecharge injection of the input switches.

However, a beneficial attribute of this amplifier is that the inputcommon-mode voltage is separated from the inputs of the instrumentationamplifier, such as in a switched capacitor amplifier. This means that the inputs

+-

G1 Vout

C11

C12

++

-

Vfb

+-Vref

+-

+

-G2+

-

Vin

V2+ -

+-Vfb

V3+ -

G5

C52

C51

G4

+

-G3+

-

+

-+

-

F2

F1

F2

F1

F1

+

-

+

-

I4

I2

I3

Fig. 4-9 Auxiliary input auto-zeroed current-feedbackinstrumentation amplifier.

77


do not have to be designed to accommodate the common-mode. The dynamicelement matching, as discussed before, might be easier to implement. Theswitches in front of the capacitors CA1 to CA2, have to accommodate the inputcommon-mode voltage. Consequently, this topology can be seen as a hybridof the switched capacitor amplifier and the current-feedback instrumentationamplifier.

A disadvantage of this is, however, that the parasitic input capacitancesCp2 and Cp3 of transconductances G2 and G3 act as a voltage divider, and alterthe overall gain. Effort has to be taken into matching those parasitics.

+-

G1 Vout

C11

C12

++

-

Vfb

+-Vref

+-

Vin

V2+ -

+-Vfb

V3+ -

CA1

CA2

CA3

CA4

F1

F1

F1

F2F2

Cp2

Cp3

+

-

G2+

-

+

-

G3+

-

Fig. 4-10 Input offset storage auto-zeroedcurrent-feedback instrumentation amplifier.

+-

G1 Vout

C11

C12

++

-

Vfb

+-Vref

+-

+

-G2b+

-

Vin

V2+ -

+-Vfb

V3+ -

G5b

C54

C53

G4b

+

-G3b+

-

+

-+

-

F1

F2

F1

F2

F2

+

-

+

-

+-

+

-G2a+

-

Vin

V2+ -

+-Vfb

V3+ -

G5a

C52

C51

G4a

+

-G3a+

-

+

-+

-

F2

F1

F2

F1

F1

+

-

+

-

I4

I2

I3

Fig. 4-11 Ping-pong auto-zero instrumentation amplifier [4.15].


78

4.2.3 Ping-pong instrumentation amplifier

A wide-band instrumentation amplifier can be obtained with the ping-pongtechnique as described in section 3.2. The auto-zeroed amplifier as depictedin figure 4-9 can be used, by duplicating G2, G3, G4 and G5 and using theauto-zero switches as multiplexer between the two obtained input stages. Aninstrumentation amplifier like this is depicted in figure 4-11. A choppedping-pong instrumentation amplifier has been used in an implementation[4.15] obtaining a 3 µV offset voltage and 140 dB CMRR.

4.2.4 Ping-pong-pang instrumentation amplifier

As was explained earlier, the current-feedback instrumentation amplifieris an operational amplifier with a replica input stage. Therefore, it can also beimplemented as a ping-pong amplifier with a replica input stage. Thisping-pong-pang amplifier [4.16] is presented in figure 4-12.

There are numerous algorithms that can be implemented. One exampleis given in figure 4-13. In this algorithm two input stages are swapped duringeach cycle, while each input stage is auto-zeroed with a 1/3 duty cycle at anauto-zero frequency.

C22

C21

G2

+-

C32

C31

G3

+

-

C42

C41

Vrefin G4

+-

+-

Vout

C11

C12

++

-

Vfb+-Vref

Vin+

-

Vfb+

-

G1

Fig. 4-12 Ping-pong-pang auto-zero instrumentation amplifier [4.16].

79


This ping-pong-pang amplifier can also be chopped to reduce theresidual offset, as was also done in the ping-pong amplifier [4.17]. When analgorithm is used where the auto-zero duty cycle is 1/3, then the chopperfrequency should be chosen one-and-a-half or three times higher than theauto-zero frequency, in order to modulate the folded auto-zero noise to higherfrequencies and achieve an optimal low frequency noise.

4.2.5 Offset-stabilized instrumentation amplifiers

A chopper offset-stabilized current-feedback instrumentation amplifier ispresented in figure 4-14. Just as in the chopper offset-stabilized operationalamplifier, the cascaded amplifier stages G1, G4, G5 and G6/G7 can be seen asa low-frequency path. At DC until frequencies where the low-frequency pathis dominant, the ratio of G6/G7 determines the gain. The chopped input offset

Vin

Vfb

Vrefin AZ

G2

G3

G4

1

G2

G3

G4

2 3 4

G2

G3

G4

G2

G3

G4 G2

G3

G4

G2

G3

G4

G2

G3

G4

5 6 1Phaseinput

Fig. 4-13 Possible ping-pong-pang algorithm with dynamic matching.

+-

G5+

-

+

-+

-

G4+

-

V5+ -

C32

C31

C52

C51

I3

+G1+

-

Vout

C11

C12V3

R1

R2+ -

Vfb

Vref+-

+

-

G2

V2+ -

FC

+-

Vfb

+-

Vin

+

-

G6+

-

+

-

+

+

-

G7+

-

FC

-

G3+

-

Fig. 4-14 Chopper offset-stabilized current-feedback instrumentationamplifier.


80

voltages of G6 and G7 cause a chopper ripple which can be seen as atriangular wave.

An auto-zero offset-stabilized current-feedback instrumentation amplifieris presented in figure 4-15. It does not suffer from the chopper ripple. Howeverthis amplifier has inferior low-frequency noise due to the noise folding associatedwith auto-zeroing.

The chopper and auto-zero offset-stabilized instrumentation amplifierpresented in figure 4-16 has an improved noise performance with respect tothe topology of figure 4-15. It doesn’t suffer from the triangular chopperripple because G6 and G7 have been auto-zeroed. It is also likely that by usingtwo offset compensation techniques, the residual offset will be lower.Examples of implementations of this topology can be found in chapter 6.

+-

G5+

-

+

-+

-

G4+

-

V5+ -

C42

C41

C52

C51

I3

+G1+

-

Vout

C11

C12V3

R1

R2+ -

Vfb

Vref+

-

+

-

G2+

-

V2+ -

+-

Vfb

+-

Vin

+

-

G3+

-

V6+ -

V7+ -

CA1

CA2

CA3

CA4

F1

F1

F1

F2F2

Cp6

Cp7+

-

G7+

-

+

-

G6+

-

Fig. 4-15 Auto-zero offset-stabilized current-feedback instrumentationamplifier.

81


+-

G5+

-

+

-+

-

G4+

-

V5+ -

C42

C41

C52

C51

I3

+G1+

-

Vout

C11

C12V3

R1

R2+ -

Vfb

Vref+-

+

-

G2+

-

V2+ -

FC FC

+-

Vfb

+-

Vin

+

-

G3+

-

V6+ -

V7+ -

+

-

G6+

-

CA1

CA2

+

-

G7+

-

CA3

CA4

F1

F1

F1

F2F2

Cp6

Cp7

Fig. 4-16 Chopper and auto-zero offset-stabilized current-feedbackinstrumentation amplifier.

+-

+

-

G6 G5+

-

+

-+

-

G4+

-

V5+ -

C42

C41

C52

C51

I4

+

-

G3

+G1+

-

Vout

C11

C12V3

R1

R2+ -

Vfb

Vref+-

+

-

G2+

-

V2+ -

+

-

G7+

-

FC

FC

FC+-

Vfb

+-

Vin

+

-

+

-

Fig. 4-17 Chopper offset-stabilized chopper current-feedbackinstrumentation amplifier.


82

4.2.6 Chopper offset-stabilized chopper instrumentation amplifier

A chopper offset-stabilized chopper current-feedback instrumentation amplifieris presented in figure 4-17. Since the chopped integrator acts as a band-passfilter for the input signal G6 and G7 are effectively AC coupled, therefore, thelow frequency gain is determined by G2 and G3.This topology has also beenextended to an iterative offset-stabilized instrumentation amplifier [4.18]. Aninstrumentation amplifier like this has the potential of achieving a very lowoffset, since every source of offset has been offset-stabilized. However itrequires 24 gain stages.

4.3 ConclusionsIn this chapter the topologies of operational amplifiers discussed in the previouschapter have been extended to include current-feedback instrumentation amplifiers.Of these topologies, the chopper offset-stabilized instrumentation amplifier offersthe best option for obtaining a low-noise instrumentation amplifier.

4.4 References[4.1] P. Horowitz, W. Hill, “The arts of electronics”, Cambridge

university press, 1989.[4.2] R.C. Yen, P.R. Gray, “A MOS switched-capacitor instrumentation

amplifier”, IEEE JSSC, pp. 1008–1013, Dec. 1982.[4.3] P.M. van Peteghem, I. Verbauwhede, W.M.C. Sansen,

“Micropower high-performance SC building block for integratedlow-level signal processing”, IEEE JSSC, pp. 837–844, Aug. 1985.

[4.4] K. Martin, L. Ozcolak, Y.S. Lee, G.C. Temes, “A differentialswitched-capacitor amplifier”, IEEE JSSC, pp. 104–106, Feb. 1987.

[4.5] H. Krabbe, “A high-performance monolithic instrumentationamplifier”, IEEE ISSCC, pp. 186–187, Feb. 1971.

[4.6] A.P. Brokaw, M.P. Timko, “An improved monolithicinstrumentation amplifier”, IEEE JSSC, pp. 417–423, Dec. 1975.

83

References

[4.7] R.J. van de Plassche, “A wide-band operational amplifier witha new output stage and a simple frequency compensation”,IEEE JSSC, pp. 347–352, Dec. 1971.

[4.8] R.J. van de Plassche, “A wide-band monolithic instrumentationamplifier”, IEEE JSSC, pp. 424–431, Dec. 1975.

[4.9] J.H. Huijsing, “Operational amplifiers theory and design”,Dordrecht: Kluwer, 2001.

[4.10] B.J. van den Dool, J.H. Huijsing, “Indirect current feedbackinstrumentation amplifier with a common-mode input rangethat includes the negative rail”, IEEE JSSC, pp. 743–749, July1993.

[4.11] J.H. Huijsing, B.Shahi, “Accurate voltage-to-current convertersfor rail-sensing current-feedback instrumentation amplifiers”,US patent Nr. 7,202,738, Apr. 10, 2007.

[4.12] G.H. Hamstra, A. Peper, C.A. Grimbergen, “Low-powerlow-noise instrumentation amplifier for physiological signals”,Medical & Biological Eng. & Comput., pp. 272–274, May1984.

[4.13] M.S.J. Steyaert, W.M.C. Sansen, “A micropower low-noisemonolithic instrumentation amplifier for medical purposes,”IEEE JSSC, pp. 1163–1168, Dec. 1987.

[4.14] R.F. Yazicioglu, P. Merken, R. Puers, C. Van Hoof, “A 60µW60nV/√Hz readout front-end for portable biopotential acquisitionsystems”, IEEE JSSC, pp. 1100–1110, May 2007.

[4.15] M.A.P. Pertijs, W.J. Kindt, “A 140dB-CMRR current-feedbackinstrumentation amplifier employing ping-pong auto-zeroingand chopping”, IEEE ISSCC, pp. 324–325, Feb. 2009.

[4.16] J.H. Huijsing, “Instrumentation amplifiers developments”,AACD workshop, Pavia, Apr. 2008.


84

[4.17] A.T.K. Tang, “A 3 µV-offset operational amplifier with 20nV/√Hz input noise PSD at DC employing both chopping andautozeroing”, IEEE ISSCC, pp. 386–387, Feb. 2002.

[4.18] J.H. Huijsing, B.Shahi, “Chopper chopper-stabilizedinstrumentation and operational amplifiers”, US patent Nr.7,132,883, Nov. 7, 2006.

5

85

Realizations of Operational Amplifiers 5

5.1 IntroductionIn the previous chapters, the theory necessary for designing low-offset CMOSoperational amplifiers has been discussed. This chapter focuses on the designof two complete general-purpose low-offset wide-bandwidth operationalamplifiers, which have been designed using this theory. Chapter 6 will focuson the realization of instrumentation amplifiers.

In section 5.2 a chopper offset-stabilized operational amplifier will bedescribed. In this implementation, a sample-and-hold is used to reducechopper ripple, as discussed in section 3.3.4. In section 5.3, a chopper andauto-zero offset-stabilized operational amplifier will be described. Bothamplifiers are designed to be unity-gain stable with a 100 pF load capacitorand achieve a unity-gain frequency of 1MHz with a 60-degree phase margin.

Realizations of Operational Amplifiers

86

5.2 Chopper offset-stabilized operational amplifier

The first implementation that will be discussed in this book is a chopperoffset-stabilized operational amplifier. It has been designed as a feasibilitystudy, to investigate the performance of a chopper-stabilization topology, asdiscussed in chapter 3. This amplifier was designed around the same time asthe work of Burt and Zhang [5.1], who independently designed a product[5.2] with a very similar topology, which was discussed in section 3.3.4. Thestarting point of this design was the operational amplifier described insection 3.4 [5.3].

First the chosen topology will be presented. In section 5.2.2, thetransistor level implementations of the stages used in this design aredescribed. In section 5.2.3, the measurement results are shown. Conclusionswill be presented in the final section.

5.2.1 Topology

The foundation of this amplifier is a three-stage amplifier consisting of G1,G2 and G3. The topology used in the implemented circuit is shown infigure 5-1. It consists of an offset-stabilized input stage G3, and a two-stage

G1

G6

Vos

Vin

R1

Vout+

-

+-

CH2 CH1

+ -

R2

C11C21

C22

C41

C42

C51

C52

Cp6

V5+ -

G5

G3 G2

G4

FC

FC

Sample&Hold

Csh1

Csh2

FS

FS

FS

FS

C12

V6+ -

Fig. 5-1 Chopper offset-stabilization using an active integrator withsample-and-hold to reduce chopper ripple.

87

Chopper offset-stabilized operational amplifier

class-AB biased operational amplifier composed of G2 and G1. Thestabilization loop around G3 consists of a chopper amplifier, an integrator, asample-and-hold, and G4, which serves as an auxiliary input of G3. Thechopper amplifier consists of CH2, G6 and CH1, while the integrator iscomposed of G5 and capacitors C51 and C52. It should be noted that all thechoppers operate at the same clock frequency. The intermediate stage G2stage is mainly used to simplify the design. The current summing andclass-AB biasing do not have to be combined in this way. The two stages canbe combined, as will be demonstrated in the implementation described insection 5.3.

Due to feedback, the offset Vos appears at the input of chopper CH2. Asshown in figure 5-1, the amplifier is configured in an inverting topology viaresistors R1 and R2, but the system works with any negative feedbacknetwork. The modulated offset voltage is converted into a current by G6 andthen demodulated by CH1. The resulting DC current, which is proportional tothe input offset voltage, is integrated. The integrator then applies an offsetcompensating voltage at the input of G4. This transconductance acts as anauxiliary input for G3 and applies an offset compensating current to the outputof G3. For as long as there is offset present at the input of the entire amplifier,the integrator will try to reduce it. Without taking charge injection effects intoaccount, the residual offset due to finite gain can then be expressed by:

, (5-1)

where Vos is the uncompensated offset of the main amplifier consisting of G3,G2 and G1, and A0i, i=3, 4, 5, 6, are the DC voltage gains of the appropriateamplifier stages. This means that in order to reduce the offset of the mainamplifier from, say, 10 mV to 0.1 µV, the gain of the stabilization loop shouldbe at least 100 dB higher than the gain of G3.

The circuit shown in figure 5-1 can be considered as a multi-pathamplifier in which the cascaded transconductances G3, G2 and G1 form thelow-gain/high-frequency path, while the cascaded transconductances G6, G5,G4, G2, and G1 form the high-gain/low-frequency path. Capacitors C11, C12,C21, and C22 implement nested Miller frequency compensation [5.4] and arechosen to achieve a 60-degree phase margin for a 1 MHz unity gain frequencywith a 100 pF load. The two capacitors C41 and C42, together with the

Vos res gain, ,A03Vos

A04A05A06--------------------------=


88

integrator capacitors C51 and C52, form a hybrid-nested Miller frequencycompensation, as discussed in section 3.3.2.

Chopper ripple reductionThe modulated offset of G6 gives rise to chopper ripple, in the form of atriangular wave at the output of G5, which in turn gives rise to a triangularwave at the input of the whole amplifier. The input referred peak-to-peakvoltage of this triangular wave can be approximated by:

, (5-2)

where V6 is the offset of G6, FC is the chopper frequency, and C5 is theintegrator capacitance. For use as a general-purpose operational amplifier, theamplitude of this ripple should be reduced below the noise floor.

From equation (5-2) it can be seen that the amplitude of the ripple canbe minimized by decreasing the transconductance G6 and G4, and increasingthe size of the integrating capacitors C51 and C52. However, increasing thecapacitance size increases the chip area. While decreasing the transconductanceof G6 increases the input-referred noise of the amplifier. Alternatively, thechopping frequency can be increased, although this causes more residual offsetdue to the effect of charge injection in the chopper switches. It is also possibleto auto-zero G6, which is done in another implementation discussed insection 5.3.

In this design the chosen solution is to implement a sample-and-holdcircuit after the integrator, as shown in figure 5-1. The circuit samples thetriangular wave at the integrator output, thereby eliminating the ripple. The

Vin pp–V6G6G4

2FCC5G3----------------------=

chopper clock FC

integrator output

S&H clock FS

output S&Ht

Csh1 Csh1 Csh1Csh2 Csh2 Csh2

Fig. 5-2 Timing diagram. It is indicated if Csh1 or Csh2 issampling the output of G5.

89


timing of the sample moment is not critical, although the dynamic range ofthe integrator is used optimally when the triangular wave is sampled at thezero crossings. To achieve a quasi-continuous output signal, two sample-and-holdcircuits have been used. Their timing is arranged in such a way that while onesample-and-hold capacitor Csh1 is sampling, the other sample-and-hold capacitorCsh2 is driving G4. The timing diagram of the sample-and-hold is shown infigure 5-2.

The offset of G5 also contributes to the residual offset. This is becauseit appears as a chopped voltage that charges and discharges the parasiticoutput capacitance Cp6 of G6. The required current is provided by G6, whichmeans that a voltage must be present at its input. Hence there will be aresidual offset at the input of the amplifier. This residual offset is given by:

. (5-3)

To minimize this offset, the transconductance of G6 should bemaximized, while its parasitic capacitance should be minimized. However, ascan be seen from equation (5-2), maximizing G6 will increase the ripple. Adesigner could minimize the parasitic output capacitance of G6 by usingminimum-sized transistors and by minimizing the length of the metal wiresconnecting G6 to the chopper. A compromise will need to be made betweenresidual offset and ripple amplitude. Of course, the ripple amplitude at theoutput of the integrator is bounded by the power supply voltage of theintegrator, since the integrator cannot be allowed to clip.

A low transconductance of 4 µA/V is implemented to measure thisamplifier with clock frequencies down to 1 kHz. A clock frequency of 1 kHzcombined with integrator capacitors of 32 pF, a 15 mV worst case offset, anda G6 of 4 µA/V would lead to a triangular wave at the output of the integratorwith a peak-to-peak value of 1 V. With lower clock frequencies the integratorwould saturate.

Another possibility which increases the complexity of the circuit, butdoes not have conflicting trade-offs, is to cancel the integrator’s offset. Inorder to do this, a nested offset-stabilization loop is implemented around theintegrator. The complete topology can be seen in figure 5-3.

The offset V5 of G5 appears at the input of chopper CH1 as a squarewave. This signal is converted into a current and then demodulated by thesense amplifier G9 and chopper CH3, respectively. An integrator composed of

Vos res par, ,4V5FCCp6

G6------------------------=


90

G8, C81, and C82, integrates this current and then drives an offset compensatingcurrent into the output of G5 via its auxiliary input G7. All the choppers work atthe same clock frequency FC.

The offset V9 of G9 also needs to be reduced because it is a source ofadditional residual offset and output ripple. For this reason the multiplexerM1, integrator G11, and auxiliary input G10 are added, which auto-zero G9 athalf the chopper clock frequency. This technique is similar to the iterativeoffset-stabilization approach discussed in section 3.4.1.

To further investigate the behaviour of this topology, several parts ofthe circuit can be bypassed. By doing this, the three-stage amplifier consistingof G1, G2 and G3 can be measured. The offset-stabilization loop and nestedoffset-stabilization loop can be turned on separately, while the sample-and-holdcan be switched on or off.

G1G3

G4G5G6

Vin

R1

Vout+-

+-

CH2CH1

R2

C51

C52

G7G8G9

G10 G11

C81

C82C111

C112

CH3M1

V3+ -

V6+ -

V5+ -

V9+ -

Nestedstabilizationloop

Cp6

Sample&Hold

Csh

G2

C11C21

C22

C41

C42

C12

Fig. 5-3 Chopper offset-stabilization using an active integratorwith a sample-and-hold to filter the chopper ripple and anested integrator offset-stabilization loop.

91


5.2.2 Circuits

So far only the topology has been discussed. This section focuses on thecircuits with which this design has been implemented. First, the output stageis discussed. Secondly, the input stages are discussed. Both input stages aredesigned with the same topology, however, they are biased at different currentlevels. After that the integrator is discussed. Lastly, the biasing technique andbias current generator is discussed. The values of the transistor width W andlength L have been omitted because they were not chosen optimally. In theimplementations discussed in section 5.3.2, the values of W and L will beshown.

Output stageIn the implementation of the topology shown in figure 5-3, a class-AB outputstage was chosen for stages G1 and G2. This topology is shown in figure 5-4.The quiescent current through the output transistors M1 and M2 is controlledby two trans-linear loops designed with M1–4 and M5–8 [5.5]. The generalidea is that the gate source voltages of M1 and M5 are controlled by thesetranslinear loops such that:

. (5-4)

When M3 and M4 operate at the same drain current density, their gate-sourcevoltages are equal, so the gate-source voltages of M1 and M2 should also beequal. This means that the current through M1 when Iout = 0, i.e. the quiescentcurrent, is equal to:

. (5-5)

In this design the output transconductance was designed to be 2500 µA/V in order to drive a 100 pF output capacitor with a unity gain frequency of4 MHz. Since this stage has two preceding stages, and Miller compensation isused, the overall amplifier has a unity gain of 1MHz [5.4]. Since M1 and M5were only operating in moderate inversion, the quiescent current Iq through M1and M5 is 250 µA.

Transistors M9 and M10 are a copy of M4 and M8. They are added toimprove the offset voltage of the operational amplifier, by keeping the drain

Vgs1 Vgs4+ Vgs3 Vgs2+=

IqW1L2

W2L1------------I5=


92

source voltage of cascode transistors M12 and M14 almost equal. Without thetransistors M9 and M10 the drain-source voltages of M12 and M14 woulddiffer by a few volts, which in turn would cause their gate-source voltages todiffer, thus causing an input offset.

M1

M5M12

M4

M8

M6

M2M16VDD

VSS

M11

M10

M13

M14

I1

Vout

Vin

VB2

VB1

+

-

M3

M7

M9

M15

M17 M18

I2 I3 I5

I4

Iq

C11

C12

Fig. 5-4 Two-stage class-AB output operational amplifier implementationof G1 and G2.

M2

M13

VDD

VSS

M1M3

M4

Vout+

Vin

VB2

VB1

+

-

M14Vout-

M6M5 M8M7

M9 M10M11 M12

VCM

M15Vaux

+

-

M16

G3

G4

I1 I2 I3 I4 I5I6

Fig. 5-5 Folded cascode with auxiliary input for offset compensationand a common-mode feedback circuit.

93


Input stagesThe input stages G3 and G6 are implemented using a folded cascode topology.The circuit of G3 with its auxiliary input G4 can be seen in figure 5-5. PMOSinput transistors M13 and M14 are used to implement G3. Cascode transistorsM1–4, current sources I2 and I3, and current sources M9 and M10 are used toimplement a fully-differential folded cascode operational amplifier. Thecurrent through M9 and M10 is controlled by a common-mode feedbackcircuit designed with a differential-difference amplifier composed of longPMOS transistors M5–8. These transistors are long to achieve a lowtransconductance and a wider linearity range. This amplifier compares theoutput common-mode voltage to the voltage VCM and adjusts the currentthrough M11 to keep the output common-mode voltage equal to VCM.

M15 and M16 form the auxiliary input for the offset compensatingvoltage. Its output current is summed together with the output currents of M13and M14. A MOS transistor biased with a drain current Id in weak inversionhas the transconductance . In the process used, nVth=50mV atroom temperature. Thus, the differential input Vaux is effectively limited toabout 50 mV. The transconductance of G4 is chosen a factor of four lowerthan the transconductance of G3 by making I6 four times smaller than I1. Thismeans that the noise voltage associated with the sample-and-hold isreduced only by a factor of four, when referred to the input. Probably a betterimplementation would involve degenerating the differential input pair with aresistor Rdeg. A transconductance of would then be obtained andthe range of Vaux is given by , which can be made much larger then50 mV. In the implementations discussed in section 5.3 and chapter 6, theauxiliary amplifier was implemented in this way. This wider limit wouldmake better use of the integrator’s output dynamic range.

For G6, the same topology is used, but without the auxiliary input.From equation (5-2) it can be seen that the ripple amplitude is proportional toG6 and inversely proportional to the chopper frequency Fc. Therefore, thetransconductance of G6 is designed to be 100 times lower than that of G3 byapplying bias currents that are 100 times lower. This choice was made inorder to contain the ripple at the output of the integrator at low chopperfrequencies and to be able to measure at a 1 kHz chopper frequency. The lowtransconductance actually improves the DC voltage gain of G6 with respect toG3. However, it destroys the low frequency noise performance of the wholeamplifier, since this is dominated by the white noise of G6.

gm Id nVth⁄≈

kT C⁄

gm 1 Rdeg⁄≈IdRdeg


94

IntegratorIn order to achieve less then 0.1 µV offset, while the initial uncompensatedoffset is 10 mV, the DC voltage gain of G4, G5 and G6 has to be at least100 dB more than of G3, as can be seen in equation (5-1). The DC gain of G4is 4 times less than that of G3. The DC gain of G6 is about 50 dB over corners.A voltage divider with a voltage ratio of 25 was added after the integrator, tomake use of the dynamic range of the integrator. These decisions led torequired 80dB DC voltage gain.

Therefore, the operational amplifier G5, which is used as an integrator,was implemented by a two-stage amplifier as shown in figure 5-6. TransistorsM3 and M4 form an input differential pair, while transistors M1 and M2 form theoutput gain stage. Miller capacitances CM1 and CM2 are used to assure localstability. A resistor R1–4 network is used to sense the output common-modevoltage. This resistor divider also divides the output of the integratorcapacitances by a factor of 25. Transistors M5 and M6 make the outputcommon-mode voltage equal to a set voltage VCM at the source of the replicatransistor M7. With this common-mode feedback, a rail-to-rail output can becreated, which is needed to handle the chopper ripple. To make optimal use ofthe output dynamic range, VCM could be fixed at 0.5VDD.

M7M1

M6

VDD

VSS

M2

Vin

+

-

M5

R1

R2

VCM

C1

C2

CM1

CM2

VoutC+

VoutC-

M3M4

I2I1 I3 I4 I5

I6 I7 I8

R3

R4

Vout-

Vout-

to C51

to C52

to S&H

to S&H

Fig. 5-6 Two-stage class-A operational amplifier with resistivecommon-mode feedback.

95


Bias generatorAll the transconductance setting transistors in the amplification stages of theamplifier are of the PMOS type. To implement a constant transconductanceover temperature, a bias generator (illustrated in figure 5-7) was used. Thisbiasing is used in all implementations. In this part of the book it will be shownthat this biasing technique ensures a constant transconductance overtemperature.

In weak inversion, the effective gate-source voltage of a PMOStransistor is given by:

, (5-6)

where np is the weak inversion slope factor of a PMOS transistor, which isabout 2 for the used CMOS processes, and Is is the specific current, which fora PMOS transistor is given by:

. (5-7)

So when M1 is x times wider then M2 the current through Rptim is:

, (5-8)

VDD

VSS

M2

M5

Rptim

IptimM3

M1

M4 M7M6

xW2/L2 W2/L2

W2/L2

W4/L4 W4/L4 W4/L4 W4/L4

Fig. 5-7 PTIM current source.

V– gseff VT Vgs– npVthId

Is----ln= =

Is 2nµpCoxVth2 W

L-----=

IptimnpVth xln

Rptim--------------------=


96

which is actually a current proportional to absolute temperature. When aPMOS transistor operating in weak inversion is biased with a multiple of thiscurrent, its transconductance will be proportional to the value of the resistorsince:

. (5-9)

For strong inversion the effective gate-source voltage of a PMOS transistor isgiven by:

. (5-10)

The voltage over the resistor Rptim can be expressed as:

. (5-11)

Under the condition that the threshold voltages of M1 and M2 are equal andsubstituting and this leads to:

. (5-12)

This current is proportional to the inverse of the mobility µp, hence the namePTIM. The mobility is proportional to T–n, where [5.6]. The value of ndepends on doping concentration. If a multiplication of this current is used tobias a PMOS transistor in strong inversion, it can be seen that, again, itstransconductance is proportional to the resistor value since:

. (5-13)

Assuming that Rptim is constant over temperature, which is true for thin-filmresistors, which are available in many CMOS processes, it is clear that thisbiasing leads to a transconductance, which is, to first order, constant over

GmId

npVth------------ 1

Rptim------------∝=

V– gseff VT Vgs–2

µpCox------------- L

W-----Id= =

VR2

µpCox-------------

L2

W2-------Id VT2–

2µpCox-------------

L1

W1-------Id– VT1

L2

W2-------

L1

W1-------–

2

µpCox-------------Id≈+=

VR RptimId= L1 L2= W1 xW2=

Id1

Rptim2

------------ 2µpCox-------------

L1

W1------- 1 x–( )

2

x-------------------=

n 2.2≈

Gm µpCoxWL-----Id

1Rptim------------∝=

97


temperature. However, both the transconductance setting transistor and thebias current setting transistor should operate in the same region. In otherwords, this technique works best if the current density of M2 matches thecurrent densities of the transconductance setting transistors in theamplification stages. The transistors should also be of the same type to avoidinfluences of the p and n type doping.

Current consumptionIn simulations the amplifier draws a total current of 770 µA. In table 5-1, boththe value of the transconductance and the current consumption of each stageas well as the values of the capacitors are given. Although this design isn’tdesigned for optimal current consumption, it can be seen that the nestedstabilization loop that compensates for the offset of the integrator G5consumes only 12% of the total power.

Table 5-1. Capacitor values, transconductance, and current consumption of each stage.

StageTranscon- ductance

Current consumption Capacitors

Cap value

G1 2.5 mA/V 260 µA C11+C12 8 pFG2 130 µA/V 110 µA C21 & C22 60 pFG3 400 µA/V 180 µAG4 100 µA/V 12.5 µA C41 & C42 1 pFG5 40 µA/V 40 µA C51 & C52 40 pFG6 4 µA/V 2 µAG7 10 µA/V 1 µAG8 40 µA/V 40 µA C81 & C82 10 pFG9 4 µA/V 2 µAG10 1 µA/V 100 nAG11 40 µA/V 40 µA C111 & C112 10 pFBias 100 µA


98

5.2.3 Measurement results

The design was implemented in a 0.7 µm CMOS process, with a chip area of3.6 mm2. The chip micrograph is shown in figure 5-8. The measured supplycurrent is 700 µA from a 5 V supply voltage.

Frequency responseIn figure 5-9 the measured frequency response of the complete amplifier isshown. With a 50 pF load, the unity-gain frequency is 1.3 MHz with a56-degree phase margin. The circuit is also stable with a closed-loop DC gainof 80 dB and has a 20 dB per decade roll off, which demonstrates the efficacyof the multi-path hybrid-nested Miller compensation.

Fig. 5-8 Chip micrograph.

99


Fig. 5-9 Bode plot at a DC gain of 80 dB with a 50 pF load.


100

Noise spectrumThe noise spectrum is measured at theoutput of the amplifier. For thesemeasurements, the amplifier is used inan inverting configuration with a DCgain of 40 dB. The –3dB bandwidth isaround 10 kHz. The output noisespectrum of the amplifier with the offsetstabilization technique turned off isshown in figure 5-10a. Low frequency1/f noise can be seen. The output noise spectrum with thechopper offset-stabilization turned on isshown in figure 5-10b. The 1/f noise isnow suppressed by the chopperamplifier, and an increased white-noiselevel at low frequencies can be observedsince the stabilization loop producesmore noise than the main amplifier. Theinput referred noise density is of140 nV/√Hz. The chopper frequency is4 kHz and the chopper ripple is visibleas a small peak. When observed on anoscilloscope, the ripple is triangularwith an amplitude of about 250 µVamplitude ripple.In figure 5-10c, the output noise spectrumis shown with the sample-and-hold andnested stabilization loop turned on. In thismeasurement the sample-and-hold runs at2 kHz, and it can be seen that the chopperripple is now effectively suppressed.When observed on an oscilloscope, theripple is below the noise level. However,

since the sample-and-hold under-samples the wide band noise of the stabilizationloop, the total noise increases somewhat.

Fig. 5-10 Spectrum of theoutput noise (gain 40 dB) of: (a)the amplifier withoutoffset-stabilization; (b) theamplifier with chopper (4 kHz)offset-stabilized turned on; (c)as b with the sample-and-hold(2 kHz) and nested stabilizationloop turned on.

101


OffsetFirst, the initial offset of the amplifier was measured without activating anyoffset-stabilization circuits. Secondly, the chopper offset-stabilization circuitwas activated, resulting in the circuit of figure 5-1 without the sample-and-holdactivated. Next, the offset stabilization loop of the integrator was activated inorder to realise the circuit of figure 5-3, but without the sample-and-hold.Finally, the sample-and-hold was also enabled. The measurements were madeon 19 samples using an external clock generator. The measurements results aresummarized in table 5-2.

Fig. 5-11 Initial offset without any stabilization.

Fig. 5-12 Offset of a chopper offset-stabilized operationalamplifier without nested stabilization loop.


102

First, the offset of the amplifier without offset-stabilization ispresented. A histogram of all 19 samples is shown in figure 5-11. A 0.1mVaverage offset with a 1.5 mV average absolute deviation was measured. Theaverage absolute deviation from the mean was used as a figure of merit for thespread in offset voltage, because the measured offset distribution was nottruly Gaussian.

Second, the chopper offset-stabilization loop was activated, but withboth the nested integrator offset-stabilization loop and the sample-and-holdswitched off. A histogram of all 19 samples is shown in figure 5-12. With anexternally applied clock frequency of 16 kHz, a 16 µV average offset with a30 µV average absolute deviation was measured. Consequently, the spread is50 times lower than without offset compensation. The main cause of residualoffset is the offset of the integrator. This corresponds with the results ofsimulation.

Third, the nested offset-stabilization loop of the integrator wasactivated. A –1.4 µV average offset with a 0.5 µV average absolute deviationwas measured. A histogram is presented in figure 5-13. This shows that thisnested stabilization loop lowers the offset of the whole amplifier by more thana factor of 10 and reduces the spread by a factor of 60. The input-referredamplitude of the triangular ripple can be seen on an oscilloscope and can be ashigh as 250 µV.

Fig. 5-13 Offset of a chopper offset-stabilized operationalamplifier with nested stabilization loopexcluding sample-and-hold.

103


Finally, the sample-and-hold was activated to reduce the chopperripple below the noise level, and offset was measured at three different clockfrequencies. Theoretically, the offset should not be influenced by thesample-and-hold action. However, due to the reduction of the chopper ripple,some on-chip capacitive cross-talk effects were also reduced, which resultedin a somewhat lower average offset and average absolute deviation. Thehistogram of the measurements with a 16 kHz clock is shown in figure 5-14.

Fig. 5-14 Offset of chopper offset-stabilizedoperational amplifier according to figure 5-3including the sample-and-hold.

Table 5-2. Offset measurement statistics.

Circuit complexity

Clock frequency

(kHz)

Average offset (µV)

Absolute average offset deviation (µV)

A initial amplifier 16 100 1,500B figure 5-1 with-

out S&H16 16 30

C figure 5-3 with-out S&H

16 –1.4 0.5

D figure 5-3 16 –1.22 0.334 –0.8 0.1332 –1.81 0.67


104

With a 4 kHz clock frequency, an average offset plus average absolutedeviation of less than 1 µV was achieved. From table 5-2 it can be seen thatthe offset spread increases with the clock frequency. Therefore, it can beconcluded that clock-frequency-dependent capacitive cross-talk and chargeinjection are the main sources of the remaining residual offset.

5.3 Chopper and auto-zero offset-stabilized operational amplifier

In this section of the book, a chopped and auto-zeroed offset-stabilizedoperational amplifier will be presented. This design was implemented afterthe instrumentation amplifier presented in section 6.3, and in parallel with theinstrumentation amplifier presented in section 6.2. This amplifier wasimplemented to investigate the performance of a chopper and auto-zerooffset-stabilization topology, as discussed in chapter 3, and to reduce powerconsumption.

First the topology is presented. After that the transistor implementations ofthe transconductances used in this realization are shown. Then the measurementresults are shown in section 5.3.3. This section ends with conclusions.

5.3.1 Topology

The topology presented in this section is based on a two-stage amplifier.Around the first stage, a chopped and auto-zero offset-stabilized loop isimplemented, as can be seen in figure 5-15. Stages G1 and G2 form a mainamplifier implemented as a two-stage class-AB amplifier. The stabilizationloop around G2 consists of a chopped auto-zeroed amplifier, and an integrator.Stage G3 is an auxiliary input for this two-stage amplifier. The integrator,implemented with G4 and capacitors C41 and C42, applies an offsetcompensating voltage to the inputs of G3. The chopped and auto-zeroedamplifier G5 measures the offset of the main amplifier. Stages G5 and G4 areimplemented as a folded cascode and a gain-boosted folded cascode,respectively. Capacitors C11–12, C31–32 and C41–42 form the hybrid-nestedMiller frequency compensation, as discussed in section 3.3.2.

105

Chopper and auto-zero offset-stabilized operational amplifier

Instead of sampling the integrator output voltage, as was discussed insection 5.2.1, in this design the auto-zero technique is used to reduce thechopper ripple. As shown in equation (5-2), the chopper ripple isproportional to the initial offset of the chopped amplifier. Therefore,auto-zeroing this offset significantly reduces the chopper ripple, as discussedin chapter 3.3.5. Clock F1 is used to drive the auto-zero action.

In this design, the chopper switches, driven by clock FC, are also usedas auto-zero switches, i.e. to implement clock F1. Therefore, they are drawnas separate switches in figure 5-15. All clocks are generated synchronouslywith an on-chip oscillator and logic. The timing diagram is shown infigure 5-16.

The chopper clocks Fc and Fc alternate in time in order to drive theinput more symmetrically. Because logic is already needed to implementclock FC, this alternating algorithm only adds an insignificant portion to thecomplexity.

Comparing this design with the previous design, the input stage G5 hasa higher transconductance. Therefore, the white noise level should be muchlower. However, the switches driven by Fc and Fc can limit the white noise

+-

+-

+

-G5+

-G4

+

-

+

-+

-G3+

-

V5+ -

V4+ -

C32

C31

C42

C41CA1

CA2

FCF1

I3

+G2

+

-+G1

-

Vout

C11

Vin

V3

R1

R2

FC

FC

FCF1

+ -

C12

-+

Fig. 5-15 Chopped Auto-zeroed offset-stabilized operationalamplifier.


106

floor of the whole amplifier, because the noise contribution of the Ron ofminimum size switches is significant in comparison to the amplifier G5. In thiscase, these switches are chosen with W/L=11/0.7 µm instead of minimum sizeswitches of W/L=2/0.7 µm, which means that their charge injection is a factor5.5 more significant. This in turn leads to a higher residual offset.

The offset of G4 influences the residual offset, because it appears as achopped voltage that charges and discharges the parasitic output capacitanceCp5 of G5. The required current is provided by G5, which means that a voltagemust be present at its input. Hence there is a residual offset at the input of theamplifier. This residual offset is given by:

. (5-14)

If Cp5=1 pF, FC=30 kHz, and G5=200 µA/V, then a 10 mV offset V4would cause a residual offset of 6µV. To be able to achieve a lower offset, anauto-zero offset-stabilization technique is used around the integrator, asshown in figure 5-17. The transconductance G7 is auto-zeroed with clock F1.During clock F1 the auto-zeroed transconductance G7 measures the offset ofintegrator G4, and applies current to capacitor CA5, which functions as apassive integrator. Transconductance G7 is implemented as a copy of G5.Stage G6 is an auxiliary input of G4. The offset V4 of integratortransconductance G4 can be reduced down to:

, (5-15)

t

FC

FC

F1b

F1a

F1

F1

Fig. 5-16 Timing diagram.

Vores4V4FCCp5

G5------------------------=

V4res

V4----------- G4

Ao7G6---------------=

107


where Ao7 is the DC voltage gain of G7. Transconductances G4 and G6 sharethe same output impedance.

Furthermore, during the auto-zero action the inputs of G5 arealternatingly connected to the positive or negative input of the wholeamplifier. Without doing this the charge injection would only be applied toone input, leading to a systematic cause for residual offset. In thisimplementation only the charge injection mismatch between the switches thatare driven by F1a, F1b, Fc, and Fc introduces residual offset.

5.3.2 Circuits

So far the topology has been discussed. This part of the book focuses on thecircuits with which this design has been implemented. First the implementation

+-

+-

+

-G5+

-G4+

-

+

-+

-G3

+

-

V4+ -

C32

C31

C42

C41CA1

CA2

FC F1

I3

+G2+

-+G1

Vout

C11

Vin

V3

R1

R2

FCFC

FCF1b

F1a

+ -

+

-G7+

-

CA3

CA4

+

-G6+

-I6

F1

VCM5

F1

CA5

F1F1

C12

+

-

-

Fig. 5-17 Chopped Auto-zeroed offset-stabilized operational amplifierwith auto-zero offset-stabilized integrator.


108

of G1, G2 and G3 will be discussed. Then the implementation of the chopperamplifier G5 is presented. Finally, the integrator amplifier G4 is discussed.The transconductances are biased with the same biasing technique as describedin section 5.2.2.

Input and output stageIn figure 5-18 the implementation of G1, G2 and G3 is shown. In comparisonto the realization shown in figure 5-4, this output stage G1 consumes twotimes less quiescent current. Since a two-stage topology is used, only half thetransconductance is needed to obtain the same unity gain frequency as aMiller compensated three-stage amplifier.

To improve the independence of quiescent current to the power supplyvoltage VDD, cascode transistors M9 and M10 are added to the class-ABbiasing transistors M4 and M8. The quiescent current is dependent on thedrain source voltage of M4 and M8, which is dependent on VDD. The cascodesM9 and M10 fix the drain source voltages of M4 and M8.

To keep the drain source voltage of M16 at the same level as M15,transistors M17 and M18 are added. Since their drain current is twice as high

M1

M2

M12

M7

M8

M4

M3

M21

VDD

I2I 2I VSS

M9

M10

M11

M17

M18

M16

M13

M14

2I

Vout

Vin

VB2

VB1

+

-

I

M5

M6

M15M22

R2

R1

M19 M20

M23

Fig. 5-18 Two-stage class-AB operational amplifier with improveddependency of quiescent current to VDD and degeneratedauxiliary input.

109


as of M8 and M10 at quiescent, their width is doubled to keep the same currentdensity.

The auxiliary input G3 is implemented as a degenerated differentialpair. This degeneration makes the differential input range approximately 1 V,making the resistor divider in front of the auxiliary input, as used in theprevious section, superfluous.

The chopper amplifier G5 is implemented as a folded cascodeamplifier, as shown in figure 5-19. Again, the common-mode feedback circuitis designed with a differential difference amplifier composed of long PMOStransistors M5–8.

Fig. 5-19 Folded cascode operational amplifier.

M2

M13

VDD

VSS

M1M3

M4

Vout+Vin

VB2

VB1

+

-

M14

Vout-

M6M5 M8M7

M9

VCM

G5

I1 I2 I3 I4 I5

20µA 10µA 10µA

20µA 20µA

2.5µA 2.5µA

2.5µA 2.5µA

R9

M10 M11 M12

R10 R11 R1216kΩ 16kΩ 128kΩ 128kΩ

200/1200/1 50/1 50/1

60/1 60/1

400/1 400/1

180/1 180/1

5/15 5/15 5/15 5/15


110

IntegratorIn this design for the integrator operational amplifier G4, the two-stageconfiguration was not used. Instead a single stage gain-boosted topology[5.7], as shown in figure 5-20, was used. The gain-boosting amplifiers areshown in figure 5-21.

Gain-boost amplifier Gp fixes the drain voltages of M13 and M14 to avoltage VB2, while gain-boost amplifier Gn fixes the voltage over currentsources I2 and I3 to VB1, thus creating a very high output impedance. Again,the common-mode feedback circuit has been designed with a differentialdifference amplifier composed with long PMOS transistors M5–8. In thistopology the integrator does not have to be able to drive a large chopperripple. Consequently, this common-mode feedback can be used because arail-to-rail output stage is not necessary.

The gain-boost amplifiers Gp and Gn are depicted in figure 5-21. Theyboth use input common-mode feedback to apply the voltages VB1 and VB2 tothe inputs of the gain-boost amplifiers.

M2

M13

VDD

VSS

M1M3

M4

Vout+

Vin

VB2

VB1

+

-

M14Vout-

M6M5 M8M7

M9M10 M11 M12

VCMG4

I1 I2 I3 I4 I5

Gn

Gp

20µA 10µA 10µA 2,5µA

400/1 400/1

2,5µA

20µA 20µA 2,5µA 2,5µA

40/10 40/105/10 5/10

5/15 5/15 5/15 5/15

25/125/1

75/175/1

Fig. 5-20 Gain-boosted folded cascode topology.

111


Current consumptionThe amplifier as a whole is designed to consume 300 µA of current. Intable 5-3 the value of the transconductance of each stage and the currentconsumption of the stage as well as the values of the capacitors are given. Thebias current and oscillator consume 4 and 10 µA, respectively.

M2

M6

VDD

VSS

M1M3

M4

Vin

VB4

VB3+

-

M5

Gp

I11 I12 I13

I14 I15

M8 M7

VB2 M12

M16

VDD

VSS

M11M13

M14

Vin

VB4

VB3+

-

M15

Gn

I11

I12 I13

I14 I15

M18 M17

VB1

4µA

30/1

1µA 1µA

1µA 1µA 2µA 2µA 4µA 1µA 1µA

1µA 1µA 2µA 2µA

30/1 30/1 30/1

25/125/1

75/175/1

30/1 30/1 30/1 30/1

25/125/1

75/175/1

Fig. 5-21 Folded cascodes amplifiers with PMOS and NMOS inputpairs both using input common-mode voltage control.

Table 5-3. Capacitor values, transconductance, and current consumption of each stage.


Current consumption Capacitors Cap value

G1 1 mA/V 55 µA C11+C12 32 pFG2 200 µA/V 55 µAG3 2.5 µA/V 7.5 µA C31 & C32 32 pFG4 200 µA/V 50 µA C41 & C42 24 pFG5 200 µA/V 55 µA CA1 & CA2 4 pFG6 50 µA/V 7.5 µA CA5 4 pFG7 200 µA/V 55 µA CA3 & CA4 4 pF

Bias 4 µAOsc 10 µA


112


The design was implemented in a 0.7 µm CMOS process, and the chipmicrograph is shown in figure 5-22. The chip area is 2.7 mm2. The measuredsupply current is 280 µA from a 5.5 V supply voltage.

Noise SpectrumThe noise spectrum was measured at the output of the amplifier. For thesemeasurements, the amplifier was used in an inverting configuration with aDC gain of 40 dB. The spectrum is shown in figure 5-23. The measurementshows that the input referred noise is 33 nV/√Hz. The 1/f noise is effectivelysuppressed by the combination of the chopper and auto-zero offset stabilizationtechnique.


113


OffsetIn figure 5-24 the offset performance of two samples is shown versus thecommon-mode input voltage VCMin at supply voltages Vdd =3.3 V andVdd =5.5 V. From this measurement it can be concluded that the CMRR is125 dB and the PSRR is 118 dB.

00+E00.0

60-E00.1

60-E00.2

60-E00.3

60-E00.4

60-E00.5

50+E00.140+E00.130+E00.120+E00.1

)zH( ycneuqerF

Noi

se (V

/Hz0.

5 )

Fig. 5-23 Spectrum of the output noise (gain 40 dB) showing that the noise is3.3 µV/√Hz, indicating that the input referred noise is 33 nV/√Hz.


114

4-

5.3-

3-

5.2-

2-

5.1-

1-

5.0-

0

35.225.115.00

)V( niMCV

inpu

t offs

et ( µ

V)

[email protected]@[email protected]@8

Fig. 5-24 Input referred offset versus input common-mode voltageVCMin measured at two different supply voltages for twodevices.

02-

0

02

04

06

60+E00.150+E00.140+E00.130+E00.120+E00.1

)zH( ycneuqerF

Gai

n (d

B)

06-

0

06

021

081

Phas

e (d

egre

es)

esahP

niaG

Fig. 5-25 Bode plot of the operational amplifier in an invertingamplifier configuration with a DC gain of 40 dB.

115

Conclusions

Frequency responseA measured Bode diagram is shown in figure 5-25. The measured unity gainfrequency is 620 kHz with a phase margin of 57º. A chopper artifact can benoticed in the Bode diagram around 25 kHz. This artifact is caused byaliasing, caused by the sampling action of auto-zeroing.

5.4 ConclusionsIn this chapter two operational amplifiers have been presented. The first is achopper offset-stabilized operational amplifier, and the second is a chopperauto-zero offset-stabilized operational amplifier. Both circuits wereimplemented in a 0.7 µm CMOS process.

A chopper offset-stabilized operational amplifier with a GBW productof 1.3 MHz, a 140 nV/√Hz low frequency input referred noise and an offset ofless than 1 µV at a 4 kHz chopper frequency, or an offset less than 1.5 µV at achopper frequency of 16 kHz, was presented. The circuit consumes 700 µAfrom a 5.5V supply voltage.

This design proves that it is possible to design a low-offset widebandwidth chopper offset-stabilized amplifier. It was shown that the use of anested offset-stabilization loops significantly reduces the residual offset of theamplifier, and that the use of a sample-and-hold reduces the chopper ripple.

A chopper and auto-zero offset-stabilized amplifier was presented,which has a GBW product of 620 kHz, a 33 nV/√Hz low-frequency inputreferred noise, and an offset of less than 1.5 µV at a supply voltage of 3.3 Vwith a 25 kHz chopper frequency, and a 12.5kHz auto-zero frequency. Thecircuit consumes 280 µA from a 5.5 V supply voltage.

This design proves that a chopper auto-zero offset-stabilizedoperational amplifier is feasible. In comparison to the first design, in thesecond design the power consumption was reduced by 60%. Moreover, thenoise level at low frequencies was also reduced, because of the use of a 50times larger transconductance as stabilizing amplifier.

However, the lower noise also required a wider chopper switch toachieve a lower Ron. The resulting higher charge injection, together with thehigher chopper frequency, leads to a higher residual offset.


116

5.5 References[5.1] R. Burt, J.A. Zhang, “Micropower chopper-stabilized

operational amplifier using a SC notch filter with synchronousintegration inside the continuous-time signal path”, IEEEJSSC, pp. 2729–2736, Dec. 2006.

[5.2] OPA333 Datasheet “1.8V, micropower CMOS operationalamplifiers zero-drift series”, www.ti.com, May 2007.

[5.3] J.H. Huijsing, M.J. Fonderie, “Chopper chopper-stabilizedoperational amplifiers and methods”, US patent Nr. 6,734,723,Nov. 7, 2004.


[5.5] D.M. Monticelli, “A quad CMOS single-supply opamp withrail-to-rail output swing”, IEEE JSSC, Vol. SC-21, pp. 1026–1034, Dec. 1986.

[5.6] D. Neamen, “Semiconductor Physics & Devices”, Second ed.,New York, McGraw-Hill, 1997.

[5.7] K. Bult, G.J.G.M. Geelen, “A fast settling CMOS op amp forSC-circuits with 90-dBDC gain”, IEEE JSSC, pp. 1379–1383,Dec. 1990.

6

117

Realizations of Instrumentation Amplifiers 6

6.1 IntroductionIn chapters 2 and 3, the theory necessary for designing low-offset CMOSamplifiers was presented. In the previous chapter, implementations ofoperational amplifiers designed using this theory were discussed. This chapterfocuses on realizations of the indirect current-feedback instrumentationamplifiers discussed in chapter 4.

This chapter focuses on two realizations of indirect current-feedbackinstrumentation amplifiers. The first is a chopper and auto-zerooffset-stabilized indirect current-feedback instrumentation amplifier. Thesecond is an indirect current-feedback instrumentation amplifier for high-sidecurrent-sense amplifier applications.

Realizations of Instrumentation Amplifiers

118

6.2 Low-offset indirect current-feedback instrumentation amplifier

6.2.1 Introduction

In this section of the book, a chopped and auto-zeroed offset-stabilizedindirect current-feedback instrumentation amplifier will be presented. Thisdesign was implemented after the design which will be presented insection 6.3, and in parallel with the design presented in section 5.3. Thepurpose of this design is to investigate the performance of a chopper andauto-zero offset-stabilization topology for an instrumentation amplifier asdiscussed in chapter 4. This design is very similar to the design presented insection 5.3, except that extra input stages have been implemented to achievean indirect current-feedback instrumentation amplifier.

First, the topology of the amplifier is presented. After that thetransistor implementations of the used transconductances are discussed.Finally the measurement results are shown.

6.2.2 Topology

The simplified block diagram of the amplifier is shown in figure 6-1. There are twosignal paths: a high-frequency path and a low-frequency path. The high-frequencypath consists of input transconductor G21, which amplifies the input voltage Vin,while feedback transconductor G22 amplifies the feedback-voltage Vfb across theresistor divider R2 and R1. This voltage is proportional to the output voltage Vout.The difference in their output currents drives the output stage G1. The lowfrequency path consists of a chopped input transconductor G51, which alsoamplifies Vin, and a chopped replica transconductor G52, which also amplifies Vfb.The difference in their output currents drives an integrator around G4, which in turndrives a transconductance G3. If the transconductances of G51 and G52 are equal,the integrator’s output will converge until Vin and Vfb are equal. When Vin and Vfbare equal, transconductance G3 compensates for the offset of G21 and G22 byapplying a current I3.

119

Low-offset indirect current-feedback instrumentation amplifier

Input stages G51 and G52 determine the low-frequency characteristics.The DC gain of the instrumentation amplifier can be expressed as:

, (6-1)

assuming that G51 and G52 are identical.Since there are two input stages in this implementation, the offsets of

G51 and G52 create twice the chopper ripple compared to the operationalamplifier implementations discussed in chapter 5. In order to reduce thechopper ripple in this design, a combination of both chopping andauto-zeroing was used, as discussed in section 5.3. This implementation,which is shown in figure 6-2, is similar to the operational amplifier shown infigure 5-15.

During the auto-zero phase Faz, both the inputs of G51 and G52 areshorted, and both transconductance stages are put into a unity gainconfiguration. During this phase the input offset voltages are stored on CA1 toCA4.

Vout

Vin---------

R1 R2+

R2----------------

G51

G52--------

R1 R2+

R2----------------≈=

+-

+

-G51+

-G4

+

-

+

-+

-G3+

-

V4+ -

C32

C31

C42

C41

I3

+G22+

-

+G1

-

Vout

C11

V22

R1

R2+ -

Vfb

Vref+-

+G21+

-

V21+ -

+

-G52+

-

FCFC

+-Vfb

+-

Vin

FC

CH1CH21

CH22

Cp5

C12

-+

+

Fig. 6-1 Simplified topology of a chopped offset-stabilizedcurrent-feedback instrumentation amplifier.


120

As discussed before in section 5.3, the offset of the integrator V4together with the parasitic capacitance Cp5 seen at the inputs of CH1, again, isa cause of residual offset. This residual offset is given by:

. (6-2)

Therefore, an auto-zero offset-stabilization technique is used aroundthe integrator, as shown in figure 6-3. The transconductance G7 is auto-zeroedwith clock F1. During clock F1, the auto-zeroed transconductance G7measures the offset of integrator G4 and applies current to capacitor CA5,

Vores4V4FCCp5

G5------------------------=

+-

+

-G51+

-G4

+

-

+

-+

-G3+

-

V4+ -

C32

C31

C42

C41CA1

CA2

I3

+

-G22+

-

+G1+

-

Vout

C11

V22

R1

R2+ -

Vfb

Vref+-

+

-G21+

-

V21+ -

+

-G52+

-

CA3

CA4

FC FAZ

FAZFAZ FC

+-

Vfb

+-

Vin

CH1CH21

CH22

FC

C12

Fig. 6-2 Simplified topology of a chopped auto-zeroed offset-stabilizedcurrent-feedback instrumentation amplifier.

121


which functions as a passive integrator. Stage G6 is an auxiliary input of G4.The offset V4 of integrator transconductance G4 can be reduced down to:

, (6-3)

where Ao7 is the DC voltage gain of G7. Transconductors G4 and G6 share thesame output impedance. The timing diagram is shown in figure 6-4.

V4res

V4----------- G4

Ao7G6---------------=

+-

+

-G51+

-G4

+

-+

-G3

V4+ -

C32

C31

C42

C41CA1

CA2

I3

+G22+

-

+G1

-Vout

C11

V22

R1

R2

+ -

+

-G7

+

-

CA3

CA4

+

-G6

+

-I6

F1VCM5 F1

CA5

F1F1

Vfb

Vref+-

+G21+

-

V21+ -

+

-G52+

-

CA3

CA4

FC

F1FC F1b

F1a

FC

FC

+-

Vfb

+-

Vin

-

C12

+

+

++

- +

Fig. 6-3 Actual implementation of the chopped auto-zeroed offset-stabilizedinstrumentation amplifier with auto-zero offset-stabilizedintegrator.


122

6.2.3 Circuits

The circuits are very similar to the circuits shown in the operational amplifierimplementation of chapter 5.3. The only difference is that there are additionalinput stages to implement the feedback and replica inputs of the indirectcurrent-feedback amplifier. The implementations of G1, G21, G22, and G3 areshown in figure 6-5. The implementations of G51 and G52 are shown infigure 6-6.

t

FC

FC

F1b

F1a

F1

F1


M1

M5M15

M4

M8

M6

M2

M21

VDD

VSS

M9

M10

M11

M18

M17

M12

M16

Vout

Vfb

VB2

VB1

+

-

M3

M7

M20

R3

M14 M13

M19

M22Vaux

+

-

M23

R1R2

G1G22

G3

I1

I2 I3

I4

I5

I6

5µA 20µA 10µA 10µA 5µA 5µA 50µA

22.5µA 22.5µA 5µA 5µA 50µA

M24

60/1 60/1

400kΩ 400kΩ

300/1 1200/1

400/1 400/1

300/1 300/1

60/10 60/10

100/1 100/1

1500/0.7

600/0.7

60/0.7

150/0.7

20/0.7

60/0.7

60/0.7

60/0.7

20/0.7

20/0.7

40/0.7

40/0.7

40kΩ

R4 40kΩ

M21

Vin

+

-

M20

M19

G21

I1

20µA

1200/1

400/1 400/1 C11

C12

Fig. 6-5 Implementation of G1, G21, G22, and G3.

123


The integrator transconductor G4 is implemented as shown infigure 5-20, while the transconductor G7 is implemented is shown infigure 5-19.

Current consumptionThe amplifier as a whole is designed to consume 340 µA of current. In table 6-1,

M2

M13

VDD

VSS

M1M3

M4

Vout+Vfb

VB2

VB1

+

-

M14

Vout-

M6M5 M8M7

M9

VCM

G52

I1 I2 I3 I4 I5

20µA 10µA 10µA

20µA 20µA

2.5µA 2.5µA

2.5µA 2.5µA

R9

M10 M11 M12

R10 R11 R1216kΩ 16kΩ 128kΩ 128kΩ

200/1200/1 50/1 50/1

60/1 60/1

400/1 400/1M13

Vin

+

-

M14

I1

20µA

400/1 400/1

180/1 180/1

5/15 5/15 5/15 5/15

G51

Fig. 6-6 Implementation of G51 and G52.

Table 6-1. Transconductance and current consumption of each stage.


Current consumption Capacitors Cap value

G1 1 mA/V 55 µA C11+C12 32 pFG21+G22 220 µA/V 75 µA

G3 2.5 µA/V 7.5 µA C31 & C32 32 pFG4 200 µA/V 50 µA C41 & C42 24 pF

G51+G52 220 µA/V 75 µA CA1 & CA2 4 pFG6 50 µA/V 7.5 µA CA5 4 pFG7 200 µA/V 55 µA CA3 & CA4 4 pF

Bias 4 µAOsc 10 µA


124

for each stage both the value of the transconductance and the current consumptionof the stage as well as the values of the capacitors are given.


The design was implemented in a 0.7 µm CMOS process, and the chipmicrograph is shown in figure 6-7. The chip area is 3.5 mm2. It could havebeen 2.8 mm2, if the layout of the internal transconductance stages had notbeen optimised for the operational amplifier design presented in figure 5.3.The measured supply current is 325 µA from a 5.5 V supply voltage.

NoiseThe noise spectrum was measured at the output of the amplifier. For thesemeasurements, the amplifier was used in an inverting configuration with aDC gain of 40 dB. The spectrum is shown in figure 6-8. The measurementshows that the input referred noise is 42 nV/√Hz. Compared to theoperational amplifier described in section 5.3 the noise increases with a factor1.3. The noise seems flat and the 1/f corner is below 10 Hz.


125


00+E00.0

60-E00.1

60-E00.2

60-E00.3

60-E00.4

60-E00.5

60-E00.6

50+E00.140+E00.130+E00.120+E00.1

)zH( ycneuqerF

Noi

se (V

/Hz0

.5)

Fig. 6-8 Spectrum of the output noise (gain 40 dB) showing that thenoise is 4.2 µV/√Hz, which indicates that the input referrednoise is 42 nV/√Hz.

02-

0

02

04

06

60+E00.150+E00.140+E00.130+E00.120+E00.1

)zH( ycneuqerF

Gai

n (d

B)

042-

081-

021-

06-

0Ph

ase

(deg

rees

)

esahP

niaG

Fig. 6-9 Bode plot of the operational amplifier in an invertingamplifier configuration with a DC gain of 40 dB.


126

Frequency responseA measured bode plot is shown in figure 6-9. The measured unity gainfrequency is 630 kHz with a phase margin of 57°. Around 25 kHz a chopperartifact can be observed. This artifact is caused by aliasing, caused by thesampling action of auto-zeroing.

OffsetThe offset performance as a function of the supply voltage is shown infigure 6-10. From this figure it can be seen that the PSRR is 114 dB. Infigure 6-11 the offset performance is shown versus the common-modereference voltage Vref at supply voltage Vdd =3.3 V and Vdd =5.5 V. Infigure 6-12 the offset performance is shown versus the common-mode inputvoltage VCMin at supply voltage Vdd =3.3 V and Vdd =5.5 V. It can be seenthat the offset voltage is less than 2.5 µV for a supply voltage of 3.3 V. TheCMRR for both Vref and VCMin is 130 dB for Vdd =5.5 V.

0

1

2

3

4

5

6

7

8

5.665.555.445.335.22

V DD )V(

Offs

et ( µ

V)

V fer V= niMC 2.0=

Fig. 6-10 Offset as a function of supply voltage VDD.

127


01-

9-

8-

7-

6-

5-

4-

3-

2-

1-

0

5.445.335.225.115.00

V fer )V(

Offs

et ( µ

V)

V DD V V3.3= niMC V2.0=

V DD V V5.5= niMC V2.0=

Fig. 6-11 Offset as a function of reference voltage Vref at twodifferent supply voltages.

8-

7-

6-

5-

4-

3-

2-

1-

0

5.445.335.225.115.00

V niMC )V(

Offs

et ( µ

V)

V DD V V3.3= fer V4.0=

V DD V5.5=V V40

Fig. 6-12 Offset as a function of the input common-mode voltageVCMin at two different supply voltages.


128

001

5.001

101

5.101

201

5.201

301

5.445.335.225.115.00

V fer )V(

Gai

n

Fig. 6-13 Gain as a function of the reference voltage Vref.

001

1.001

2.001

3.001

4.001

5.001

6.001

7.001

8.001

543210

V niMC )V(

gain

1.0-

80.0-

60.0-

40.0-

20.0-

0

20.0

40.0

60.0

rela

tive

gain

err

or %

Vsupply 5.5V Vref 0.5Vrelative gain error

Fig. 6-14 Gain as a function of the input common mode voltageVCMin.

129

High-side current-sense amplifier

Gain accuracyIn a current-feedback instrumentation amplifier, the value of the inputtransconductance can change over the input common-mode voltage, causinggain errors. Therefore, not only are offset, CMRR and PSRR important, butalso the gain accuracy is important over the entire input common-mode rangeand reference common-mode range.

In figure 6-13 the gain is shown as a function of referencecommon-mode voltage Vref. A discrepancy in gain can be seen, because themeasurement setup has offset, and the input signal had to be inverted toprevent the output from clipping. In figure 6-14 the gain is shown as afunction of input common-mode voltage VCMin. It can be seen that the relativegain error is smaller than 0.05% from 0 to 3.6 V.

6.3 High-side current-sense amplifierIn this part of the book an indirect current-feedback instrumentation amplifierwill be discussed for high-side current-sense applications [6.1]. First,current-sensing will be introduced. Afterwards, the topology of the usedamplifier will be discussed in section 6.3.2. The circuits used in theimplementation of this topology will be shown in section 6.3.3. Measurementresults will be presented in section 6.3.4, followed by conclusions.

6.3.1 Current-sensing

Sensing supply currents is a fundamental requirement in many electronicsystems, and the techniques to do so are as diverse as the applicationsthemselves. Typical applications include: over-current protection,programmable current sources, and Coulomb counting to monitor the chargelevel of a battery.

The supply current is typically measured or sensed through a smallcurrent-sense resistor in series with the battery and load. So basically thereare two options to implement this current-sense resistor RS. It can either beimplemented between the negative power supply and the load, which is calledlow-side current-sensing, or at the positive power supply, which is called thehigh-side current-sensing, both of which are depicted in figure 6-15. Thevoltage across the sense resistor will be amplified by a current-sense


130

amplifier. In many applications it is also preferable to measure the supplycurrents through multiple loads.

Because of the low input common-mode voltage of the low-sidecurrent-sense amplifier, a single supply instrumentation amplifier could beused to amplify this signal. However, a high-side current-sense amplifiershould also be able to withstand a high input common-mode voltage and referits output voltage to ground. The implementation presented in this sectionfocuses on the challenges of designing a high-side current-sense amplifier.

However, there are important system-level disadvantages of low-sidecurrent-sensing [6.2]. Firstly, the load is shifted from ground, which could bea problem in a system design with multiple parallel current-sense systems.Secondly, various fault mechanisms cause a load to be shorted to ground,which bypasses the current-sense resistor and cause currents to remainundetected by low-side current-sensing. These facts increase the demand forhigh-side current-sense amplifiers. A few specifications can be derived byfocusing on the application of measuring the current flowing through alaptop-battery. Nowadays battery voltages already range up to 15 V, but theyare expected to increase in the future. Moreover, a higher voltage is appliedover the battery while it charges. Therefore it is not outrageous to design for a30 V maximum input common-mode voltage. After all, the current flowingthrough the laptop battery can range from a stand-by current of approximately10 mA to high-power currents of 10 A.

Generally speaking, to minimize the sense-resistor’s value and itspower dissipation, two specifications for high-side current-sense amplifiers

+

-

VBat

+

-

Vin1+

-

VBat

RS1

Load1+

- IS1

(a) (b)

Vinn+

-RSn

Loadn

ISn

+

-Vin1RS1

Load1

IS1

VinnRSn

Loadn

ISn

Fig. 6-15 Current-sensing principle (a) low-side, (b) high-side.

131


are critical: input offset voltage and common-mode rejection ratio (CMRR).In a laptop-battery application, a sense resistor of 1 mΩ means that the inputvoltage Vin can range from 10 µV to 10 mV. Therefore, the input offset shouldbe smaller than 10 µV and the CMRR should be higher than 130 dB to keepthe offset below 10 µV over a 30 V range.

The circuit shown in figure 6-16 can be used to monitor the chargelevel of a battery. The current-sense amplifier AS monitors the bidirectionalcurrent through the battery. This amounts to Vout>Vref for load currents andVout<Vref for charge currents. A user can select Vref to optimise the outputdynamic range of the current-sense amplifier for its application; if there is nointerest in the charging currents Vref can be equal to ground. The ADCdigitizes the output of the current-sense amplifier AS. A micro-processor thenintegrates this value and stores a value, which is proportional to the charge inthe battery. This application requires the current-sense amplifier to have again error of less than 0.5%. Moreover, because the laptop can consumepower in spurs, a signal bandwidth of 1 kHz is also required.

Many topologies can be used for implementing a current-senseamplifier: a resistor bridge amplifier, a flying or switched capacitor amplifier,a current follower, or an instrumentation amplifier implementation. The lasttwo are shown in figure 6-17.

Vin+

-

VBat

RS

Load

+

-IS

Vout+-

ADC

VDD

Vref+

-Charger

VDD

AS

+

-

µP

Fig. 6-16 Bidirectional high-side current-sense system.


132

In figure 6-17a, a current follower topology is used [6.3]. The gain ofoperational amplifier A1 forces the sense voltage Vin onto the input resistorRa. The current through this resistor equals the output current. For positiveVin, the gain of the current-sense amplifier can be expressed as:

. (6-4)

Transistor Qa isolates the high-voltage input from the low-voltageoutput, but offers no output voltage limit. To achieve a low-offsetcurrent-sense amplifier, the operational amplifier A1 can be designed for lowoffset, as discussed in the previous chapters.

A topology based on an indirect current-feedback instrumentationamplifier is shown in figure 6-17b. By making use of current summing at theoutputs of G1 and G2, the input and output, or reference common-mode voltagecan be isolated [6.4][6.5]. This implies that the input common-mode voltagecan be even lower than the output, or reference common-mode voltage. Theinput transconductance G1 amplifies the input voltage Vin, while a replicatransconductance G2 amplifies the feedback-voltage Vfb across resistor dividerR3 and R4. The difference in their output currents drives an operational

Vin

+

-RS

Rb

Ra

RoutVout R4

R3

+VDD

Vout-

(a) (b)

Qa

A3

+

-+-Vref

Vfb

A1+

- +

G1Vin

++

-RS

-

+

-

IS

IS

G2+

-

-+

Fig. 6-17 High-side current-sense amplifier based on (a) a V-to-Iconverter, (b) an indirect current-feedback instrumentationamplifier.

Vout Vref–

Vin---------------------

Rout

Ra---------=

133


amplifier A3. The feedback cancels the output currents of G1 and G2. The gainof the current-sense amplifier is:

. (6-5)

The offset of the amplifier shown in figure 6-17b is the sum of the offsetsof both G1 and G2. The next part of the book presents a low-offset indirectcurrent-feedback instrumentation amplifier for high-side current-sensingapplications. VDD can range from 2.8 to 5.5 V, while the input common-modeVBat can independently range from 2 to 30 V by making use of currentsumming at the outputs of G1 and G2.

The use of separate supply voltages simplifies the task of interfacingthe current-sense amplifier with other systems, for instance an ADC.Furthermore, the amplifier’s output can be referred to an external referencevoltage Vref, which can range from 0 V to VDD–1.4 V. Chopping andauto-zeroing are used to achieve an offset voltage of less than 5 µV over aCM input voltage range of 28 V, which in turn achieves a CMRR of morethan 140 dB. Compared to a recently announced low-offset current-senseamplifier [6.6], the chosen topology enables bidirectional current-sensing,e.g. of the current through a rechargeable battery. Furthermore, trimmedgain-setting resistors are used to achieve 0.1% gain accuracy.

6.3.2 Topology

The simplified block diagram of the amplifier is shown in figure 6-18. Athree-stage amplifier serves as the basis of this implementation. There are twosignal paths. The low frequency path consists of a chopped inputtransconductor G7, which amplifies the input voltage Vin, while a choppedfeedback transconductor G8 amplifies the feedback-voltage Vfb across theresistor divider Rfb and R1. This voltage is proportional to the output voltageVout.

The difference in the output currents of G7 and G8 drives an integratoraround G6, which in turn drives a transconductance G5. If the transconductancesof G7 and G8 are equal, the integrator’s output will change until Vin and Vfb areequal, i.e. until the main amplifier’s offset is compensated for. Transconductor G5compensates for the offset of G3 and G4 by applying a current I5.

Vout Vref–

Vin---------------------

R3 R4+

R4----------------

G1

G2------=


134

The high-frequency path consists of input transconductor G3 andfeedback transconductor G4. The difference in their output currents drives atwo-stage class-AB operational amplifier (G2 and G1). G3 and G7 are biasedvia the high-side CM input voltage VBat, while the other stages are biased viathe supply voltage VDD.

Transconductors G7 and G8 determine the low-frequency characteristicssuch as offset, low-frequency or 1/f noise, DC CMRR, and DC gain error. Whentheir transconductances are equal, the output currents of G7 and G8 will canceldue to the feedback and so:

. (6-6)

The offset and low-frequency noise is chopper modulated by chopperCH1, while the input and feedback signals are chopper-modulated anddemodulated by choppers CH2, CH3, and CH1, respectively. This will lead tothe associated offset and low-frequency noise reduction. The transconductorsG3 and G4 determine the high-frequency characteristics such as unity gainfrequency and high-frequency CMRR.

C62

C61

Vout

+

-Vfb

R1+

-Rfb Vfb

G3

Vbat

Vbat

VDD

I5

CH1CH2

CH3

C52 C22

C51C21

C11

Vin+

-

G4

G5 G2 G1G7 G6

G8

C12+

-

-

++

-

+

-

-

+

+

-

-

+

+

-

+

-

+

-

+

-

+

-

-

+

+

-

-

+ +

Fig. 6-18 High-side current-sense amplifier based on a multi-pathindirect current-feedback instrumentation amplifier.

Vout

Vin---------

R1 Rfb+

Rfb------------------

G7

G8------

R1 Rfb+

Rfb------------------≈=

135


The modulated offset voltage of G7 and G8 gives rise to ripple in theform of a triangular wave at the output of G6, which in turn, gives rise to atriangular wave at the output of the whole amplifier. The input referredpeak-to-peak voltage of this triangular wave is given by:

. (6-7)

To reduce this ripple, the combination of auto-zeroing and chopping isused, as shown in figure 6-19, where the low-frequency path is shown inmore detail.

All switches between Vfb and G8 are implemented with NMOStransistors. All switches between Vin and G8 are implemented with PMOSswitches in a high-voltage epi-pocket. Controlled by the clock F1, the offsetsof G7 and G8 are auto-zeroed by shorting their inputs, connecting G8 in aunity-gain configuration, and then storing the resulting voltage on capacitorsCA1 and CA2. In addition, G7 and G8 are chopped by clock FC to modulateboth the residual offset due to finite voltage gain and the under-sampled noiseassociated with auto-zeroing [6.7]. A level-shift circuit drives the high-sidechopper switches connected between the input voltage Vin and G7. Thesystem timing diagram is shown in figure 6-20. The base frequency of thechopper clock is 30 kHz clock. A 5 bit pseudo-random algorithm is used tovary this frequency between 28 kHz and 32 kHz to prevent aliasing.

Vin pp– V7 V8+( )G7 8, G5

2FchC6G3 4,---------------------------=

level shift

G7

G8

G6 G5

Vbat

Vin

Vfb

+

-

+

-

V7

V8

V6

C62

C61

CS

CA3

CA4

CA1

CA2

FC FCF1 F1 F4 F4 F4 F3 F2F1 F1

I5

VDD

VoutG2,1

R1

+

-RfbVfb

Fig. 6-19 Offset-stabilizing loop.


136

Note that in this design there are no auto-zero capacitors connectedbetween G7 and the input voltage, as there are in the implementation offigure 6-3. This is because in the process used, no high-voltage capacitorswere available. This, however, means that there is a systematic gain error inthis implementation due to the parasitic capacitance at the inputs of G8. Thisis illustrated in figure 6-21.

FC

F1

F2

F3

F4 t


Vin

Vfb

+

-

+

-

CA1

CA2

Vbat

G7

Cp1

Cp2

Va

+

-

G8

Fig. 6-21 Input stages with gain error due to capacitivevoltage division.

137


The parasitic capacitances Cp1 and Cp2 model the parasitic capacitancecaused by line capacitances. This causes the systematic voltage division:

, (6-8)

where CA=CA1+CA2 and Cp=Cp1+Cp2. This means that the overall gain ofthe instrumentation amplifier is:

, (6-9)

which means that in order to maintain a gain which is accurately defined bythe resistor values, G7 should be equal to G8, and Ca should be much largerthan Cp.

The combination of auto-zeroing, chopping, and the multi-pathtechnique is powerful. Auto-zeroing reduces the offset, and therefore thechopper ripple, while chopping modulates the folded noise associated withauto-zeroing to higher frequencies, where they can cause little harm becausethe characteristics of the amplifier are dominated by the high-frequency path.However, since the transconductances only see the input and feedbackvoltages half of the time, the signal-to-noise ratio is worsened by at least afactor .

The offset V6 of the integrator also causes residual input offset [6.8].To avoid this, the integrator is also auto-zeroed, as shown in figure 6-19.During the auto-zeroing of G7 and G8, the integrator’s output voltage issampled on CS by clock F2. This sampling operation also reduces thetriangular ripple caused by chopping [6.9][6.8]. Next, the integratingcapacitors C61 and C62 are disconnected from the output of G6 by clock F3,after which G6 is configured in unity-gain and its offset V6 will be stored oncapacitors CA3 and CA4 by clock F4. To avoid momentarily shorting theintegration capacitors, F3 and F4 are designed to be non-overlapping clocks.

Va

Vfb-------

CA

Cp C+ A-----------------=

Vout

Vin---------

R1 Rfb+

Rfb------------------

G7

G8------

Cp C+ A

CA-----------------=

2


138

In figure 6-22 the frequency compensation network is shown.Capacitors C11, C12, C21, and C22 form a nested Miller compensationnetwork [6.10], which is designed to obtain a GBW of 1MHz with a loadcapacitance CL of 100pF. Capacitors C61 and C62 are used as integrationcapacitors. Capacitors C51 and C52 are used to implement a hybrid-nestedMiller frequency compensation scheme with a smooth 20 dB/decade roll-off[6.10]. Without capacitors C51 and C52 the amplifier would only beconditionally stable.

6.3.3 Circuits

In this part of the book all the circuits are discussed that are used in thisimplementation. First, the gain determining input stages will be discussed.Secondly, the bias generator will be discussed, that generates the bias currentfor these input stages. Thirdly, the integrator implementation will bediscussed. Lastly, the output stage will be discussed. In this design the W andL values of the transistors have been omitted because of third party interest.

C62

C61

Vout

C11

C21

C51

C52 C22

G7

G8

G6 G5 G2 G1

G3

G4

C12 CL

+-

Vfb

+-

Vin

Fig. 6-22 Multi-path hybrid-nested Miller frequencycompensation in an indirect current-feedbackinstrumentation amplifier.

139


Input stagesTo sense the positive rail, the high-side input stages G3 and G7 should bedesigned with high-voltage capable NMOS input transistors. In contrast, theground-sensing input stages G4 and G8 should be designed with PMOS inputtransistors. Since these stages use different types of transistors and areoperated at different common-mode voltages, their transconductances will beinherently mismatched. To solve this problem, composite transistors are used,whose transconductances are set by resistors. In this way, accurate V-to-Iconverters can be realised [6.4] [6.11]. A simplified schematic of G7 and G8 isshown in figure 6-23.

The high-voltage input transconductors G3 and G7 are designed asfollows. The input NMOS transistors M1 and M2 act as voltage followers andforce the input voltage across resistors R1 and R2. Transistors M1 and M2 areimplemented with regular low-voltage NMOS devices, which are biased witha high-voltage bulk. This can be done because a twin-well BiCMOS processis used.

The drains of M1 and M2 are connected to high-voltage PMOS foldedcascodes M3 and M4, which drive high-voltage NMOS M5 and M6functioning as inverting amplifiers and as current-followers. The high gain ofthis local loop ensures that the transconductance of G3 and G7 is accuratelydefined by the values of R1 and R2. With the biasing currents shown infigure 6-23, the amplifier’s simulated gain variation is less than 0.15% over

PMOS NMOS NDMOS HVPMOS

G7 G8

Vin- Vin

+Vfb

+

Vfb-

VO+ VO

-CMFB

2I 2I4I

I I

6I 6I

2I 2I

I I8I

12I 12I

3I

3I

3I

3I

Vbat

VDD

VSS

M1

M3

M5

M7

M9

M11

M13

M15

M2

M4

M6

M8

M10

M12

M14

M16

R3 R4R1 R2

VB1

VB2

VB3

VB4

Fig. 6-23 Input transconductors G7 and G8.


140

the entire common-mode range. The high-voltage devices M3 to M6 canhandle common-mode voltages as high as 30 V, which is the limit imposed bythe process used. Transistors M1 to M4 are biased at a current I. As a result,the maximum input differential voltage range is 6IR, where R is the value ofR1 or R2. In this design this value corresponds to 150 mV.

A similar topology is used for G4 and G8, but with PMOS input transistors,NMOS cascodes, and NMOS current followers [6.11]. The input PMOStransistors M11 and M12 act as voltage followers and force the input voltageacross resistors R3 and R4. The drains of M11 and M12 are connected to NMOSfolded cascodes M13 and M14, which drive NMOS transistors M15 and M16functioning as inverting amplifiers and as current-followers. The high gain of thislocal loop ensures that the transconductance of G4 and G8 is accurately defined bythe values of R3 and R4.

To define the gain of the indirect current-feedback amplifier byexternal resistors, the transconductance defining both resistors R1 and R2 inG7 and R3 and R4 in G8 are laser-trimmed.

The output currents of the input stages are summed together in a foldedcascode. The fully differential amplifier needs one common-mode feedbackloop. The transconductance is determined by the degeneration resistor. Aspreviously mentioned, the maximum input differential voltage range is 6IR.To keep this value constant over temperature, a current should be used, thathas the same temperature characteristic as the degeneration resistors.

Bias generatorContrary to the constant transconductance biasing used in all otheramplification stages discussed in section 5.2.2, the degenerated input stagesneed to be biased with a constant current over temperature to maintain aconstant differential input voltage range. The circuit used is shown infigure 6-24. In this circuit both a proportional to absolute temperature [PTAT][6.12] and a current proportional to the base emitter voltage are summedtogether to generate a bandgap related constant current.

The PTAT current can be expressed as:

, (6-10)IptatkTqR2--------- A2A3

A4A1-------------ln=

141


in which Ax is the emitter area of the indexed transistor. The Vbe current canbe expressed as:

, (6-11)

in which Is1 is the saturation current of Q1. Since this parameter is highlytemperature dependent, the current IVBE has a negative temperaturedependency. Furthermore, since the Vbe and ∆Vbe voltages have opposedtemperature dependencies, an almost temperature-independent Ibg can beobtained by choosing the appropriate values for resistors R2 and R3.

IntegratorIn figure 6-25 the implementation of the integrator transconductance G6 isshown. An implementation very similar to figure 5-6 is used, the differencebeing that to assure a 100 dB open loop DC voltage gain, the cascodetransistors M9 and M10 are added to the input transistors M3 and M4. Thesecascode transistors are biased with diode connected transistor M8. Thecommon-mode feedback circuit is also implemented in the same way as infigure 5-6.

IVBEVbe5 Vbe4– Vbe1–

R3------------------------------------

Vbe1–

R3------------ kT

qR3--------- I1

Is1-----ln=≈=

VDD

VSS

Q2

IbgQ5

Q1

M2M1

Q4Q3

IptatI1

Vbe+

-

+

- R2

R1

R3

∆Vbe

IVbe

Fig. 6-24 BiCMOS constant current generator.


142

A potential disadvantage of this circuit is the switching transientbehaviour, caused by the two-stage topology. Since this amplifier is beingauto-zeroed, the output jumps from the common-mode voltage to the valuestored on the integrator capacitors. The two-stage topology has an increasedsettling time with respect to the single-stage topology. For this reason the

M7

M1M6

VDD

VSS

M2

Vin

+

-

M5

R1

R2VCM

C1

C2

CM1

CM2

Vout-

Vout+

M3M4

I2I1 I3 I4 I5

I6 I7 I8I9

M8

M9 M10

Fig. 6-25 Two-stage class-A operational amplifier with input cascode.

M1

M2

M12

M7

M8

M4

M3

M21

VDD

I2I 2I VSS

M9

M10

M11

M17

M18

M16

M13

M14

2I

Vout

Vin

VB2

VB1

+

-

I

M5

M6

M15M22

R2

R1

M19 M20

M23

Fig. 6-26 Two-stage class-AB operational amplifier with improveddependency of quiescent current to VDD.

143


folded cascode implementation was developed, which was later used in thealready discussed implementations in sections 5.3 and 6.2.

Output stageThe output stages G1 and G2 in this topology are designed in the same way asthe operational amplifier discussed in section 5.2, except that the class-ABbias is implemented again to obtain improved behaviour with respect to thepower supply voltage. The circuit is shown in figure 6-26. It is the samecircuit as discussed in section 5.3.2; figure 5-18, except that in order to keepthe layout symmetrical, transistors M15 and M17 are added as dummytransistors.


The current-sense amplifier was fabricated in a 0.8 µm BICMOS process withhigh-voltage transistors and laser-trimmed thin-film resistors. It has a die areaof 2.5 mm2. The chip micrograph is shown in figure 6-27. The output noise(gain = 11) spectrum density is shown in figure 6-28. At frequencies below10 kHz the input referred noise density is 136 nV/√Hz. At frequencies up to15 kHz, a slight increase in noise can be seen which is due to both thecombination of auto-zeroing and chopping, and the use of an offset-stabilizingtopology [6.9][6.8][6.7]. After 15 kHz the noise goes down almost linearlywith frequency to a value of 70 nV/√Hz.


144


x

x

0

150

0

150

10k

100k

frequency(Hz)

frequency(Hz)

No

rmal

ized

Ou

tpu

t N

ois

e(n

V/

Hz)

No

rmal

ized

Ou

tpu

t N

ois

e(n

V/

Hz)

300

300

Fig. 6-28 Output noise spectrum divided by the gain; gain = 11.

145


Measurements of ten samples show that the amplifier’s offset voltageis less than 5 µV, which together with its gain accuracy of 0.1% allows forprecise current measurements even with small sense resistors. In figure 6-29the offset performance of two samples is shown versus the reference voltageVref at Vdd =3.3 V, which is the common-mode voltage of the feedback inputVfb. It can be seen that the amplifier saturates when Vref =2.2 V. The CMRRfor the reference input is about 120 dB.

VDD = 3.3V

Vref (V)

VO

ffset

(µV

)

8

4

0

-4

-80 0.4 0.8 1.2 1.6 2.0 2.4

Fig. 6-29 Input referred offset voltage versus Vref.

VDD = 3.3V

VDD = 5.5V

VBat (V)

VO

ffset

(µV

)

2 6 10 14 18 22 26 30

048

-4-8

Fig. 6-30 Input referred offset as a function of input common-modevoltage VBat.


146

In figure 6-30 the offset performance of two samples is shown versusthe input common-mode voltage VBat. It can be seen that the offset stayswithin 2 µV over a 28 V change in VBat, which refers to 143 dB CMRR. Itcan also be seen that the offset changes about 2 µV over a 2.2 V change inVDD, which refers to a 121 dB PSRR. In figure 6-31 the CMRR is presentedas a function of frequency. For frequencies below 20 kHz, the CMRR is morethan 105 dB.

Not only offset is important for a current-sense amplifier, but, the gainaccuracy is also important over both the entire input common-mode andreference common-mode range. In a current-feedback instrumentationamplifier, the value of the input transconductance can change over inputcommon-mode voltage, causing gain errors.

In figure 6-32 the gain error is shown as a function of inputcommon-mode voltage VBat at three reference voltages. Clearly, both voltageshave an influence on the gain error. However, it can be seen that there is a±0.15% gain error caused by increasing VBat from 2 to 28 V. A 0.1% gainerror is caused by increasing Vref from 0 to 1.9 V when VDD is equal to 3.3 V.

Fig. 6-31 CMRR as a function of frequency.

147

Conclusions

6.4 ConclusionsIn this chapter two designs of chopper and auto-zero offset-stabilized indirectcurrent-feedback instrumentation amplifiers were presented. The first was a5.5V instrumentation amplifier, and the second was a current-sense amplifier,which is an instrumentation amplifier having one input fixed to a supplyvoltage which can range between 1.9 and 28 V.

Firstly, a chopper and auto-zero offset stabilized indirect current-feedbackinstrumentation amplifier was presented. The GBW is 630 kHz, and low-frequencyinput referred noise 42 nV/√Hz while consuming 325 µA from a 5.5 V supplyvoltage. The PSRR is 114 dB and the CMRR of both the reference and inputcommon mode is 130 dB. The gain accuracy is within 0.5% over a referencevoltage from 0 to 3.6 V at a 5.5 V supply voltage.

Secondly, a fully integrated indirect current-feedback instrumentationamplifier for current-sense amplifier applications was presented with an offsetvoltage of less than 5 µV. It has a common-mode input range from 2 V to30 V and achieves a 143 dB DC CMRR. The reference has a common-mode

Gai

n E

rror

(%)

VBat (V)

Vref =0V

Vref =1.9V

Vref =1.65

VDD=3.3V Vin=10mV

Fig. 6-32 Gain error as a function of input common-modevoltage VBat.


148

range from 0 V to VDD–1.4 V. This gives the current-sense amplifier theintrinsic bidirectional behaviour of an instrumentation amplifier. By usingaccurate V-to-I converters as input stages, a gain accuracy of 0.1% can beobtained for a fixed reference voltage. The GBW is 1 MHz, and alow-frequency input referred noise of 150 nV/√Hz is obtained, whileconsuming 1,050 µA supply current.

In table 6-2, this design is compared to a recently introducedcurrent-sense amplifier [6.6]. These two amplifiers offer a new level ofprecision in current-sensing. In addition, however, the topology presentedhere has the natural bidirectional current-sensing capability of aninstrumentation amplifier.

The first design has a better gain accuracy over common-mode voltagethan the second design for two reasons. Firstly, the input stage and replicastage are identical in the first design, while in the second design they arecompletely different. Secondly, in the first design the input common-modevoltages seen by the gain setting stages are equal. Therefore, the gainaccuracy is dependent on the quality of the capacitors and switches, in

Table 6-2. Comparison of low-offset current-sense amplifiers.

LTC6102 [6.6] This workYear of release/

publication2007 2008

Offset 10 µV 5 µVBidirectional No Yes

Gain Accuracy External resistor dependent

0.15%

Isupply shutdown No 1 µAVDD VBat 2.8 to 5.5 VVBat 4 to 60 V 1.9 to 30 VVout 0 to 8 V 0 to VDD

Isupply from VBat 420 µA 200 µAIsupply from VDD 850 µA

149

References

contrast to the second design in which the high-voltage input operates at adifferent input common-mode voltage.

6.5 References[6.1] J.F. Witte, J.H. Huijsing, K.A.A. Makinwa, “A current-feedback

instrumentation amplifier with 5mV offset for bidirectionalhigh-Side current-sensing”, IEEE ISSCC, pp. 74–75, Feb. 2008.

[6.2] Linear Technology Corp., “Application note 105: Current sensecircuit collection”, http://www.linear.com/ad/current_sense.jsp,Feb. 2008.

[6.3] Linear Technology Corp., “LT1787”, Datasheet, www.linear.com,Apr. 2007.

[6.4] R.J. v.d. Plassche, “A wide-band monolithic instrumentationamplifier”, IEEE JSSC, pp. 424–431, Dec. 1975.

[6.5] B.J. van den Dool, J.H. Huijsing, “Indirect current feedbackinstrumentation amplifier with a common-mode input rangethat includes the negative rail”, IEEE JSSC, pp. 743–749, July1993.

[6.6] Linear Technology Corp., “LTC6102”, Datasheet, www.linear.com,July 2007.

[6.7] A.T.K. Tang, “A 3 µV-offset operational amplifier with 20 nV/√Hz input noise PSD at DC employing both chopping andautozeroing”, IEEE ISSCC, pp. 386–387, Feb. 2002.

[6.8] J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, “A CMOSoffset-stabilized opamp”, IEEE JSSC, pp. 1529–1535, July2007.

[6.9] R. Burt, J. Zhang, “A micropower chopper-stabilizedoperational amplifier using a SC notch filter with synchronousintegration inside the continuous-time signal path”, IEEEJSSC, pp. 2729–2736, Dec. 2006.


[6.11] J.H. Huijsing, B. Shahi, “Accurate voltage-to-current convertersfor rail-sensing current-feedback instrumentation amplifiers”,US patent Nr. 7,202,738, Apr. 10, 2007.


150

[6.12] R.C. Dobkin, “Input supply independent circuit”, US patentNr. 3,930,172, Dec. 30, 1975.

[6.13] Linear Technology Corp., “LT6104”, Datasheet, www.linear.com,Apr. 2007.

7

151

Conclusions and Future Directions 7

7.1 ConclusionsThe theory and realizations presented in this book show that theoffset-stabilization techniques, as discussed in section 3.3, can be used todesign broad-band low-offset general-purpose operational amplifiers andinstrumentation amplifiers. The chopper offset-stabilization amplifier can beused to obtain good noise performance. However, the chopper ripple remainsa problem. This problem can be overcome by using a sample-and-hold inorder to low-pass filter the ripple [7.1] [7.2], or to use a chopper and auto-zerooffset-stabilization amplifier [7.3]. The latter technique will lead to amplifierswith a √2 higher low-frequency noise, unless, a ping-pong technique is used[7.4] [7.5].

7.2 Future directionsThe field of dynamic offset compensation techniques does not end with thisbook. A number of advancements can still be made in future researchprojects. This section gives just an idea of what the future will bring and whatkinds of projects might follow the work presented in this book.

Conclusions and Future Directions

152

An important remark to be made is that there should always be amarket for a product. For instance, an expensive amplifier with a less than100 nV input-referred offset will probably not do very well, because there aresimply not many applications that really benefit from an offset of less than1 µV. Thermocouple effects on printed circuit boards would also ruin theultra-low offset. These same thermocouple effects increase the testing cost ofsuch amplifiers. Therefore, a general-purpose instrumentation amplifier withless than 1 µV offset will probably never be available on the market.However, if a sensor interface requires offsets of less than 100 nV, forinstance in Hall sensors for compass applications [7.6], this requirementcould be achieved by custom on-chip read-out electronics.

Recently a CMOS amplifier has been published in which trimmingwas used to obtain a low offset with a 0.33 µV/ºC offset drift [7.7]. In chapter2, it was shown that dynamic offset compensated amplifiers perform verywell if the inherent offset is already low. In the future, there might be someproducts in which offset trimmed amplifiers are also chopped to obtain asub-microvolt offset and low noise. If and when these circuits will bedeveloped would depend on the market. If the increased trimming cost isbelieved to be more beneficial than the increased circuit complexity, whichincreases both design time and time to market, it will happen.

In this book the feasibility has been proven for a low-offset indirectcurrent-feedback instrumentation amplifier for high-side current sensingapplications. In the future, this topology could be adopted by the industry.Nowadays, high-voltage low-offset amplifiers are available for currentsensing applications [7.3] [7.8]. In these applications, one input is alwaysconnected to the high-voltage supply. It might be an interesting project todesign a high-voltage rail-to-rail input stage capable of sensing up to both thehigh-voltage rail as well as the ground rail. This way a current-sense amplifiercould be obtained for both low-side and high-side current-sensingapplications.

In this book two techniques has been discussed in which the chopperripple in chopper amplifiers or chopper offset-stabilized amplifiers is reduced.The first technique uses a sampler which samples the chopper ripple. Thesecond technique uses a chopped and auto-zeroed input stage which samplesthe input offset and thereby decreases the ripple. Both techniques, however,use a sampling action. This can cause a ripple due to kT/C noise of thesampling capacitors, noise aliasing, and signal aliasing effects. It is advisableto investigate future techniques in which the ripple can be reduced by using

153

References

continuous-time circuits. A continuous time ripple reduction loop has alreadybeen described in [7.9].

The chopper offset-stabilized chopper amplifier and specifically theiterative offset-stabilization technique discussed in section 3.4.1 have thepotential of a very low offset, since every source of offset has beenoffset-stabilized. This topology, however, can still be thoroughly researched.The ping-pong-pang instrumentation amplifier proposed in section 4.2.3[7.10] has the potential to obtain a very good gain-error specification, whichcan also still be researched more thoroughly.

A step beyond dynamic offset compensation is dynamic offset and gaincompensation. It might be advantageous to design an instrumentationamplifier that dynamically compensates for its own offset as well as its owngain error. It could, for instance, be possible to auto-calibrate twotransconductances by applying the same input signal to both their inputs andauto-calibrating their output currents to be equal. Combining dynamic gaincompensation with dynamic offset compensation could be another interestingresearch challenge.

7.3 References[7.1] R. Burt, J. Zhang, “A micropower chopper-stabilized

operational amplifier using a SC notch filter with synchronousintegration inside the continuous-time signal path”, IEEEJSSC, pp. 2729–2736, Dec. 2006.

[7.2] J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, “A CMOS chopperoffset-stabilized opamp”, IEEE JSSC, pp. 1529–1535, July2007.

[7.3] J.F. Witte, J.H. Huijsing, K.A.A. Makinwa, “Acurrent-feedback instrumentation amplifier with 5µV offset forBidirectional High-Side Current-Sensing”, IEEE ISSCC, pp.74–75, Feb. 2008.

[7.4] Texas Instruments, “0.05µV/C max, single-supply CMOS opamps zero-drift”, Datasheet, Rev. D, OPA335, June 12, 2003.

[7.5] Thomas Kugelstadt, “Auto-zero amplifiers ease the design ofhigh-precision circuits”, Texas Instruments, 2005,focus.ti.com/lit/an/slyt204/slyt204.pdf.

Conclusions and Future Directions

154

[7.6] J.C. van der Meer, F.R. Riedijk, E. van Kampen, K.A.A.Makinwa, J.H. Huijsing, “A fully integrated CMOS Hallsensor with a 3.65µT 3σ offset for compass applications”,IEEE ISSCC, pp. 246–247, Feb. 2005.

[7.7] M. Bolatkale, M.A.P. Pertijs, W.J. Kindt, J.H. Huijsing,K.A.A. Makinwa, “A biCMOS operational amplifierachieving 0.33µV/ºC offset drift using room-temperaturetrimming”, IEEE ISSCC, pp. 76–77, Feb. 2008.

[7.8] Linear Technology Corp., “LTC6102 data sheet”,www.linear.com, July 2007.

[7.9] R. Wu, K.A.A. Makinwa, J.H. Huijsing, “A choppercurrent-feedback instrumentation amplifier with a 1 mHz 1/fnoise corner and an AC-coupled ripple-reduction loop”, IEEEISSCC, pp. 322–323, Feb. 2009.

[7.10] J.H. Huijsing, “Instrumentation amplifiers developments”,AACD workshop, Pavia, Apr. 9, 2008.

A

155

Layout Issues A

A.1 IntroductionA book describing dynamic offset compensated amplifiers, withoutinformation about layout issues would be unfinished. Analog engineerssometimes overlook critical layout issues, therefore, redesigns can becomenecessary in practical implementations of auto-zero and chopper amplifiers. Itis always advisable to do a parasitic extraction in dynamic offset compensatedsystems.

Contrary to normal amplifiers, dynamic offset compensatedamplifiers require on-chip oscillators and digital circuits to generate clocks,which drive the dynamic offset compensation circuits. The clock generation,clock distribution, and switching can severely cripple the offset performanceof these amplifiers.

In order to improve common-mode behaviour it is also beneficial toshort the backgate of input switches to the sources, as shown in figure A-1.Because the backgate source voltage changes with the input common-mode infigure A-1a, the threshold voltage is effected. This means that the channelcharge injection is modulated by the common-mode input voltage, whichtranslates into a CMRR limit. The implementation shown in figure A-1b alsohas an extended common-mode range.

Layout Issues

156

In section A.2 methodologies are shown to minimize chopperparasitic capacitance mismatches, and section A.3 deals with shieldingtechniques for clock lines and ground lines. This chapter ends withconclusions in section A.4.

Clock feedthroughIn section 2.3.3 it was illustrated that the mismatch of clock feedthroughcapacitances in a differential chopper amplifier can cause a residual offsetvoltage [A.2]. In section 2.3.3 it was also shown that the residual offset can beexpressed by:

, (A-1)

M1

FC

M2

M3

FC

M4

M1

FC

M2

M3

FC

M4

a b

C1

C2

C3

C4

C1

C2

C3

C4

inn

inp

outn

outp

inn

inp

outn

outp

Fig. A-1 Two possible implementations of NMOS choppers (a) withbackgates connected to ground, (b) with backgates connectedto the sources.

Vout

CH2CH1

+-

Vin+

-G1Va

+-

Vb+-

LPF Vlfp+-

C1C2

VFC

R1

R2 C4

C3

Fig. A-2 Charge injection model in a chopper amplifier.

Vos res1, 2 R1 R2+( ) C1 C2–( )VFFC=

157

Chopper layout

where (R1+R2) is the input impedance including ON-resistances of thechopper switches, (C1–C2) is the mismatch of clock feed throughcapacitances, VF is the driving voltage, and FC is the chopper frequency. Forexample a 20 kHz chopper frequency, ON-resistance of 5 kΩ, no sourceimpedance, and a 5V driving voltage would lead to a residual offset per unitof capacitance mismatch between C1 and C2 of 2 µV/fF.

Also the capacitors C3 and C4 depicted in figure A-2 can causeresidual offset. This leads to a residual offset which can be expressed by:

, (A-2)

where G1 is the transconductance of the chopped amplifier. It can be seen thathigher transconductance amplifiers are less vulnerable to the mismatch of C3and C4. For example for a 20 kHz chopper frequency, a 100 µA/Vtransconductance, and a 5 V driving voltage would also lead to a residualoffset per unit of capacitance of 2 µV/fF.

It can be concluded that the mismatch of C1 and C2 as well as themismatch of C3 and C4 are both of importance and effort must be made tominimize those mismatches. Therefore, the next section focuses on the layoutof choppers.

A.2 Chopper layoutTwo layouts of choppers have been developed during the design of theamplifiers discussed in chapters 5 and 6. The analysis in the previous sectionshowed that charge injection mismatch from the input chopper to the input ofthe amplifier that is chopped and from the output chopper to the output of theamplifier that is chopped is what mainly causes the residual offset.

This charge injection can be reduced by reducing the absolutecapacitive crosstalk from clock lines towards the one side of the chopper. Inthe layout shown in figure A-3 the poly clock lines only run parallel to theinput lines, and do not run parallel to the output lines. Except for the parasiticcapacitance mismatch due to metal differences, there can also be a mismatchin the gate-source and gate-drain capacitance due to transistor mismatch. Tominimize transistor mismatch the use of dummy transistors is widely

Vos res2,2 C3 C4–( )VFFC

G1------------------------------------=

Layout Issues

158

accepted [A.1]. The chopper layout shown in figure A-3 contains two dummytransistors: MD1 and MD2. These dummy transistors give transistors M1–M4topologically and electrically the same surroundings. The gate line driving thedummy switch MD2 is necessary to make the crosstalk from Fc to inn equal to

via con act m1m2 pol

inn inp outn outpFc Fc

gnd gnd gnd

M1

M2

M3

M4

MD2

MD1

CA1

CB1

CB2

CA2

CA3

CB3

CB4

CA4

Fig. A-3 Chopper layout with dummy switches to balance theparasitic capacitances and improve the mismatch ofthe chopper switches.

159

Chopper layout

the crosstalk of Fc to inp by making the capacitances CA1+CA2 equal toCA3+CA4. The gate line driving MD1 is not really necessary, although it doeshelp making the parasitic crosstalk from Fc to inn and inp and from Fc to innand inp equal to each other, which helps in reducing common-mode spikes.To further reduce capacitive clock feedthrough, a grounded metal 1 plate isused to shield the metal 2 clock lines from the signal lines.

In conclusion, the layout depicted in figure A-3 has matched switchtransistors, minimised capacitive crosstalk towards the output, and balancedcrosstalk from each clockline to the differential inputs and outputs. Adisadvantage of this layout is that it needs a large area. By using minimumsize switches, the matching will never be very good and so the use of dummytransistors may be regarded as being superfluous.

Another more compact layout was developed without the use ofdummy transistors. This layout was made as symmetrically as possible tobalance the parasitic capacitances. This layout is shown in figure A-4. Incomparison to the previous layout, the switches are closer to each other,which improves transistor mismatch.

via con act m1m2 pol

inn

inp

outn

outp

Fc Fc

M1

M2

M4

M3

gnd

Fig. A-4 Compact chopper layout with balanced and shielded clockfeedthrough capacitances.

Layout Issues

160

The absolute parasitic capacitance is reduced with respect to theprevious layout because, firstly, the signal lines and clock lines are alwaysperpendicular to each other, whereas in figure A-3 they also run parallel toeach other. Secondly, it is possible to shield the metal 2 signal lines from thepoly clock lines with a grounded metal 1 shield.

During the research described in this book the two layouts were bothused, but they were never used in the same amplifier. Therefore, it could notbe verified experimentally which layout would benefit residual offset themost. The layout shown in figure A-3 has been used in the operationalamplifier design described in section 5.2, all other implementations use thelayout depicted in figure A-4.

A.3 Clock shieldingIn the previous section, layouts of choppers were discussed. The clock signalshave to be routed from the clock generation circuit to the switches of thedynamic offset compensation. This could lead to unforeseen clockfeedthrough and substrate feedthrough.

To minimize the clock feedthrough, an on-chip coax cable was usedin all designs. A cross section of this layout is shown in figure A-5. Agrounded shield can be made, which confines the clock signals. In atwo-metal process the substrate (or P-well) itself can be grounded, which thenserves as a bottom plate.

This reduces the clock feedthrough from the clock lines to the analogsignals of the amplifier. A disadvantage, however, is that the capacitance of

grounded P-substrate/P-Well

M1

M2

M3

gnd

gnd

gnd gnd

gnd

gnd gnd

a b

FC FC

FC FC

Fig. A-5 Cross sections of on-chip coax clock lines in (a) a 3-metalprocess and (b) a 2-metal process.

161

Clock shielding

the clock lines to ground increases and relatively strong digital buffers areneeded to boost the clock signals.

Another disadvantage is that by using all metal layers available in aprocess, there are no remaining metal layers to route signals from one side ofthe shield to the other side of the shield. However, when the layout of adynamic offset compensated amplifier is planned carefully, crossings are notnecessary. When a crossing is unavoidable, the crossing should be created insuch a way that the parasitic capacitive feedthrough is balanced. It is alsoimportant that the clock generation circuits do not interfere too much with theamplifier. The separation of an analog and digital ground can be advised.

An example of a chip is shown in figure A-6. In this layout theoscillator and digital circuit that generate the clock signals are placed in the

Fig. A-6 Chip micrograph of the operational amplifier discussed inchapter 5.3 with the oscillator, on-chip coax, and chopper andauto-zero switches, SW, indicated.

Layout Issues

162

bottom. The on-chip coax is used both to shield the clock generation circuitsfrom the amplifier and to shield the clock signals that are confined by theon-chip coax. In this chip the chopper and auto-zero switches are designedsimilarly to the chopper shown in figure A-4.

In these layouts the ground was separated in four grounds: an analogground to bias the amplifier, a digital ground to bias the clock generationcircuit, a shield ground to bias the on-chip coax, and a separate ground to biasthe output stage of the amplifier.

A.4 ConclusionIn this appendix a brief overview was given to address critical layout issues.Two layouts of chopper amplifiers were discussed both of which balanceparasitic capacitive clock feedthrough. It was also shown that the use of anon-chip coax makes the shielding of clock lines possible. As an example, astrategy for the layout of one amplifier was discussed. In conclusion, it is veryimportant to carefully plan the layout of a dynamic compensated amplifier,and to be very aware of the problems of unbalanced clock feedthroughcapacitors in dynamically offset compensated systems.

A.5 References[A.1] A. Hastings, “The art of analog layout”, New Jersey: Prentice

Hall, 2001.[A.2] A. Bakker, J.H. Huijsing. “High-accuracy CMOS smart

temperature sensors”, Dordrecht: Kluwer, 2000.

163

About the Authors

J.F. (Frerik) Witte was born in Amsterdam,the Netherlands, on March 16, 1979, wherehe lived until finishing his high schooleducation (Atheneum) at the PieterNieuwland College in 1997. In that year hemoved to Delft to start his studies inelectrical engineering. He received his M.Sc.degree in electrical engineering (cum laude)from Delft University of Technology in2003. The subject of his M.Sc. thesis was“On-Chip Time References and Electro-Thermal Oscillators”. In 2003, he startedworking towards a Ph.D. degree at theElectronic Instrumentation Laboratory of

Delft University of Technology. The subject of his research was to designlow-offset broadband CMOS amplifiers, which resulted in this book.

From January to April 2003, he did an internship at PhilipsSemiconductors, San Jose, California, where he worked on integrateddiagnostic circuits to measure the value of an external capacitor. SinceJanuary 2009, he is working as a senior design engineer for NationalSemiconductor at Delft. His professional interests include sensors, precisionanalog and mixed-signal design. He received the ESSCIRC 2006 YoungScientist Award.

About the Authors

164

Kofi A. A. Makinwa received the B.Sc. andM.Sc. degrees from Obafemi AwolowoUniversity, Ile-Ife, Nigeria, in 1985 and1988, respectively, the M.E.E. degree fromthe Philips International Institute,Eindhoven, the Netherlands, in 1989, andthe Ph.D. degree from Delft University ofTechnology, Delft, the Netherlands, in 2004.

From 1989 to 1999, he was a ResearchScientist with Philips Research Laboratories,where he designed sensor systems forinteractive displays and analog front-endsfor optical and magnetic recording systems.

In 1999, he joined Delft University of Technology, where he is currently anprofessor with the Faculty of Electrical Engineering, Computer Science andMathematics. His main research interests are in the design of precision analogcircuitry, sigma-delta modulators and sensor interfaces. His work has resultedin ten U.S. patents and over 70 technical papers.

Prof. Makinwa is on the program committees of several internationalconferences, including the IEEE International Solid-State Circuits Conference(ISSCC) and the International Solid-state Sensors and Actuators Conference(Transducers). He has given plenary talks and tutorials at several conferences,including twice at the ISSCC. He is a co-recipient of JSSC (2005), ISSCC(2008, 2006, 2005), ESSCIRC (2006) and ISCAS (2008) best paper awards.In 2005, he received the Veni Award from the Netherlands Organization forScientific Research and the Simon Stevin Gezel Award from the DutchTechnology Foundation. He is a distinguished lecturer of the IEEESolid-State Circuits Society and a fellow of the Young Academy of the RoyalNetherlands Academy of Arts and Sciences.

165

Johan H. Huijsing was born on May 21,1938. He received the M.Sc. degree inElectrical Engineering from the DelftUniversity of Technology, Delft, theNetherlands in 1969, and the Ph.D. degreefrom this University in 1981 for his thesis onoperational amplifiers.

He has been an assistant and associateprofessor in Electronic Instrumentation atthe Faculty of Electrical Engineering of theDelft University of Technology since 1969,where he became a full professor in the chairof Electronic Instrumentation since 1990,

and professor-emeritus since 2003. From 1982 through 1983 he was a seniorscientist at Philips Research Labs. in Sunnyvale, California, USA. From 1983until 2005 he was a consultant for Philips Semiconductors, Sunnyvale,California, USA and since 1998 also a consultant for Maxim, Sunnyvale,California, USA.

The research work of Johan Huijsing is focused on the systematicanalysis and design of operational amplifiers, analog-to-digital converters andintegrated smart sensors. He is author or co-author of some 250 scientificpapers, 40 patents and 13 books, and co-editor of 13 books. As a professor heguided 27 Ph.D. students toward their degree. He is fellow of IEEE forcontributions to the design and analysis of analog integrated circuits. He wasawarded the title of Simon Stevin Meester for applied Research by the DutchTechnology Foundation.

167

Index 1

Aauto-zero 14–23

auxiliary input stage 17input offset storage 16instrumentation amplifier 76noise 19output offset storage 15

Bbiasing

constant current 141constant transconductance 95PTAT 140PTIM 95

Ccharge injection 15, 17, 18, 27, 29,

31, 32, 33, 34, 35, 36, 37, 40see also residual offset

chopped auto-zero amplifier 29–31chopper 23–29

amplifier 24charge injection 27–29feedback amplifier 26instrumentation amplifier 75noise 25ripple 88ripple reduction 88

chopper layout 158, 159

chopper offset-stabilized chopper amplifier 60, 82

common-mode feedbackinput controlled 111long tailed pair 92, 109, 110resistive 94, 142

continuous-time auto-zerosee also offset-stabilization

auto-zero 48cross talk capacitors in

choppers 27–29current-feedback instrumentation

amplifier 68–74common-mode gain

dependency 129, 146current-sensing 129–133

Ddynamic offset compensation

see auto-zerosee choppersee offset-stabilization

Ffrequency compensation

Miller 94multi-path hybrid-double-nested

Miller 52, 53multi-path hybrid-nested

Index

168

Miller 50, 51, 54, 55, 56, 57, 61, 88, 98, 104, 138

multi-path nested Miller 50nested Miller 55

Ggain-boosting 110

Hhigh-side current-sensing 130

Llow-side current-sensing 130

Mmismatch 4–7

Nnoise

effect of auto-zero on 19–23effect of chopper and auto-zero

offset-stabilization on 59effect of chopper offset

stabilization on 49effect of chopper on 25

noise folding 19–23

Ooffset 3

minimizing 6offset in CMOS amplifiers 3offset-stabilization 45–59

auto-zero 47chopper 48chopper and auto-zero 58chopper with ripple filter 55–58concept 45frequency compensation 50instrumentation amplifier 79–81

iterative 61on-chip coax 160opamp

class-A 94, 142class-AB 92, 108folded cascode 6, 92, 109gain-boosted folded cascode 110

Pping-pong 44–45, 78ping-pong-pang 78–79PTAT current source 140PTIM current source 95

Rresidual offset

due to charge injection 15, 17, 18, 27, 88

due to chopped parasitic 54, 56, 89, 106, 120

due to finite gain 17, 18, 46, 47, 56, 57, 87

due to parasitics 28, 29, 156, 157layout 156–162

ripple reduction 88

Tthreshold voltage mismatch 4, 5transconductance factor

mismatch 4, 5

Documents

Dynamic offset compensated CMOS amplifiers