ECE448 Lecture6 FSM

8/11/2019 ECE448 Lecture6 FSM

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George Mason University

Finite State Machines

State Diagrams,State Tables,

Algorithmic State Machine (ASM) Charts,and VHDL Code

ECE 448

Lecture 6


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Required reading

P. Chu, FPGA Prototyping by VHDL ExamplesCh apt er 5, FSM


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Recommended reading

S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 8 , Sync hro no us Sequ ent ia l Ci rcui t s

Sect io n s 8.1-8.5Sect ion 8 .10, A lgo ri th m ic State Machin e (A SM)

Charts


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Datapathvs.

Controller


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Structure of a Typical Digital System

Datapath(ExecutionUnit)

Controller(ControlUnit)

Data Inputs

Data Outputs

Control & Status Inputs

Control & Status Outputs

ControlSignals

Status

Signals


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Datapath (Execution Unit) Manipulates and processes data Performs arithmetic and logic operations,

shifting/rotating, and other data-processingtasks

Is composed of registers, multiplexers, adders,decoders, comparators, ALUs, gates, etc.

Provides all necessary resources and

interconnects among them to perform specifiedtask Interprets control signals from the Controller

and generates status signals for the Controller


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Controller (Control Unit)

Controls data movement in the Datapath byswitching multiplexers and enabling or disablingresources

Example: enable signals for registersExample: select signals for muxes

Provides signals to activate various processingtasks in the Datapath

Determines the sequence of operationsperformed by the Datapath Follows Some Program or Schedule


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Programmable vs. Non-Programmable Controller

Controller can be programmable or non-programmable Programmable

Has a program counter which points to next instruction Instructions are held in a RAM or ROM

Microprocessor is an example of programmablecontroller Non-Programmable

Once designed, implements the same functionality

Another term is a hardwired state machine, orhardwired FSM, or hardwired instructions

In this course we will be focusing on non-programmable controllers.


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Finite State Machines Controllers can be described as Finite State

Machines (FSMs) Finite State Machines can be represented using

State Diagrams and State Tables - suitable

for simple controllers with a relatively fewinputs and outputs Algorithmic State Machine (ASM) Charts -

suitable for complex controllers with a largenumber of inputs and outputs

All of these descriptions can be easily translatedto the corresponding synthesizable VHDL code


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Labs in This Class

Datapath

(ExecutionUnit)

Controller

(ControlUnit)

Data Inputs

Data Outputs

Control & Status Inputs

Control & Status Outputs

ControlSignals

StatusSignals

Lab 2: Combinational DatapathLab 3: Sequential Datapath

Lab 4: Primarily the Controller

Labs 5-7 will include both Datapath and Controller


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Hardware Design with RTL VHDL

Pseudocode

Datapath Controller

Blockdiagram

Blockdiagram

State diagramor ASM chart

VHDL code VHDL code VHDL code

Interface


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Steps of the Design Process1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface divided into Datapath and Controller6. ASM chart of the Controller

7. RTL VHDL code of the Datapath, Controller, andTop-Level Unit

8. Testbench for the Datapath, Controller, and Top-LevelUnit

9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing using FPGA board

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1. Text description

2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface divided into Datapath and Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, Controller , and

Top-level Unit8. Testbench for the Datapath, Controller, and Top-Level

Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing using FPGA board

Steps of the Design ProcessIntroduced in Class Today

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Finite State MachinesRefresher


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Finite State Machines (FSMs) An FSM is used to model a system that transits

among a finite number of internal states. Thetransitions depend on the current state and externalinput.

The main application of an FSM is to act as thecontroller of a medium to large digital system

Design of FSMs involves Defining states

Defining next state and output functions Optimization / minimization

Manual optimization/minimization is practical forsmall FSMs only


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Moore FSM

Output is a Function of the Present State Only

Present Stateregister

Next Statefunction

Outputfunction

Inputs

Present StateNext State

Outputs

clockreset


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Mealy FSM Output is a Function of the Present State and the

Inputs

Next Statefunction

Outputfunction

Inputs


Outputs

Present Stateregister

clockreset


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State Diagrams


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Moore Machine

state 1 /output 1

state 2 /output 2

transitioncondition 1

transitioncondition 2


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Mealy Machine

state 1 state 2

transition condition 1 /output 1

transition condition 2 /output 2


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Moore FSM - Example 1

Moore FSM that Recognizes Sequence 10

S0 / 0 S1 / 0 S2 / 1

00

0

1

11

reset

Meaningof states:

S0: Noelementsof thesequenceobserved

S1: 1 observed

S2: 10 observed


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Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence 10

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1reset

Meaningof states:

S0: Noelementsof thesequenceobserved

S1: 1 observed


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Moore & Mealy FSMs Example 1

clock

input

Moore

Mealy

0 1 0 0 0

S0 S0 S1 S2 S0 S0

S0 S0 S1 S0 S0 S0

state

output

state

output


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Moore vs. Mealy FSM (1)

Moore and Mealy FSMs Can BeFunctionally Equivalent Equivalent Mealy FSM can be derived from

Moore FSM and vice versa Mealy FSM Has Richer Description and

Usually Requires Smaller Number of States

Smaller circuit area


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Mealy FSM Computes Outputs as soon asInputs Change Mealy FSM responds one clock cycle sooner

than equivalent Moore FSM Moore FSM Has No Combinational Path

Between Inputs and Outputs

Moore FSM is less likely to affect the criticalpath of the entire circuit


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Types of control signal Edge sensitive

E.g., enable signal of counter

Both can be used but Mealy is faster

Level sensitive E.g., write enable signal of SRAM Moore is preferred


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Which Way to Go?

Safer.Less likely to affect

the critical path.

Mealy FSM Moore FSM

Lower Area

Responds one clockcycle earlier

Fewer states


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Finite State Machinesin VHDL


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FSMs in VHDL Finite State Machines Can Be Easily

Described With Processes Synthesis Tools Understand FSM

Description if Certain Rules Are Followed State transitions should be described in a

process sensitive to clock and asynchronousreset signals only

Output function described using rules forcombinational logic, i.e. as concurrentstatements or a process with all inputs in thesensitivity list


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Mealy FSM

Next Statefunction

Outputfunction

Inputs


Outputs

Present StateRegister

clockreset

process(clock, reset)

concurrentstatements


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Moore FSM - Example 1

Moore FSM that Recognizes Sequence 10

S0 / 0 S1 / 0 S2 / 1

0

0

0

1

11

reset


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Moore FSM in VHDL (1)

TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset)BEGIN

IF(reset = 1) THEN Moore_state IF input = 1 THEN

Moore_state


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Moore FSM in VHDL (2)

WHEN S1 =>IF input = 0 THEN

Moore_state


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Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence 10

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1reset


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Mealy FSM in VHDL (1)

TYPE state IS (S0, S1);SIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset)BEGIN

IF(reset = 1) THEN Mealy_state IF input = 1 THEN

Mealy_state


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Mealy FSM in VHDL (2)

WHEN S1 =>IF input = 0 THEN

Mealy_state


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Algorithmic State Machine (ASM)Charts


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Algorithmic State Machine

Algorithmic State Machine representation of a Finite State Machine

suitable for FSMs with a larger number ofinputs and outputs compared to FSMsexpressed using state diagrams and state

tables.


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Elements used in ASM charts (1)

Output signals or actions

(Moore type)

State name

Conditionexpression

0 (False) 1 (True)

Conditional outputs

or actions (Mealy type)

(a) State box (b) Decision box

(c) Conditional output box


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State Box State box represents a state. Equivalent to a node in a state diagram or

a row in a state table. Contains register transfer actions or

output signals

Moore-type outputs are listed inside ofthe box. It is customary to write only the name of

the signal that has to be asserted in thegiven state, e.g., z instead of z


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Decision Box

Decision box indicates that agiven condition is tobe tested and theexit path is to bechosen accordingly.The condition

expression mayinclude one or moreinputs to the FSM.

Conditionexpression

0 (False) 1 (True)


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Conditional Output Box

Conditionaloutput box

Denotes outputsignals that are of

the Mealy type. The condition that

determineswhether suchoutputs aregenerated isspecified in thedecision box.

Conditional outputsor actions (Mealy type)

ASMs representing simple FSMs


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ASMs representing simple FSMs

Algorithmic state machines can model bothMealy and Moore Finite State Machines

They can also model machines that are of

the mixed type


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Moore FSM Example 2: State diagram

C z 1=

Reset

B z 0= A z 0= w 0=

w 1=

w 1=

w 0=

w 0= w 1=


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Present Next state Output state w = 0 w = 1 z

A A B 0B A C 0C A C 1

Moore FSM Example 2: State table


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w

w

w0 1

0

1

0

1

A

B

C

z

Reset

w

w

w0 1

0

1

0

1

A

B

C

z

Reset

ASM Chart for Moore FSM Example 2


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USE ieee.std_logic_1164.all ;

ENTITY simple ISPORT ( clock : IN STD_LOGIC ;

resetn : IN STD_LOGIC ;w : IN STD_LOGIC ;z : OUT STD_LOGIC ) ;

END simple ;

ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;

BEGINPROCESS ( resetn, clock )BEGIN

IF resetn = '0' THENy


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E l 2 VHDL d (3)


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Example 2: VHDL code (3)

END IF ;END PROCESS ;

z


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A

w 0= z 0=

w 1= z 1= Bw 0= z 0=

Reset

w 1= z 0=

Mealy FSM Example 3: State diagram


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ASM Chart for Mealy FSM Example 3

w

w

0 1

0

1

A

B

Reset

z

E l 3 VHDL d (1)


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LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY Mealy ISPORT ( clock : IN STD_LOGIC ;

resetn : IN STD_LOGIC ;w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;END Mealy ;

ARCHITECTURE Behavior OF Mealy ISTYPE State_type IS (A, B) ;SIGNAL y : State_type ;

BEGINPROCESS ( resetn, clock )BEGIN

IF resetn = '0' THENy


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CASE y ISWHEN A =>

IF w = '0' THENy


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END IF ;END PROCESS ;

z


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Control Unit Example: Arbiter (1)

Arbiter

reset

r1

r2

r3

g1

g2

g3

clock



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Idle

000

1--

Reset

gnt1 g1 1=

-1-

gnt2 g2 1=

--1

gnt3 g3 1=

0-- 1--

01--0-

001--0




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r 1r 2

r 1r 2 r 3

Idle

Reset

gnt1 g 1 1=

gnt2 g 2 1=

gnt3 g 3 1=

r 1r 1

r 1

r 2

r 3

r 2

r 3

r 1r 2 r 3

r 1r 2

r 1r 2 r 3

Idle

Reset

gnt1 g 1 1=

gnt2 g 2 1=

gnt3 g 3 1=

r 1r 1

r 1

r 2

r 3

r 2

r 3

r 1r 2 r 3

ASM Ch f C l U i E l 4


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ASM Chart for Control Unit - Example 4

r 1

r 30 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

r 1

r 30 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

E l 4 VHDL d (1)


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LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY arbiter ISPORT ( Clock, Resetn : IN STD_LOGIC ;

r : IN STD_LOGIC_VECTOR(1 TO 3) ;g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

END arbiter ;

ARCHITECTURE Behavior OF arbiter IS

TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;SIGNAL y : State_type ;

E l 4 VHDL d (2)


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Example 4: VHDL code (2)BEGIN

PROCESS ( Resetn, Clock )

BEGINIF Resetn = '0' THEN y


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WHEN gnt3 =>IF r(3) = '1' THEN y


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ASM Summary by Prof. Chu

ASM (algorithmic state machine) chart Flowchart-like diagram Provides the same info as a state diagram More descriptive, better for complex description ASM block

One state box One or more optional decision boxes:

with T (1) or F (0) exit path One or more conditional output boxes:

for Mealy output


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I t ASM Ch t


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Incorrect ASM Charts

Based on RTL Hardware Design by P. Chu

G li d FSM


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Generalized FSM

Based on RTL Hardware Design by P. Chu


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Alternative Coding Stylesby Dr. Chu

(to be used with caution)


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VHDL Description of a FSM

Follow the basic block diagram Code the next-state/output logic according

to the state diagram/ASM chart Use enumerate data type for states

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C bi / l i h


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Combine next-state/output logic together

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Documents

ECE448 Lecture6 FSM