計算システム論第2 （3章） - 東京大学nakamura/section3.pdf3 5 7 Start FSMで記述した制御論理状態1 計算システム論第2 14 Step name Action for R-type

計算システム論第2 1

計算システム論第２（３章）

中村宏

工学部計数工学科情報理工学系研究科システム情報学専攻


MIPS Assembly Language (抜粋) MIPS operands

Name Example Comments$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform

32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero alw ays equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants.Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so

230 memory Memory[4], ..., sequential w ords differ by 4. Memory holds data structures, such as arrays,words Memory[4294967292] and spilled registers, such as those saved on procedure calls.

MIPS assembly languageCategory Instruction Example Meaning Comments

add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constantsload word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to registerstore word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory

Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to registerstore byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memoryload upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100

Equal test; PC-relative branch

Conditional

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100

Not equal test; PC-relative

branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0

Compare less than; for beq, bne

set less than immediate

slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0

Compare less than constant

jump j 2500 go to 10000 Jump to target addressUncondi- jump register jr $ra go to $ra For switch, procedure returntional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call


命令の subset

ADD and SUB • addU rd, rs, rt (unsigned) • subU rd, rs, rt

OR Immediate: • ori rt, rs, imm16

LOAD and STORE Word • lw rt, rs, imm16 • sw rt, rs, imm16

BRANCH: • beq rs, rt, imm16

op rs rt rd shamt funct 0 6 11 16 21 26 31

6 bits 6 bits 5 bits 5 bits 5 bits 5 bits

op rs rt immediate 0 16 21 26 31

6 bits 16 bits 5 bits 5 bits





命令フォーマット


実現すべき動作 • PC (Program Counter) で指定された番地のメモリから命令を取る．

• PC は+4する（分岐命令以外）

op | rs | rt | rd | shamt | funct = MEM[ PC ]

op | rs | rt | Imm16 = MEM[ PC ]

命令実現すべき動作

addU R[rd] <– R[rs] + R[rt]; PC <– PC + 4

subU R[rd] <– R[rs] – R[rt]; PC <– PC + 4

ori R[rt] <– OR(R[rs], zero_ext(Imm16) ); PC <– PC + 4

lw R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4

sw MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4

beq if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

２つの命令フォーマット

addU, subU ori, lw, sw, beq


命令の種類と各ステージにおける処理

制御信号の作り方制御信号は，命令の種類，および現在のステップ（状態）に依存状態遷移機械 (FSM : Finite State Machine) として記述可能

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction forbranches

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) thencomputation, branch/ (IR[15-0]) PC = ALUOutjump completionMemory access or R-typ Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or

Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR


データパスと制御論理

Shift left 2

PCM u x

0

1

RegistersWrite register

Write data

Read data 1

Read data 2

Read register 1

Read register 2

Instruction [15– 11]

M u x

0

1

M u x

0

1

4


Sign extend

3216




Instruction register

ALU control

ALU result

ALUZero

Memory data

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWriteControl

Outputs

Op [5– 0]

Instruction [31-26]


M u x

0

2

Jump address [31-0]Instruction [25– 0] 26 28

Shift left 2

PC [31-28]

1

1 M u x

0

32

M u x

0

1ALUOut

MemoryMemData

Write data

Address


例：状態０










状態０におけるデータの流れ

IorD=0 (Mux: PCMem) MemRead=1 IRwrite=1 PCwrite=1

IR = Memory[PC], PC=PC+4

ALUsrcA=0 (Mux: PCALU) ALUsrcB=01 (Mux: 4ALU) ALUop=00 (ALU : 足し算) PCSource=00 (ALU出力をPCへ)

必要な制御信号

Shift left 2

PCM u x

0

1


Write data

Read data 1

Read data 2

Read register 1

Read register 2


M u x

0

1

M u x

0

1

4


Sign extend

3216





ALU control

ALU result

ALUZero

Memory data

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWriteControl

Outputs

Op [5– 0]

Instruction [31-26]


M u x

0

2


Shift left 2

PC [31-28]

1

1 M u x

0

32

M u x

0

1ALUOut

MemoryMemData

Write data

Address


制御信号の定義


PCWrite PCSource = 10

ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond

PCSource = 01

ALUSrcA =1 ALUSrcB = 00 ALUOp= 10

RegDst = 1 RegWrite

MemtoReg = 0MemWrite IorD = 1

MemRead IorD = 1

ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00

RegDst = 0 RegWrite

MemtoReg =1


MemRead ALUSrcA = 0

IorD = 0 IRWrite

ALUSrcB = 01 ALUOp = 00


Instruction fetchInstruction decode/

register fetch

Jump completion

Branch completionExecution

Memory address computation

Memory access

Memory access R-type completion

Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op

= 'BEQ')

(Op

= 'J

')

(Op = 'SW')

(Op

= 'L

W')

4

01

9862

753

Start

FSMで記述した制御論理状態０


例：状態１










Shift left 2

PCM u x

0

1


Write data

Read data 1

Read data 2

Read register 1

Read register 2


M u x

0

1

M u x

0

1

4


Sign extend

3216





ALU control

ALU result

ALUZero

Memory data

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWriteControl

Outputs

Op [5– 0]

Instruction [31-26]


M u x

0

2


Shift left 2

PC [31-28]

1

1 M u x

0

32

M u x

0

1ALUOut

MemoryMemData

Write data

Address

状態１におけるデータの流れ A = Reg [IR[25-21]] B = Reg [IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2)




PCSource = 01


RegDst = 1 RegWrite


MemRead IorD = 1


RegDst = 0 RegWrite

MemtoReg =1


MemRead ALUSrcA = 0

IorD = 0 IRWrite




register fetch

Jump completion



Memory access


Write-back step


(Op

= 'BEQ')

(Op

= 'J

')

(Op = 'SW')

(Op

= 'L

W')

4

01

9862

753

Start

FSMで記述した制御論理状態１










状態遷移図の作り方

ステップ間の因果関係を状態遷移図で表す

0

1

2

3

4 5

6

7

8


Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

IorD

IRWrite

MemReadMemWrite

PCWritePCWriteCond

MemtoRegPCSource1

ALUOp1

ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0

ALUSrcB1ALUOp0

PCSource0

P C W r i t e

P C W r i t e C o n d

I o r D

M e m t o R e g

P C S o u r c e

A L U O p

A L U S r c B

A L U S r c A

R e g W r i t e

R e g D s t

N S 3

N S 2 N S 1

N S 0

O p 5

O p 4

O p 3

O p 2

O p 1

O p 0

S 3 S 2 S 1 S 0

S t a t e r e g i s t e r

I R W r i t e

M e m R e a d

M e m W r i t e

I n s t r u c t i o n r e g i s t e r o p c o d e f i e l d

O u t p u t s

C o n t r o l l o g i c

I n p u t s

組み合わせ回路

wired logic (布線論理) を用いた制御回路の実現

４ビットで９状態命令内の

opフィールド

組み合わせ論理を PLAで記述

AND平面

OR平面

RegWrite=^S3・S2・^S1・^S0 + ^S3・S2・S1・S0




PCSource = 01


RegDst = 1 RegWrite


MemRead IorD = 1


RegDst = 0 RegWrite

MemtoReg =1


MemRead ALUSrcA = 0

IorD = 0 IRWrite




register fetch

Jump completion



Memory access


Write-back step


(Op

= 'BEQ')

(Op

= 'J

')

(Op = 'SW')

(Op

= 'L

W')

4

01

9862

753

Start

RegWriteは?

状態4(0100)と状態7(0111)

^S3・S2・^S1・^S0 + ^S3・S2・S1・S0


P C W r i t e P C W r i t e C o n d I o r D

M e m t o R e g

P C S o u r c e A L U O p

A L U S r c B A L U S r c A R e g W r i t e

A d d r C t l

O u t p u t s

M i c r o c o d e m e m o r y

I R W r i t e

M e m R e a d

M e m W r i t e

R e g D s t

C o n t r o l u n i t

I n p u t

M i c r o p r o g r a m c o u n t e r

A d d r e s s s e l e c t l o g i c

O p [

5 – 0

]

A d d e r

1

D a t a p a t h


B W r i t e

microprogram による制御論理の実現

O p

A d d e r

1

M u x 3 2 1 0

D i s p a t c h R O M 1 D i s p a t c h R O M 2

0

A d d r C t l

A d d r e s s s e l e c t l o g i c


microprogram counter

microcode memory

マイクロ命令を格納

次に実行すべきマイクロ命令を指定


microprogram による制御論理の実現 Dispatch ROM 1

Op Opcode name Value

000000 R-format 0110

000010 jmp 1001

000100 beq 1000

100011 lw 0010

101011 sw 0010

Dispatch ROM 2

Op Opcode name Value

100011 lw 0011

101011 sw 0101

LabelALU

control SRC1 SRC2Register control Memory

PCWrite control Sequencing

Fetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch

microcode memory に保持されるmicrocode

データパスに与える制御信号次のマイクロ命令を指定

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001


microcodeのフォーマット Field name Value Signals active Comment

Add ALUOp = 00 Cause the ALU to add.ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for

branches.Func code ALUOp = 10 Use the instruction's function code to determine ALU control.

SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.A ALUSrcA = 1 Register A is the first ALU input.B ALUSrcB = 00 Register B is the second ALU input.

SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input.Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input.Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input.Read Read two registers using the rs and rt fields of the IR as the register

numbers and putting the data into registers A and B.Write ALU RegWrite, Write a register using the rd field of the IR as the register number and

Register RegDst = 1, the contents of the ALUOut as the data.control MemtoReg = 0

Write MDR RegWrite, Write a register using the rt field of the IR as the register number andRegDst = 0, the contents of the MDR as the data.MemtoReg = 1

Read PC MemRead, Read memory using the PC as address; write result into IR (and lorD = 0 the MDR).

Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR.lorD = 1

Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as thelorD = 1 data.

ALU PCSource = 00 Write the output of the ALU into the PC.PCWrite

PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contentsPCWriteCond of the register ALUOut.

jump address PCSource = 10, Write the PC with the jump address from the instruction.PCWrite

Seq AddrCtl = 11 Choose the next microinstruction sequentially.Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.

Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.


水平vs.垂直マイクロプログラム Label

ALU control SRC1 SRC2

Register control Memory

PCWrite control Sequencing

Fetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch

2bit 1bit 2bit 3bit 3bit 4bit 2bit

Label U/LALU

control SRC1 SRC2Registercontrol Sequencing

U/L Memory PC Write ControlFetch U Add PC 4 Seq

L Read PC ALU SeqU Add PC Extshft Read Dispatch 1'

Mem1 U Add A Extend Dispatch 2'LW2 L Read ALU Seq

U Write MDR FetchSW2 L Write ALU FetchRformat1 U Func code A B Seq

L Write ALU FetchBEQ1 U Subt A B Seq

L ALU Out-Cond FetchJUMP1 L Jump address Fetch

2bit 1bit 2bit 3bit 2bit 1bit

折りたたんでフィールドを共有する

×命令ステップは僅かプラス２

○マイクロ命令用メモリ量減少

17bit x 10 = 170bit 11bit x 12 = 132bit

Documents

計算システム論第2 （3章） - 東京大学nakamura/section3.pdf3 5 7 Start FSMで記述した 制御論理 状態1 計算システム論第2 14 Step name Action for R-type

計算システム論第2 （3章） - 東京大学nakamura/section3.pdf3 5 7 Start FSMで記述した制御論理状態1 計算システム論第2 14 Step name Action for R-type