EMLAB

1

Chapter 7. Differential and multistage amplifiers

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1. The MOS differential pair

2. Small-signal operation of the MOS differential pair

3. The BJT differential pair

4. Other non-ideal characteristics of the differential amplifier

5. The differential amplifier with active load

6. Multistage amplifiers

Contents

EMLAB

3Introduction

1. Differential pair 는 아날로그 IC 에서 가장 흔하게 쓰이는 블록임 .

2. 초고속 switching 소자인 ECL(emitter-coupled logic) 의 기초가 됨 .

3. 1940 년대 진공관 형태로 발명되었으나 추후 discrete BJT 로 구현됨 .

4. 특히 집적 회로가 발명된 이후 매우 널리 쓰임 .

• Differential pair 의 성능은 두 트랜지스터의 특성이 얼마나 일치하느냐에 달려있음 .

• 여러 부품을 필요로 함 .

Differential 증폭기의 장점

1. Single-ended 회로에 비해 잡음과 간섭에 강함 .

2. Multi-stage 구성 시 by-pass capacitor 나 coupling capacitor 필요 없음 .

EMLAB

4uA741 chip layout

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1. MOS differential pair

Current mirror로 구현

Current mirror (ac-tive load) 로 구현

• Q1, Q2 가 matched transistor 라고 가정

• Saturation 영역에서 동작시킴

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6

LW

kIV

VVVVL

Wk

I

nOV

tGSOVOVn )(,2

1

22

Operation with a common-mode input voltage

Q1, Q2 가 saturation 영역인 경우 VCM 을 바꿔도 출력 전압은 전류에만 의존하므로 변동 없음 .

max,2/)( CMtDDDtGSDS VVIRVVVV 최고 입력 전압 :

최저 입력 전압 : CSSSOVtCMCSSSS

OVtSCMOVtGS

VVVVVVVV

VVVVVVV

min,

(Current source I 의 최소 출력 전압에 의해 결정됨 .)

EMLAB

7Operation with a differential input voltage

21 )(

2

1tGSn V

L

WkI

최고 입력 전압 :

OVtntGS VVL

WkIV 221

OVtOVtSGSid VVVV 221max,

(Q1 전류는 I, Q2 전류는 0 일 때 전압임 .)

최저 입력 전압 : Q1 전류 0, Q2 전류가 I 인 경우임 .

OVidOV VV 22

EMLAB

8Large signal operation)(

2

1)(

2

111

211 tGSnDtGSnD V

L

WkiV

L

Wki

)(2

1)(

2

122

222 tGSnDtGSnD V

L

WkiV

L

Wki

Iii DD 21

idnDD L

Wkii

2

121

221

22121 2

12)( idnDDDDDD L

WkIiiiiii

2

4)(

0)(

212

2121

21212

DDDDDD

DDDD

iiiiiix

iixiix

OV

idid

OVn

ididnD

OV

idid

OVn

ididnD

VV

II

LW

kII

L

Wk

Ii

VV

II

LW

kII

L

Wk

Ii

22

2

22

1

)2/(1

22/

)2/(1

22

)2/(1

22/

)2/(1

22

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9

22

22

2

1

id

OVD

id

OVD

V

IIi

V

IIi

1 차 함수 근사식

EMLAB

102. Small signal operation

1G

2id

CMV

= 2G

2id

CMV

=

2121 ,

2 GGidGG

CMV

2,

2 21id

CMGid

CMG VV

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11

CMV CMV2id

2id

Common mode Differential mode

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12Differential mode equivalent

OVOV

DtGSnm V

I

V

IV

L

Wkg

2)( 2Differential mode half circuit

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13

Q1, Q2 가 matched transistor 이다 . ro 가 매우 클 때 differential mode 전압 이득을 구하라 .

Example 7.2

sm

LD

id

odd Rg

RRA

/1

)2/(||

EMLAB

142.3 differential amplifier with current-source loads

)||( 21 oomid

odd rrgA

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152.4 cascode differential amplifier

7551331 )(,)(),||( oomopoomonoponmid

odd rrgRrrgRRRgA

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162.5 Common-mode gain and CMRR

CMRR : Common mode rejection ratio

EMLAB

17Common mode half circuit

SSm

icm

Rgi

2/1

SS

D

SSm

Dd R

R

Rg

RA

22/1

icmSS

Do R

R 21

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18Effect of mismatch (CMRR)

DRicm

SS

DDoicm

SS

Do R

RR

R

R 2

,2 21

D

D

SS

D

SS

D

icm

oocm R

R

R

R

R

RA

2212

||

||

cm

d

A

ACMRR

CMRR : Common mode rejection ratio

)/(

2

DD

SSm

RR

RgCMRR

RD mismatch

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19

)/(

2

mm

SSm

gg

RgCMRR

gm mismatch

mmmmmm gggggg 2

1,

2

121

222111 )/1()/1( gsmmgs gigi

1

2121 1

m

m

g

giii

SSmmm

SSmicm Rggig

Riigi )(11

)(/ 2111

2111

SSmm

icmm

Rgg

gi

)(1 21

11

icmSSmm

DmDo Rgg

RgRi

)(1 21

111

icmSSmm

Dmo Rgg

Rg )(1 21

22

icmSSm

Dmoood Rg

Rg 2112

SSm

Dmcm Rg

RgA

21

EMLAB

203. BJT differential pair

• Q1, Q2 가 matched transistor• linear active 영역에서 동작시킴

EMLAB

21Basic operation

Different modes of operation of the BJT differential pair: (a) the differential pair with a common-mode input voltage VCM; (b) the differential pair with a “large” differential input signal;

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(c) the differential pair with a large differential input signal of polarity opposite to that in (b); (d) the differ-ential pair with a small differential input signal vi. Note that we have assumed the bias current source I to be ideal (i.e., it has an infinite output resistance) and thus I remains constant with the change in VCM.

4.02

4.0max,

CCCCCM R

IVVV

BECSEECM VVVV min,

Input common mode range

Q1 이 saturation 되는 전압 .

Current source I 가 sat-uration 되는 전압 .

EMLAB

233.3 Large signal operation

TBBTEBTEB V

E

EVSE

VSE e

i

ie

Iie

Ii /)(

2

1/)(2

/)(1

2121 ,

TBBTBB VEE

EV

EE

E

eii

i

eii

i/)(

21

2/)(

21

1

2112 1

1,

1

1

TidTid VEVE ei

ei /2/1 1

1,

1

1

2TV

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The transfer characteristics of the BJT differential pair can be linearized (i.e., the linear range of operation can be extended) by including resistances in the emitters.

Extension of linear range

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253.4 Small signal operation

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A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vid; dc quantities are not shown.

Small signal equivalent

rr

iR e

b

idid 22)1(

Cmid

odd RgA

EMLAB

27Small signal equivalent of DP with emitter resistor

)(2)1( eeid RrR ee

C

ee

Cd Rr

R

Rr

RA

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28Differential half circuit

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29

Single-ended 로 접속해도 REE>>re 이면 앞 페이지와 동일

EMLAB

30Common-mode gain and CMRR

)/(

2

CC

EEm

RR

RgCMRR

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(a) Definition of the input common-mode resistance Ricm. (b) The equivalent com-mon-mode half-circuit.

o

EEC

oCEEicm

rRR

rRRR

1

/1

EMLAB

32Example 7.4Assume β = 100. Evaluate the following:(a) The input differential resistance Rid .(b) The overall differential voltage gain vod/ vsig (neglect the effect of ro).(c) The worst-case common-mode gain if the two collector resistances are accurate to within ±1%.(d) The CMRR, in dB.(e) The input common-mode resistance (assuming that the Early voltage VA = 100 V).

505.0

2521 mA

mV

I

Vrr

E

Tee

kRrR Eeid 40)15050(1012))(1(2 1

]/[40)(2

2VV

Rr

R

RR

R

Ee

C

idsig

id

id

od

]/[1052002

200

)2(4 VV

kRRr

RA

EEEe

Ccm

][98108105

40

||

|| 44

dBA

ACMRR

cm

dm

MRR EEicm 20

EMLAB

334. Other Non-ideal Characteristics of the Differential Amplifier

4.1 Input Offset Voltage of the MOS Differential Pair

21D

DD

RRR

22

DDD

RRR

L

W

L

W

L

W

2

1

1

L

W

L

W

L

W

2

1

2

21t

tt

VVV

22t

tt

VVV

DDDO RI

VVV 212RD mismatch :

(W/L) mismatch :

LW

LWIRIRV DDO /

)/(

2

2211 2

1)(

2

1OVntGSn V

L

WkV

L

WkI

Vt mismatch :

tGS

ttGSn

ttGSn

V

VV

L

Wk

VV

L

WkI

1

21

2

11

1)(2

1

22

1

OV

tDO V

VIRV

2

Output offset voltage

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Application of a voltage equal to the input off-set voltage VOS to the input terminals with op-posite polarity reduces VO to zero.

d

OOS A

VV

D

DOVDmDOS R

RVRgR

IV

2)/(

2

RD mismatch :

(W/L) mismatch :

LW

LWVIRV OV

DOS /

)/(

2

Vt mismatch :

tDmOV

tDOS VRg

V

VIRV

)/(

2

2)(

)(21

)2/(

1

21

OV

tGSn

tGSn

m

V

VL

Wk

VL

Wk

g

I

222

)(/

)/(

22 tOV

D

DOVOS V

LW

LWV

R

RVV

Input offset voltage

EMLAB

354.2 Input offset voltage of the bipolar differential pair

21C

CC

RRR

22

CCC

RRR

SSS III 2

11

SSS III 2

12

22

S

S

C

CTOS I

I

R

RVV

4.3 Input bias and offset currents of the bipolar differential amplifier

1

)2/(21

IIII BBOS

)1(2,

I

III BBOS

EMLAB

365. The Differential Amplifier with Active Load

1. Common-mode gain 이 줄어들어 CMRR 이 증가한다 .2. Differential mode gain 이 2 배 (6 dB) 증가한다 . ( 각 트랜지스터

출력 전압이 크기는 같고 반대 부호임 .)3. Differential mode 신호 전송이 잡음이나 , 간섭 신호에 영향을 덜

받으므로 op-amp 같은 증폭기 IC 에서 첫번째 단계로 differential amp 가 흔하게 사용된다 .

4. 그러나 차동 모드를 지원하지 않고 single-ended 모드를 지원하는 다른 부품으로 연결하는 경우 적절한 변환 장치가 필요하다 .

출력 전압을 differential mode 로 얻을 때 장점

Figure 7.30 A three-stage amplifier consisting of two differential-in, differential-out stages, A1 and A2, and a differential-in, single-ended-out stage A3.

EMLAB

37Non-ideal property – cross-talk

)(tV

SZ

LZ

Voltage

Near end crosstalk voltage

Far end crosstalk voltage

인접한 전선들 사이에 간섭이 생긴다 .

EMLAB

385.1 Differential to Single-Ended Conversion

Figure 7.31 A simple but inefficient approach for differential to single-ended conversion.

출력 신호를 single-ended 로 변환하여 전압 이득이 반으로 감소

EMLAB

395.2 The active-loaded MOS differential pair

(a) The active-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching.

(c) The circuit with a differential input signal applied and ne-glecting the ro of all transistors.

EMLAB

405.3 Differential gain of the active-loaded MOS pair

Output equivalent circuit of the differential amplifier with active-loaded pair for differ-ential input signals.

2||||

1

2 3

133

313

id

m

moo

m

idmg g

grr

gg

idmid

mid

m

mm

idmgmo gg

g

ggggi

222 23

14234

),( 2143 mmmmm ggggg

Trans-conductance Gm :

mm gG

1gs1or

2gs2or

2/id2/id

4or

1

3

||1

om

rg

11 gsmg 22 gsmg

oi3g 34 gmg

0

0

Q4 의 전류는 Q3 의 υgs 에 의해 정해짐 .

EMLAB

41Output resistance Ro :

24

,2,o

x

o

xx

x

xo R

ir

iii

R

)1( omSoo rgRrR

om

L

mom

Loin rg

R

grg

RrR

1

1

1

111

3

111

11

1/11

1 mom

m

mom

Loin grg

g

grg

RrR

2221

222122 2)1(1

)1( oomm

oominoo rrgg

rrgRrR

)1,( 2221 ommmm rgggg

42

4242

||11

12 oo

ooo

x

o

x

xo rr

rrrR

R

Differential gain :

)||( 42 oomomid

od rrgRGA

EMLAB

425.4 Common-Mode Gain and CMRR

icmmoSS

oSSicms grR

rR

)/1()||2(

)||2(

11

1

SSicm

omcm

SS

icmo R

iG

Ri

2

1

2

)1(2 1111 omSSoo rgRrR

)1(2 2222 omSSoo rgRrR

13

33 ||||

1oo

micmmcmg Rr

gG

133

4

34344

||||1

oom

icmmcmm

gmgsm

Rrg

Gg

ggi

042

4 o

o

o

oicmmcm rR

iG

13

34

24 ||||1

12

||oo

mm

SS

ooicmo Rr

gg

R

Rr

EMLAB

43

SSmomSS

o

icm

ocm RgrgR

rA

333

4

2

1

1

1

2

))((]2)][||([||

||342 SSmomSSmoom

cm

d RgrgRgrrgA

ACMRR

EMLAB

445.5 The bipolar differential pair with active load

2||||||

2 31413313id

emooeid

mb rgrrrrg

2314444id

emmbmc rgggi )( 43 bb

idmid

emmid

mbmid

mo grgggggi

222 3142442

)( 421 mmmm gggg

221222 2)]||(1[ oemoo rrrgrR 42 || ooo rrR

24

,2,o

x

o

xx

x

xo R

ir

iii

R

mm gG

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45

)||( 42 oomomid

od rrgRGA

Differential gain :

rRid 2

Common-Mode Gain and CMRR:EE

icm

Rii

221

433

313 ||||||

1 rrr

gi o

mb

02344

igr bmo

o

EE

o

om

o

EE

o

om

mEE

ocm

R

r

rrrg

rrrR

r

rrrg

gR

rA

3

4

343

3434

4333

44

111

111

2

1||||||1

2

EEmo

EEoom

cm

d Rgr

Rrrg

A

ACMRR 3

4

342 2

1)]||([

||

||

EMLAB

46Systematic Input Offset Voltage

PP

II

I

I

2

1

2/2

1

14

3

4

P

P

P

P

IIIIi

21

/2

221

2/

2

P

T

T

P

mOS

V

VI

I

G

iV

2/

/

Current mirror 의 base current 로 전류 오차 있음 .

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47

Figure 7.40 An active-loaded bipolar differential amplifier employing a folded cascode stage (Q3 and Q4) and a Wilson current-mirror load (Q5, Q6, and Q7).

2|| 5

544o

oo

rrR

2|| 5

544o

omd

rrgA

Output resistance 를 증가시키기 위해 cascode

전류 오차에 의한 offset 을 줄이기 위해 Wilson current-mirror

EMLAB

486 Multistage amplifiers

1. 실제 트랜지스터 증폭기는 여러 단으로 구성됨

2. 1 단은 전압 이득 및 높은 입력 저항 제공으로 신호원의 내부 저항에 의한 전압 감쇄를 억제함 . Differential amplifier 인 경우 common mode rejection 기능도 제공해야 함 .

3. 중간 단계는 높은 전압 이득 제공 기능 . 경우에 따라 differential mode 를 single-ended mode 로 변환하는 기능을 제공하기도 함 . DC 전압 레벨을 바꾸어 ± 전압 스윙이 가능하도록 하는 기능 제공 .

4. 마지막 단계는 부하 저항이 작은 경우 전압 강하를 피하기 위해 낮은 출력 임피던스를 제공 . 대전류 공급 기능 제공 .

EMLAB

496.1 Example : a two-stage CMOS Op amp

1st stage 2nd stage

)||( 4211 oom rrgA )||( 7662 oom rrgA

EMLAB

50Input offset voltage 를 없애는 조건

ADStGSnD VVL

Wki /1

2

1 2

IL

WL

WI

L

W

L

WIII

577

7575 ::)(

2::)2/(

466

6464

IL

WL

WI

L

W

L

WIII

76 II

Common mode 입력 전압에 대해 출력 전압이 0 이 되어야 함 .

Offset 전압이 0 이 되려면 :

5746 21

LW

LW

LW

LW

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51

DC bias circuit :

• 전원 전압 변화와 MOSFET 의 Vt 와 상관없이 바이어스 전류를 공급

• 트랜지스터의 gm 들이 저항 1 개와 트랜지스터 크기에 의해 정해짐

A Bias circuit that stabilizes gm

12

122

1212 )/(

2

2

1

LWC

IVVVV

L

WCI

oxn

BtGStGSoxnB

13

132

1313 )/(

2

2

1

LWC

IVVVV

L

WCI

oxn

BtGStGSoxnB

BBGSGS RIVV 1213

BBoxn

B

oxn

B RILWC

I

LWC

I

1213 )/(

2

)/(

2

2

13

122

12

1)/(

)/(

)/(

2

LW

LW

RLWCI

BoxnB

1

)/(

)/(

)/(2

2

13

12

12 LW

LW

ILWCR

Boxn

B

12mg

1

)/(

)/(2

13

1212 LW

LW

Rg

Bm

1312, )/(

)/()/(

LWI

LWIggLWIg

B

iDimimDm

EMLAB

526.2 Example : a bipolar Op amp

Figure 7.43 A four-stage bipolar op amp.

1. Differential amp

2. Differential amp (differential in, single ended out)

3. Amp, level shifting

4. Voltage buffer

EMLAB

53Example 7.6 : a bipolar Op amp

EMLAB

54Example 7.7

Use the dc bias quantities evaluated in Example 7.6 to analyze the circuit in Fig. 7.43, to determine the input resistance, the voltage gain, and the output resistance.

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55

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56