EMT 351EMT 351DIGITAL IC DESIGNDIGITAL IC DESIGN

En. Rizalafande Che Ismail En. Rizalafande Che Ismail (Course Co-ordinator)(Course Co-ordinator)

Pn. Siti Zarina Md NaziriPn. Siti Zarina Md Naziri

School of Microelectronic EngineeringSchool of Microelectronic Engineering

PENGUMUMANPENGUMUMAN

Pelajar yang telah pergi InDex pada 8-10 Pelajar yang telah pergi InDex pada 8-10 Mei yang lalu Mei yang lalu WAJIB WAJIB pergi ke lawatan pergi ke lawatan

industri pada 12 July 2006 (Rabu).industri pada 12 July 2006 (Rabu).

Maklumat lanjut sila rujuk di papan Maklumat lanjut sila rujuk di papan kenyataan kolej kediaman atau hubungi kenyataan kolej kediaman atau hubungi

En. Muammar ext 8366.En. Muammar ext 8366.

OUTLINEOUTLINE

Introduction to the subject EMT 351Introduction to the subject EMT 351 Introduction to the VLSI system designIntroduction to the VLSI system design

VLSI design methodology and CAD/EDA VLSI design methodology and CAD/EDA toolstools

Hardware description language (HDL)Hardware description language (HDL)

INTROINTRO

Teaching Plan Teaching Plan

Previous Semester …Previous Semester …

This Semester …This Semester …

OUTLINEOUTLINE

Introduction to the subject EMT 351Introduction to the subject EMT 351 Introduction to the Digital IC designIntroduction to the Digital IC design

Digital IC design methodology and Digital IC design methodology and CAD/EDA toolsCAD/EDA tools

Hardware description language (HDL)Hardware description language (HDL)

Today’s VLSI : System-on-Chip (SoC)Today’s VLSI : System-on-Chip (SoC)

Bidirectional Devices

System-on-ChipInput

Devices Output

Devices I/F

I/F

I/F

microphone camera sensor keypad mouse joystick switch

peripheral bus (IEEE1394, USB, RS232C, PCI, SCSI, AGP, ISA, ATA, …)

storage (SRAM, DRAM, FLASH-ROM, disk drive) network (Modem, Ethernet, wireless)

speaker LCD/CRT display LED light motor

SoC – A simplified (logical) viewSoC – A simplified (logical) view

On-chip memory

On-chip memory

On-chip memory

Interconnect network (busses, crossbar switches, wires)

I/F

Output Devices

Bidirectional Devices

Input Devices

On-chip memory

On-chip memory

Register file On-chip

memory

On-chip memory

Functional blocks On-chip

memory

On-chip memory

Controller

I/F I/F

Algorithm-Level Behavioral Description

Register-Transfer Level Structural Description

Logic/Transistor Circuit Description

VLSI Mask Layout

Logic Synthesis

Layout Synthesis

（ High-Level Synthesis ）

System Specification

（ System-Level Synthesis ）

Layout Verification

Logic Verification

Behavioral Verification

System Verification

Systematic Systematic Digital IC Design FlowDigital IC Design Flow

System SpecificationSystem Specification

System Specification System functionality (application) Operating environment (IO interface) Cost (development, manufacture, test) Size/weight (# of chips, board area, box size) Power consumption Flexibility (specification changes, added functionality)

Human language (English, Japanese, Thai, etc.)

System Synthesis/VerificationSystem Synthesis/Verification

Algorithm Description

System Specification

Software languages (C/C++, Java) Hardware languages (Verilog, VHDL)

Functional Simulation(SW/HW co-simulation)

Data : types/widths, structures, arrays Process : expressions, control-flow, procedures, functions Communication : protocols Simulation : input stimulus, output verification

manual translation

Human language

High-Level High-Level Synthesis/VerificationSynthesis/Verification

Algorithm Description Software languages (C/C++, Java) Hardware languages (Verilog, VHDL)

Functional Simulation

RTL Structural Description Verilog, VHDL

Architecture description Module (CPU, memory, register, functional unit, IO interface) Bus architecture

Module description (functional/structural) Combinational/sequential circuit description

manual translation (High-Level Synthesis ）

Logic Synthesis/VerificationLogic Synthesis/Verification

Logic Verification Timing Verification Power analysis

RTL Structural Description

Logic/Transistor Circuit Description Verilog, VHDL Schematic Netlist

Verilog, VHDL

Logic Minimization Technology Mapping

Cell components (gates, registers, transistors) Nets IO pins

Layout Synthesis/VerificationLayout Synthesis/Verification

Circuit topology verification Design rule check Timing Verification

Logic / Transistor Circuit Netlist Verilog, VHDL Schematic Netlist

VLSI Mask Layout Mask Pattern

Cell / module layout (manual or auto) Place and Route

Layers (well, diffusion, polysilicon, metals, vias) Rectangle, polygons

CAD/EDA ToolsCAD/EDA Tools

Electronic design automationElectronic design automation ( (EDAEDA) is ) is the category of tools for designing and the category of tools for designing and

producing electronic systems ranging from producing electronic systems ranging from printed circuit boardsprinted circuit boards (PCBs) to (PCBs) to

integrated circuitsintegrated circuits. This is sometimes . This is sometimes referred to as ECAD (electronic referred to as ECAD (electronic

computer-aided designcomputer-aided design) or just CAD. ) or just CAD.

Cont..Cont..

OUTLINEOUTLINE

Introduction to the subject EMT 351Introduction to the subject EMT 351 Introduction to the Digital IC designIntroduction to the Digital IC design

Digital IC design methodology and Digital IC design methodology and CAD/EDA toolsCAD/EDA tools

Hardware description language (HDL)Hardware description language (HDL)

What is HDL ?What is HDL ?

HDL – Hardware Description LanguageHDL – Hardware Description Language Used to describe the logic functionality of a Used to describe the logic functionality of a

circuitcircuit Can also describe the behavioral aspects of a Can also describe the behavioral aspects of a

circuit functioncircuit function Sometimes used to show the netlist of a Sometimes used to show the netlist of a

circuitcircuit

Cont..Cont..

Two types of HDLTwo types of HDL VerilogVerilog VHDL (VHSIC HDL – Very High Speed Integrated VHDL (VHSIC HDL – Very High Speed Integrated

Circuit Hardware Description Language)Circuit Hardware Description Language)

Latest type of HDL languageLatest type of HDL language C/C++ code – not widely acceptedC/C++ code – not widely accepted Superlog – very new. Mostly still under researchSuperlog – very new. Mostly still under research

VHDL vs VerilogVHDL vs Verilog

Always an argument on which is a better form of HDL.

Both has its advantages and disadvantages.

Cont..Cont..

Verilog :Easy to write.Easy to read & understand as it is similar to C.Easier to learn compared to VHDLAll design centres in Malaysia uses Verilog.

Cont..Cont..

VHDL : It is more complicated & more difficult to learn

compared to Verilog.More coding rules to follow.More flexible compared to VerilogCan reflect real design more efficiently.

Cont..Cont..

Whichever is more suitable to be used as the standard HDL depends largely on individual designer.

Most EDA/CAD design tools in the market can handle both Verilog & VHDL

That’s all for today. See u on Friday..That’s all for today. See u on Friday..