Network of Excellence on High Performance Embedded Architectures and Compilers

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Message from the HiPEAC coordinator

Message from the project officer

Steering Committee News

HiPEAC 2007 Conference

ACACES 2006 Summerschool

The HiPEAC cluster on whole-systemoptimization announces a PLDI 2006tutorial

News from the commission

HiPEAC Event: GCC tutorial

Industrial Vision

PhD Internships

Upcoming events

www.hipeac.net

appears quarterly | April 2006

Summer School

ACACES 2006

L'AquilaJuly 23-29

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HiPEAC Conference submission deadline: June 2, 2006

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Message from the HiPEAC coordinator

Microelectronics presentation, the first ofa series, has already been scheduled forthe spring cluster meeting of May 2006.

HiPEAC has closed its third call forresearch clusters and publication propos-als. Twenty five proposals for clusters andpublication funds were received; seven-teen were accepted, granting a total ofaround 400.000 €, of which 150.000 €was devoted to fellowships. During thepresent quarter, HiPEAC will open a firstcall for internships, with a budget of80.000 €. Our aim is to allow ourHiPEAC PhD students to start to collabo-rate with an industrial member.Members from industry will set up the listof topics that should be addressed by

As you know, HiPEAC joint research isimplemented through our research clus-ters, which are open to new participants.HiPEAC members can organize them-selves as they like within each researchclusters. Some research cluster meetingswill have a different format in the future,with a public part in which cluster activi-ties will be presented to interested partic-ipants who may join afterwards. Thepublic part will be complemented withprivate technical meetings. Someresearch clusters plan to organize coursesin the coming months. HiPEAC willfinance trips of members to attend thesepublic cluster meetings and to contactother researchers, encouraging integra-tion and joint activities in this way.

In January 2006, research clusters met inDelft, The Netherlands, for one and a halfdays. Since last year, more research clus-ters have started their activities or havebeen created. Therefore, more time willbe allowed for future cluster meetings.

Let me remind you that one of theHiPEAC objectives is the collaboration ofthe academy and industry. To this end,HiPEAC plans to hold its next group ofcluster meetings at the site of one of theindustrial members, in order to ease theattendance and participation of industrymembers. Cluster meetings will be com-plemented with speeches by industrialHiPEAC members, in which they willpresent their research interests. The ST

Dear colleagues,

The European Commission has approved our new, revised HiPEAC programme of activ-ities for this year. We learn from experience and aim at our common success; keep onreading to learn how this will be achieved.

Mateo ValeroCoordinatorUPC Barcelonamateo@ac.upc.edu

Message from the project officerIST 2006: Strategies for Leadership

This year's IST event will be held inHelsinki from the 22nd to the 24th ofNovember 2006. The event, which isorganized by the European Commissionwithin the framework of the Finnish EUPresidency, focuses on European poli-cies and research priorities forInformation Society Techno-logies.This year the event has twomain goals: Because the 7th FrameworkProgramme (2007-2013) willbe launched at around the

same time, IST 2006 will present theresearch topics selected in its first WorkProgramme, explain the new rules andprocedures for applying for funding andhelp create partnerships for submittingproposals.The second goal is to bring key policy-makers together from across Europe to

discuss a holistic policyapproach to EuropeanICT research. The aim isto create virtuous cyclesbetween ICT research,economic growth andquality of life, so theevent will explore,

amongst other topics, transnationalresearch and innovation programmes,public-private partnerships, internation-al cooperation, innovation eco-systemsand regional R&D clusters.The event is organised into threemain parts:The exhibition will present the latest ICTR&D results from across Europe. A callfor exhibits will be published on theWeb shortly. Exhibits should target thenon-specialist, contain strong visualaspects and, if possible, allow hands-onexperience for visitors. Exhibits will beassessed on the basis of these and othercriteria given in the application form.

Mercè Griera-I-Fisa (Merce.Griera-i-Fisa@cec.eu.int)

We expect to select about 100 exhibitscovering the complete spectrum of ourresearch activities.The Networking Sessions andWorkshops provide an open forum forexchanging views and ideas.Networking Sessions provide a meetingplace for communities that have possi-bly never worked together before.Workshops present the state-of-the-artin a domain and provide a platform forknowledge exchange and learning.They are selected from proposals sub-mitted by the research communitiesand other stakeholders, through a Callfor Proposals which will soon be pub-

lished on the Web.

The conference programme is decidedupon by the organising committee. Itwill have high level plenary sessionswhere recognised personalities fromindustry, academia and politics willdebate what governments and publicpolicy can do to create an innovativeEurope. The programme will alsoinclude parallel sessions on the researchcontent for the various parts of the ICTWork Programme arranged in a waythat vertical threads will be formed cor-responding to particular industrial sec-tors or technology areas. This will be

complemented by sessions on how tosubmit an FP7 proposal, that is, on rulesand procedures.

Up to date information will be available at:http://europa.eu.int/information_socie-ty/activities/istevent/index_en.htm

I would like to encourage the HiPEACcommunity to be proactive in both thenetworking and exhibition parts. Iwould be very happy if, in addition tothe excellent research you are doing,you were able to present it at the IST2006 event.

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applicants. I am sure you will want totake advantage of this opportunity whenit is announced on our website and in thisnewsletter, along with the rest of ouractivities.

The winter HiPEAC Conference will takeplace in January, 2007. Located in Ghent,Belgium, the Conference will have a new,prestigious Programme Committee. Forthe new edition, we hope to achievegreater participation. Five selected articlesfrom the first HiPEAC Conference will bepublished in the first issue of HiPEACJournal, which is about to appear. TheHiPEAC Journal call for papers hasalready started. The journal will have fourissues per year, about half of them focus-ing on specific themes or topic areas (ourspecial issues) and one of them beingdevoted to the HiPEAC roadmap. Thejournal will be published by SpringerVerlag in their LNCS series. Each issue willbe published immediately on the HiPEACweb site and via Springer’s digital library.It will also be available as a hard copy.

ACACES’2006, the HiPEAC SummerSchool, announces its new program in

this newsletter. The school will again beheld in L’Aquila, Italy, in July 2006. As lastyear, courses will be taught by topresearchers. The schedule will be adaptedto allow more time for interaction amongstudents and professors. We aim to fur-ther improve upon the success of lastyear's ACACES, so, I recommend you re-gister early if you do not want to miss it!

As both HiPEAC coordinator and part ofthe community, it is a great satisfactionfor me to see how the HiPEAC communi-ty is coming together, which will surelylead us to more impressive results. I inviteall HiPEAC members to be an active partof it; as a matter of fact, you cannotafford to be left out!

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Steering committee

HiPEAC Activity

Accepted clusters:Cluster title Total

Adaptable Computers for Embedded Applications 2 € 30000

Advanced Hardware Cache Monitors and Their Application to Reconfigurable Cache Architectures € 4000

Automatic Parallelization for Embedded Parallel Architectures € 16000

Combined Hardware/Software Approach to Coherence for Embedded Chip Multiprocessors € 7300

Embedded Tiled Architectures € 10000

Fellowship for S. Kavvadias (interprocessor communication mechanisms) € 18000

Investigation of real-time capable embedded SMT processor techniques € 48900

Kilo-instruction Multiprocessors € 50000

Machine Learning Techniques for Adaptive Optimization € 26500

Managing Caches for SMT and CMP (correct submission 2) € 16000

NSF (Rutgers) - HiPEAC Collaboration on Cooperative Embedded Computing € 16800

Paper presentation at HPCA (Austin, Texas) € 1910

Reconfigurable Computing € 25000

Scalable System Architectures (#3) € 30000

Simulation and Compilation Platforms Cluster € 67600

Value-driven Embedded Processors € 26400

Whole System Optimization € 46800

• Cluster evaluation: 25 proposals received, 17 accepted, almost 400.000 euros devoted, of which 150.000 for fellowships.

• There will be a call for internships, deadline April the 1st. Industry will

provide a list of topics of interest.• Cluster meetings:

- May 11-12, 2006 at ST, Grenoble, France.

- July 23-29, 2006, at ACACES 2006, L’Aquila, Italy.

- October 2006, at Philips Eindhoven, The Netherlands.

• ACACES 2006 Program approved.• HiPEAC 2007 Conference chairs

approved.

Please note that the format of this work-shop is peculiar (abstract submission,selection by industrial researchers only,on-going and published works welcome)because the main purpose is to makeEuropean industry (one company at atime, STMicroelectronics this time) awareof research activities in Europe on topicsof interest to them.

The workshop will take place at a loca-tion close to the main STMicroelectronicsfacilities in Grenoble.

TOPICS OF INTEREST FOR STMICRO-ELECTRONICS. The convergence of computing with con-sumer electronics poses formidable chal-

lenges to Systems on Chip architects andprogrammers, coming from a wholerange of extremely demanding factors,such as the need to provide very highquality rendering of media content, high-speed connectivity, security, flexibility andprogrammability at very low power con-sumption and very low cost. As an exam-ple, a typical chip for next generationmobile multimedia connected deviceswill deliver several GOPS of general-pur-pose processing power, hundred's ofGOPS on the media processing side withreal time constraints, it will consume lessthan a watt and it will cost less than 10$.

In trying to meet all these requirements,SoC architects need to find the right bal-

ance between general purpose and appli-cation-specific processors, H/W accelera-tion, interconnect and memory hierar-chies. The result is always a compromisebetween programmability and efficiencyrequirements.

In the past, the requirements for pro-grammability were less demanding,because the complexity of the media partcould be handled by the platformproviders alone. However this is rapidlychanging as the functionality of themedia part keeps growing, and increas-ingly important because it evolves duringthe lifetime of a single platform. Forthese reasons, system-wide programma-bility requirements are growing to a large

The 1st HiPEAC Industrial Workshop on EmbeddedComputing - STMicroelectronics - Grenoble, May 11

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extent, both for the platform providers aswell as for the external programmers.

The difficulty is to drastically improve pro-grammability without compromising thestringent area/cost/power constraintsimposed by the embedded domain, verymuch a strategic issue and limiting factorin industry today. Classical computingarchitectures and programming models,such as shared or distributed memoryand associated tools, don't fit well withthe current and envisioned platforms.

New models, architectures and toolsmust be investigated to address thisurgent industrial demand.The purpose of the workshop is to stimu-late innovative contributions in the areaof embedded computing, with a clearemphasis on cost/efficiency-aware tech-niques for the design and programmingof next generation consumer electronicsdevices. Topics of interest include, butare not limited to:• Cost effective on-chip multi-processor

architectures

• Programming models and tools for heterogeneous multi-processors

• Efficient system-wide memory hierarchy organizations

• Fine and coarse-grain reconfigurable architectures and tools

• Streaming processing architectures and tools

• Advanced compilation techniques for media processors

• Operating systems for distributed on-chip heterogeneous multi-processors

• Virtual machines and JIT compilers for embedded processors

CONTACT: Marcelo Cintra, Universityof Edinburgh, UK (mc@inf.ed.ac.uk) ■

HiPEAC Activity

We are happy to announce HiPEAC’07,the second International Conference onHigh Performance EmbeddedArchitectures & Compilers. The confer-ence will provide a high quality forumfor computer architects and compilerbuilders working in the field of highperformance computer architecture andcompilation for embedded systems. Theconference aims to achieve the dissem-ination of advanced scientific knowl-edge and the promotion of internation-al contacts among scientists from aca-demia and industry.

The second HiPEAC conference will beheld in Ghent, Belgium. The call forpapers and the list of important datesare on the conference website:http://www.hipeac.net/hipeac2007. Last year we accepted 18 out of 84papers resulting in a very high qualitytechnical programme. The proceedings

are published by Springer, and areindexed in the ISI Web of Knowledge.We encourage everybody, and HiPEACmembers in particular, to submit theirbest papers to the conference in orderto establish the conference as a highquality event. If we further succeed inmaking the HiPEAC conference one ofthe top conferences in the high per-formance embedded architecture andcompilers area, it will become a focalpoint for the network members andcontribute significantly towards durableintegration.

New this year is that we will also organ-ize an extra set of satellite eventsaround the conference. There will beseveral workshops, and also a generalcluster meeting. This will make the con-ference week one of the major net-working events for the HiPEAC commu-nity and beyond.

General Chairs• Koen De Bosschere, Ghent University,

Belgium• David Kaeli, Northeastern University, USAProgram Committee Chairs• Per Stenstrom, Chalmers University of

Technology, Sweden • David Whalley, Florida State University, USAWorkshop Chair• Lieven Eeckhout, Ghent University, Belgium Publication Chair• Theo Ungerer, University of Augsburg,

GermanyPublicity Chair• Nacho Navarro, UPC, Barcelona, SpainFinancial Chair• Wouter De Raeve, Ghent University, Belgium Web Chair• Thomas Van Parys, Ghent University, Belgium

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HiPEAC ‘07 conferenceJanuary, 2007, Ghent, Belgium

HiPEAC Activity

July 23-29, 2006, L'Aquila, Italy

After the very successful ACACES 2005Summer School, we are proud toannounce the second HiPEAC SummerSchool, which will again take place dur-ing the last week of July in L’Aquila, asmall town about 100 km northeast ofRome at the Telecom Italia LearningServices Campus. A distinguishing feature of this SummerSchool is its broad scope ranging fromlow level technological issues toadvanced compilation techniques. Inthe design of modern computer sys-tems one has to be knowledgeable

about architecture as well as about thequality of code and how to improve it.This summer school offers the ideal mixof the two worlds – both at the entrylevel and at the most advanced level.The summer school is open to every-body, but previous training and/or expe-rience in computer science as well as astrong background in computer archi-tecture or compilation is recommended. The steering committee has succeededin setting up a truly remarkable pro-gram. We start on Sunday evening withan opening ceremony. On Monday, the12 courses start, spread over two morn-ing slots and two afternoon slots. Per

slot there are three parallel courses ofwhich you can take one. The courseshave been allocated to slots in such away that it will be possible to create asummer school program that matchesyour research interests. The topics ofthis year's Summer School will be pre-sented by the following world-classexperts.

On Monday evening there will be aninvited talk by John Cornish, VP of ARM,on "The future of Low Power ProcessorDesign".On Wednesday afternoon we haveorganised a poster session where the par-ticipants can present their own work tothe other participants in order to fosterinteraction and future collaboration.On Friday evening there is a farewelldinner and party.

Students and lecturers will be accommo-dated in hotel-standard private rooms oncampus, where they will stay for oneweek. This will provide plenty of oppor-tunity to have discussions with theteachers and with the other participants

in the relaxing surroundings of theTelecom Italia Learning Facilities Campus.Long after-the-lecture discussions at thebar or the pool table are one of the majorassets of this summer school. At the endof the event you will receive a certificateof attendance detailing the courses youtook.

You can arrange to be picked up in Romeon Sunday July 23, 2006 and to be takenback on Saturday July 29, 2006 to eitherRome airport or downtown Rome (forthose who want to spend some extratime in the eternal city). We will take careof everything during the full week foronly 990 euro, a very reasonable price foran event of this quality.

Unfortunately, the number of partipi-cants will be limited. Therefore, we havean admissions procedure to guarantee afair distribution of the available placesamong all qualified applicants from thevarious countries and institutions. Incases of conflict, preference will be givento the participants who filed their appli-cation earlier, so don’t wait too long to fillin your form. If you are a student of aHiPEAC institution you can ask for agrant that covers the registration fee.

We look forward to seeing you there!

Koen De BosschereSummer school organizer

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ACACES 2006: Second International summer schoolon advanced computer architecture and compilationfor embedded systems

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Lecturer Course title

Albert Cohen, INRIA Futurs, France Compiler Optimizations Research in GCCErik Hagersten, Uppsala University, Sweden Exploring CMP thread-level parallelism: the architecture and the usageMark Hill, University of Wisconsin-Madison, USA Tread-Level Parallelism and Transactional MemoryMichael Hind, IBM T.J. Watson, USA Dynamic Compilation and Adaptive Optimization in Virtual MachinesWen-mei Hwu, University of Illinois at Urbana-Champaign, USA Compiler Techniques for Multi-core Computing and High-level SynthesisRuby Lee, Princeton University, USA Security Concepts for Computer ArchitectsRainer Leupers, RWTH Aachen University, Germany Design of Application Specific Processor ArchitecturesMargaret Martonosi, Princeton University, USA and Power-Efficient Computing: Modeling and OptimizationStefanos Kaxiras, University of Patras, GreeceDavid Padua, University of Illinois at Urbana-Champaign, USA Program OptimizationYale Patt, The University of Texas at Austin, USA Advanced MicroarchitectureTimothy Pinkston, University of Southern California, USA Multicore & Multiprocessor Interconnection NetworksDavid Whalley, Florida State University, USA Compiling for Embedded Design Constraints

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The new initiative on AdvancedComputing Architectures supported byFuture and Emerging Technologiesstarted off with the launch of threeIntegrated Projects on 1 January 2006:AETHER, SARC and SHAPES.

The vision of this initiative is to researchadvanced computing architectures(ACA) that increase the performance ofcomputing engines by two orders ofmagnitude above the increases expect-ed from shrinking CMOS technologyaccording to Moore's law. Substantialreductions in power consumption alsoneed to be reached, to match therequirements of future computing, stor-age and communication systems in a

10+ year time frame.

SARC will improve the scalability of sys-tems designs, by developing a scalablearchitecture and scalable and re-tar-getable compilers. It will provide a 10-fold reduction in design time, reductionof power consumption, and improvedusability of architectures.

SHAPES addresses future multimediaapplication requirements for low-ener-gy, low-cost, high-performance digitalsignal processors (DSPs). It proposes amulti-tile structure connected through apacket-switching network, with a sim-ple and efficient programming environ-ment. It targets multi-Teraops single-

board computers and multi-Petaopssystems

AETHER will research self-adaptation inprocessor architectures, operating envi-ronments, programming and systemscomposition, while controlling concur-rency and power dissipation. Thesearchitectures will correspond to applica-tion requirements in networked perva-sive computing applications, where amajority of future application deploy-ments is expected.

Patrick Van Hove(Patrick.Van-Hove@cec.eu.int)

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News from the commission

Ottawa, June 11, 2006

This tutorial will introduce attendees tothe current state of the art in binary pro-gram rewriting. Applications of staticbinary rewriting such as compaction,optimization, customization, instrumen-tation, obfuscation, support for dynamicrewriting, etc. will be presented, as wellas pitfalls and reliability concerns. The useof the retargetable, extensible and reli-able binary rewriting framework Diabloto support these applications and to facil-

itate experimentation will be discussedextensively. This discussion will includemore abstract design aspects of Diablo,as well as more concrete data structures,algorithms and methods implemented inDiablo.The tutorial consist of four parts:

First we will introduce the field of stat-ic binary program rewriting, and theplace of Diablo in this field as a retar-getable, extensible and reliable frame-work for static binary rewriting. In the second part, a number of

important data structures in Diablowill be discussed. Rather than simplyiterating over a number of data struc-tures, this part will emphasize the roleof the data structures in the design ofDiablo-like tools that want to offerretargetability, extensibility and relia-bility. In the third part, existing control flowanalyses, data flow analyses and pro-gram transformations in Diablo arepresented. In this part, we will alsodemonstrate how the static rewriterDiablo supports dynamic analyses andrewriting applications such as pro-gram instrumentation and the inser-tion of self-modifying code for pro-gram obfuscation. Finally, this part willintroduce Lancet, a graphical interfaceimplemented on top of Diablo thatfacilitates both the evaluation of newanalyses and transformations, and thedebugging of prototype implementa-tions thereof. In the final part, the retargeting ofDiablo to new architectures and otherfile-formats will be discussed.

http://www.cs.umd.edu/~jfoster/pldi06tut.html■

BioBjorn De Sutter obtained his PhD in Computer Science fromGhent University in 2002 on the subject of link-time programcompaction. Since then he has been working at that universityon the more broad subject of binary program rewriting.Applications for which methods and tools were developedinclude software compaction, Linux kernel customization, pro-gram instrumentation, and program obfuscation. Furthermore,he has worked on the subject of Java whole-program opti-mization in the IBM T.J Watson Research Center in Hawthorne,NY during 2002-2003. Since the summer of 2005, Bjorn is working at IMEC(Interuniversity Micro-Electronics Center) where he is developing tool chains andmethodologies for high-performance, low-power computing on coarse-grainedreconfigurable architectures.

The HiPEAC cluster on whole-system optimizationannounces a PLDI 2006 tutorial

Cluster Activity

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Cluster Activity

Industrial vision

May 10, 2006Grenoble, FranceColocated with the HiPEAC 5thGeneral Cluster Meeting (May 11and 12)

The free GNU Compiler Collection is theleading tool suite for portable develop-ments on open platforms. It supportsmore than 6 input languages and 30target instruction sets, with state-of-the-art support for debugging, profilingand cross-compilation. It has long beensupported by the general-purpose andhigh-performance hardware vendors.The last couple of years have seen GCCgaining momentum in the embeddedsystems industry, and also as a platform

for advanced research in programanalysis, transformation and optimiza-tion.

ContextThe HiPEAC network has decided tosupport GCC as a compiler platform forresearch and development in compila-tion for high-performance and embed-ded systems. It encourages researchersfrom inside and outside the network toshare experience, projects, and proto-types based on this common platform.

This tutorial is an attempt to bootstrapnew research and developments involv-ing GCC, and to help those alreadyinvolved in GCC-related projects to get

support and answers.

The targeted audience is the compila-tion/architecture researcher/engineerfrom industry or academia with a goodbackground in textbook compilationand optimization. Prior knowledge of acompiler infrastructure is not assumed.Conversely, people with a lot of experi-ence should be able to gain usefulinformation and practice from this tuto-rial.

Notice that we will address practicalissues aimed at helping developers withtypical problem-solving and technicaldesign issues. The overlap with GCC-related courses presented during the

GCC Research Platform Cluster announces gcc tutorial

Major research challenges in thedomain of high performance embed-ded computing

This presentation will highlight some highlevel challenges we see coming in thedomain of high performance embeddedcomputing. I will not present solutions(although Philips is actively working tosolve major issues) because we are waitingfor the HiPEAC research community tocome up with innovative solutions andconcepts, not what we (industry) can doourselves.

Mastering ComplexityOne of the first challenges is mastering theincreasing complexity of future Systems onChip (SoC). As an example, one of our cur-rent chips for advanced set-top box anddigital TV running at 250 MHz already has100 clock domains, more than 60 IP blocks(including processors and coprocessors),250 RAMs, and delivers an equivalent ofmore than 100 Gops for a power budgetof 4 W. In the coming years, we can envis-

age systems that will be of one or severalorders of magnitude more complex. The complexity will increase unrelentinglybecause applications become more andmore demanding and the associated algo-rithmic complexity grows exponentiallyover time. For example, TV image improve-ment applications will soon exceed thetera-operation per second mark for HighDefinition images, not counting therequirements for new features like contentanalysis and indexing, 2D to 3D conver-sion, mixed synthetic and natural imagesand other requirements for AmbientIntelligence. This huge amount of compu-tation will increasingly be performed withprogrammable/configurable architecturesto reduce the development cost comparedto dedicated/non-reusable solutions (maskcost is increasing above a dangerousthreshold).

Improving silicon efficiencyHow can we improve silicon efficiencywhile still being programmable? This willinvolve the challenges of designing multi-

core systems using all possible levels ofparallelism to reach the performance den-sity required, of extracting all the paral-lelism from the application(s) and of map-ping it efficiently to the hardware. Majorbreakthroughs will be required in compilertechnology and in mapping tools.

The nightmare of debug and validationBut that will not be enough: debuggingand validating/testing systems is becomingmore and more of a nightmare. Systemscan no longer be verified with simulations,and we will need new validationapproaches otherwise the unpredictabilityand unreliability due to the combination ofuse cases will make the systems practicallyunusable: the probability of “crash” will be100%! Assembling systems with “unpre-dictable” elements will increase the globalsystem unpredictability, therefore tech-niques that add unpredictability (such ascache, run-time re-ordering, …) should beavoided if possible. A large area of today'smicroprocessors are used to cope withapplication unpredictability (branch predic-

Summary of the talk given by Dr. Marc Duranton at the Delft cluster meeting

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ACACES 2005 and 2006 summerschools should be minimal.

OutlineStarting from a brief presentation ofGCC and its ecosystem, we will surveythe main information sources and drawa quick map of the compiler infrastruc-ture. We will cover debugging, trou-bleshooting and testing issues, as wellas the standard interaction policy withother GCC developers.

Two practical examples of how todesign, add, implement and test a newphase will follow:

high-level program transformation

for the typed SSA-form representa-tion in GCC 4, through the design ofa new optimization based on loopdistribution, an optimization that isnot currently offered by GCC;low-level code generation and back-end retargeting, through a automaticvectorization example for an SIMDinstruction not currently supported byGCC.

The time allocated for the tutorial willnot allow for a fully interactive hands-on tutorial session. However, eachexample will be associated with a pre-digested hands-on exercise. A precisedescription of the exercise, with instal-lation procedure, support files and doc-

umentation, will be available on theHiPEAC web site a few weeks prior tothe tutorial.

The tutorial organizers will be availablein the late afternoon, and during thenext two days, to help the attendeeswith these exercises or with GCC-relat-ed issues in general.

OrganizersAlbert Cohen (INRIA)Zbignew Chamski (Philips)Ayal Zaks (IBM)Georges Silber (Ecole des Mines de Paris)Sebastian Pop (Ecole des Mines de Paris)

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tion, reordering buffers, instructionscaches, …) in order to have best effort per-formance.

Sustained performancesBut for most embedded systems, the mainchallenge is in having sustained perform-ance, not peak: guaranteed performanceand predictable timing behavior are impor-tant, together with Quality of Service, safe-ty, reliability and dependability.Current systems are not really designedwith a “separation of concerns” in mind,and, due to shared resources, a slightchange can have a drastic impact. This is aclear challenge for system modeling andfor system design flow.

Design approachA disciplined design approach is needed,guided by the principle of predictabilityand compositionality (composability).Virtualization of (shared) resources with afocus on real-time guarantees, standard-ized interfaces to connect subsystems, for-mal methods (allowing “correct by con-struction” systems), and a higher abstrac-tion level for combined hardware and soft-ware specifications are key elements toovercome the limits of validation by simu-lation and worst case designs that are nolonger affordable. This could also help to

reduce the gap between design complexi-ty and designer productivity.

Communication centric architecturesComputational complexity is not the onlyproblem: communication, i.e. bringingdata on time is a well-known challenge.The classical “Von Neumann” bottleneckor “memory wall” suggests the need fornon-classical architectures to overcome itsconstraints. This move from “computecentric” to “communication centric”architectures is also induced by the newsub-micron technology nodes that willincrease the gap between access time andcompute time. The interconnect beingpredominant, the scaling for clock speed isno longer valid, suggesting the need formore parallel architectures. This also hasan impact on timing closure, the size ofsynchronous areas, the derating factor,etc.

Impact of smaller technology nodesAnother consequence is the increasingvariability of components. Of course, thesmaller technology nodes also add to thewell-known power challenge: the leakagepower becomes predominant, leading toactive power management and powergating at a much finer grain. The totalactive power can be unacceptable due to

the sum of leakage and active currents.

Impact for peopleThe increasing complexity of systems isalso an issue for the end user: for example,a study indicates that 2/3 of Americans lostinterest in a technology product because itseemed “too complex to set up or oper-ate” and 48% of people have put off buy-ing a digital camera because they see themas too complicated. Hence the quest fortechnology that is really useful. Fortunatelyfor us, researchers and industry, we needexponentially more technology to provide abit more sense and simplicity.

As shown above, many challenges lay infront of us, but the strategic partnershipbetween top researchers and industrialistsinvolved in high-performance embeddedsystems as developed in HIPEAC will openthe way to new breakthroughs that willallow Europe to keep her leadership inembedded systems, as expressed by theCommission in the Future and EmergingTechnologies(see http://www.cordis.lu/ist/fet/nca.htm):“High-performance, low-power embed-ded and networked computing systemsare and will be a key market for Europe.With the expected slowing down ofMoore's law, silicon technology will pro-

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IBM, HaifaInstitution: IBMLocation: IBM Research Lab in Haifa, IsraelTiming: about 3 months (summer of 2006or some time later).Description:Position 1Automatic extraction of heterogenousthread-level parallelism. We would like toexplore new ways to automatically extractparallelism and to compile a single source

program into multiple threads, each run-ning a separate 'program' on a differentprocessor/ISA (in contrast to SPMD).Position 2:Increasing ease-of-use in programming ofCell Broadband Engines. The new CellBroadband Engine provides unique capa-bilities, yet demands effective softwaretools to use these capabilities efficiently.We would like to explore innovative solu-

tions for effective debugging and monitor-ing, as well as support for easy-to-use par-allel programming models and runtime. Inaddition, compilation issues such asenhancing auto-parallelism generationbased on auto-vectorization capabilitieswill be considered.

ARM, Cambridge, UKInstitution: ARMLocation: Cambridge, UKDescription: We are looking for interns inthe R&D group in Cambridge, UK. Thecandidate should have a strong back-

ground in some or all of the following:processor microarchitecture, architecture,simulator design, compilers, signal pro-cessing algorithms, and hardware imple-mentation. All candidates should possess

good software skills C, C++, Java. Theideal candidate would be someone who isworking towards a PhD and could con-tribute both deliverables and ideas to ourprojects.

Infineon Technologies, MunichInstitution: INFINEONLocation: MunichTiming: three to six monthsDescription: The automotive and industri-

al business unit of Infineon Technologies inMunich offers a three to six month intern-ship to a PhD student to work in theTriCore applications section. The work will

cover adaption of automotive software tothe multithreaded TriCore-2 embeddedprocessor core and/or performance analy-sis topics.

vide limited further improvements on fun-damental processor design. Increasingly,breakthroughs will come from new archi-tecture developments driven by perform-ance, low power and low cost in combina-tion with a new generation of compilingand operating systems.”

Acknowledgements:Many thanks to Theo A.C.M. Claasen,Albert van der Werf and all the others towhom I have “borrowed” slides for thepresentation.Dr. Marc DurantonPrincipal Scientist

Biography:Dr. Marc Duranton is a principal scientist in the Embedded Systems Architectures on SiliconGroup of Philips Research. He has two MSc degrees, in electrical engineering and computerscience, from Ecole Nationale Supérieure d'Electronique et de Radioélectricité de Grenoble andEcole Nationale Supérieure d'Informatique et de Mathématiques Appliquées de Grenoblerespectively, and a PhD (1995) from Institut National Polytechnique de Grenoble, all in France.He worked within Philips Semiconductors in California on several video coprocessors for theTriMedia and Nexperia platforms and is currently working on the next generation computeengine for the Philips platform. His research interests include parallel and high performancearchitectures for video and image processing, system modeling and validation, software opti-mization and compiler technology. He has published several articles and book chapters, andregistered more than 20 patents. He has supervised 4 PhD students and more than 10 MScstudents, and has given courses in several engineering schools in France. ■

Embedded Systems Architectures onSilicon (ESAS) High Tech Campus 31 - 5656 AEEindhoven, The NetherlandsPhone: +31 40 27 45426Fax: +31 40 27 44639Email: marc.duranton@philips.com

PhD internships

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PhD internships

Upcoming events

CF 06, ACM International Conference on Computing FrontiersIschia, Italy, May 2-5, 2006, http://www.computingfrontiers.org/

HiPEAC GCC TutorialGrenoble, France, May 10 2006

5th HiPEAC General Cluster MeetingGrenoble, France, May 11-12 2006, http://www.hipeac.net

ICAC 2006. The 3rd IEEE International Conference on Autonomic ComputingDublin, Ireland June 2006, http://www.caip.rutgers.edu/icac2006/

Special issue on Embedded Systems for Portable and Mobile Video Platforms. Eurasip Journal on Embedded SystemsDeadline: June 1, 2006, http://www.hindawi.com

Conference on Programming Language Design and Implementation, (PLDI 2006)Ottawa, Canada, June 11-14, 2006, http://research.microsoft.com/conferences/pldi06/

Conference on Languages, Compilers, and Tools for Embedded Systems, (LCTES 2006)Ottawa, Canada, June 14-16, 2006, http://www.elis.ugent.be/lctes2006/

International Symposium on Computer Architecture (ISCA-33)Boston, MA USA, June 17-21, 2006, http://www.ece.neu.edu/conf/isca2006/

International Conference on Supercomputing (ICS06)Australia (Queensland) June 28 – July 1, 2006, http://www.ics-conference.org/2006/

SAMOS VI. Embedded Computer Systems: Architectures, Modeling, and SimulationSamos, Greece, July 17-20, 2006, http://samos.et.tudelft.nl/samos_vi/

43rd Design Automation Conference (DAC 2006)Moscone Center, San Fransisco, California. July 24 – 28, 2006, http://www.dac.com/43rd/index.html

ACACES 2006 Summer School + 6th HiPEAC cluster meetingL’Aquila, Italy, July 23-29, http://www.hipeac.net/hipeac/summerschool/

STMicroelectronics, FranceInstitution: STMicroelectronicsLocation: FranceDescription:Position 1Developing a GCC front-end that takes a.NET executable as input, and producesoptimized native code as output. Thisachieves two goals: the validation of acomplete static compilation path from Cto native code using CIL as intermediateformat; and the production of code for STspecific targets from .NET executables.Position 2Study the quality of the code produced bythe compilers Microsoft's Visual Studio,

lcc.NET and DotGNU in terms of code sizeand performance, and to propose newoptimizations. Whole program optimiza-tions are of particular interest.Position 3Improve the LCC.NET compiler, in particu-lar to support 64 bit integers and to pro-duce CIL code that is compatible with theVisual C++ compiler (Visual C++ only com-piles C++ into CIL). This work will providea way to produce CIL code on Linux plat-form for use by non-Microsoft .NET proj-ects, in particular Mono, DotGNUPortable.NET and the Just-In-Time CIL tonative code compiler currently being devel-

oped by STMicroelectronics in Manno.Position 4Work on the SSA optimizations inside theSTMicroelectronics JIT compiler, in particu-lar the transformation of conditional codeinto predicated code. In predicated code,explicit branches are replaced by instruc-tions like conditional moves or conditionalselections. The target processors for theSTMicroelectronics JIT compiler are theARM and the STMicroelectronics ST200processors. Development is done in Clanguage on Linux.

12 info6

HiPEAC Info is a quarterly newsletter published by the HiPEAC network of excellence. Funded by the 6th European Framework Programme (FP6), under contract no. IST-004408.Website : http://www.hipeac.net. Subscriptions: http://www.hipeac.net/newsletter

Upcoming events

ISSPIT 2006, The 6th IEEE International Symposium on Signal Processing and Information TechnologyVancouver, Canada. August 27-30, 2006, http://web.unbc.ca/~zhoul/isspit/

Euro-Par 2006Dresden, Germany, 29th August 1st September 2006, http://www.europar2006.de/

PATMOS 2006, Power and Timing Modeling, Optimization and SimulationMontpellier, France, September 13-15, 2006, http://www.lirmm.fr/patmos06/

International Conference on Parallel Architectures and Compilation Techniques (PACT-2006)Seattle, Washington, September 16-20, 2006, http://www.pactconf.org/

Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII) San Jose, CA, October 21-25, 2006, http://www.princeton.edu/~asplos06/

CODES+ISSS 2006, International Conference on Hardware/Software Codesign and System SynthesisSeoul, Korea, October 23-25, 2006, http://www.ida.liu.se/conferences/codes/

IISWC-2006, IEEE International Symposium on Workload CharacterizationHilton Hotel, San Jose, California, USA. October 25-28, 2006, http://www.iiswc.org/iiswc2006/

MICRO-39, The 39th Annual IEEE/ACM International Symposium on MicroarchitectureOrlando, Florida, USA, December, 9-13, 2006, http://www.microarch.org/micro39/

ACACES 2006 registration deadline: May 1, 2006Next HiPEAC General Cluster Meeting: May 11, 2006

ContributionsIf you are a HiPEAC member

and you want to contribute to this newsletter,please contact Thomas Van Parys at Thomas.VanParys@elis.UGent.be