Hướng dẫn sử dụng phần mềm thiết kế mạch điện tử Orcad 10.5

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Hng dn s dng phn mm thit k mch in t Orcad 10.5 Li ni u

Nhm 1 Lp 04T1 Page 1

Phn mm thit k mch in t OrCAD ca tp on Cadence c cc chuyn vin nh gi l mt trong nhng phn mm thit k mch mnh nht hin nay. OrCAD c mt v h tr cho cc k thut vin thit k mch t rt sm. T OrCAD phin bn 3.2 chy trn nn dos cho ti phin bn 4.0 c nhng cp nht ng k. Tip l phin bn 7.0 chy trn nn window lm say m ngi thit k mch in chuyn nghip, sau c phin bn 9.0, 10.5 v mi nht hin nay l phin bn 15.7.

Orcad l mt phn mm chuyn dng rt mnh vi giao din rt thn thin, cch s dng n gin. Bn c th v mch nguyn l vi OrCAD Capture, chy m phng vi Pspice, c bit l chc nng v mch in rt mnh vi OrCAD layout, cng vi mt th vin linh kin khng l c hu ht cc nh sn xut linh kin in t cung cp cho OrCAD. C l chng ta khng cn phi bn ti sc mnh ca n m phi quan tm ti vic lm sao khai thc v s dng OrCAD hiu qu trong vic thit k mch.

Vi mc ch hng dn s dng v gip cc bn thun li hn trong vic thit k mch, nhm chng ti xy dng nn ti liu Hng dn s dng OrCAD 10.5 ny. Chng ti ngh rng ti liu ny kt hp vi s thc hnh, my m nhiu ca cc bn s gip cho cc bn thc hin hiu qu v nhanh chng hn vic thit k mch khi s dng phn mm OrCAD.

Vi s n lc ht mnh ca cc thnh vin trong nhm, chng ti c gng trnh by tht r rng v chi tit nhng cng khng th trnh khi nhng thiu st. Mong thy c v cc bn gp ti liu ca chng ti c hon chnh hn.

Nhm 1 04T1


Hng dn s dng phn mm thit k mch in t Orcad 10.5 Mc lc


Chng 1: V mch nguyn l bng ORCAD CAPTURE 1.1. Tng quan v Orcad Capture 1.2. V mt mch nguyn l bng Orcad Capture 1.2.1. Khi ng Capture 1.2.2. To mt project mi 1.2.2.1. Ca s Capture CIS 1.2.2.2. To mt new project 1.2.2.3. Thit lp kch thc cho bn v 1.2.2.4. Mt s cng c hay dng trong vic v mch nguyn l 1.2.3. V s nguyn l 1.2.3.1. Tm kim v chn linh kin 1.2.3.2. t linh kin 1.2.3.3. Sp xp linh kin 1.2.3.4. Chy dy v hiu chnh linh kin 1.2.4. Kim tra li s nguyn l 1.2.5. To netlist 1.3. To linh kin mi t ca s Capture 1.3.1. Gii thiu 1.3.2. Cc bc to linh kin mi 1.3.2.1. Tm datasheet 1.3.2.2. Phn tch datasheet 1.3.2.3. Khi ng capture 1.3.2.4. To th vin cha linh kin 1.3.2.5. Bt u to linh kin 1.3.2.5.1. To tng nhm chn linh kin 1.3.2.5.2. Chnh sa v v ng bao 1.3.2.5.3. Lu Chng 2: V mch in bng ORCAD LAYOUT PLUS 2.1. Gii thiu tng quan v phn mm Orcad layout 10.5: 2.2. Ni dung 2.2.1. Khi ng Layout plus 2.2.2. Mt s menu lnh c bn 2.2.2.1. File 2.2.2.1.1. Open 2.2.2.1.2. Import 2.2.2.1.2. Export




2.2.2.2. Tools 2.2.2.2.1. Library Manager 2.2.2.2.2. OrCAD Capture 2.2.3. To project mi 2.2.3.1. Lin kt Footprint 2.2.3.1.1. Mt s footprint thng dng 2.2.3.1.2. Lin kt footprint 2.2.4. t footprint trn board mch 2.2.4.1. Chnh sa chn linh kin 2.2.4.2. To mi chn linh kin 2.2.4.3. Nhng ch khi to mi chn linh kin 2.2.5. Mt s thao tc cn thit trc khi Layout 2.2.6. Thit lp mi trng thit k 2.2.6.1. Thit lp n v o v hin th 2.2.6.2. o kch thc board mch 2.2.6.3. nh ngha Layer Stack 2.2.6.4. Thit lp khong cch gia cc ng mch 2.2.6.5. Thit lp rng ng mch in 2.2.6.6. V Board Outline 2.2.7. Sp xp linh kin ln board mch 2.2.7.1. Sp xp linh kin bng tay 2.2.7.2. Sp xp linh kin t ng 2.2.8. V mch 2.2.8.1. V t ng 2.2.8.2. V bng tay 2.2.9. Hon thin bn mch 2.2.9.1. Chn mt on text vo mch in 2.2.9.2. Ph ng cho mch in 2.2.9.3. Kim tra li 2.2.10. In mch Layout Chng 3: M phng mch bng ORCAD PSPISE 3.1. Gii thiu Orcad Pspice 3.1.1. Chc nng ca Pspice 3.1.2. u im ca Pspice vi mt s phn mm m phng thng dng 3.2. L thuyt 3.2.1. Cc cng c h tr cho vic m phng 3.2.1.1. Orcad Capture 3.2.1.2. Simulus Editor 3.2.1.3. Model Editor 3.2.2. M phng 3.2.2.1. M phng t ca s CAPTURE 3.2.2.3. M phng s dng ca s Pspice hoc Pspice A/D




3.2.2.3.1. Cc bc thc hin 3.2.2.3.2. Xc nh li loi phn tch t mt file m phng c sn 3.2.3. Cc dng phn tch c bn 3.2.3.1. Phn tch DC Sweep 3.2.3.1.1. Thit lp m phng DC sweep 3.2.3.1.2. Phn tch bin th cp 3.2.3.1.3. V h c tuyn vi phn tch DC Sweep 3.2.3.2. Phn tch Bias point 3.2.3.2.1. Hm truyn tn hiu nh DC 3.2.3.2.2. Phn tch nhy DC 3.2.3.3. Phn tch AC Sweep/Noise 2.2.3.3.1. Phn tch AC Sweep 3.2.3.3.2. Phn tch nhiu (noise) 3.2.3.4. Phn tch Transient v Fourier 3.2.3.4.1. Phn tch Time domain (Transient) 3.2.3.4.2. Phn tch Fourier 3.2.4. Cc dng phn tch nng cao gm nhiu phn tch cng lc 3.2.4.1. Parametric v Temparature 3.2.4.1.1. Phn tch Parametric (tham s) 3.2.4.1.2. Phn tch nhit 3.2.4.2. Monte Carlo v Sensitivity/worst-case 3.2.4.2.1. Phn tch Monte Carlo 3.2.4.2.2. Phn tch Worst case 3.2.5. M phng s 3.3. V d 3.3.1. V d m phng mt s mch tng t 3.3.1.1. M phng mt mch theo phn tch DC 3.3.1.1.1. DC Sweep 3.3.1.1.2. DC Sweep/ secondary sweep 3.3.1.1.3. H c tuyn v ng ti 3.3.1.2. M phng mt mch theo phn tch bias point (im phn cc) 3.3.1.2.1. Phn tch Bias point 3.3.1.3. M phng mt mch theo phn tch AC/Noise 3.3.1.3.1. Phn tch AC Sweep 3.3.1.3.2. Phn tch nhiu AC/Noise 3.3.1.4. M phng mt mch theo phn tch trong min thi gian 3.3.1.5. Phn tch Monte Carlo v Sensitivity/worst case (phn tch nhy) 3.3.1.5.1. Phn tch Monte Carlo 3.3.1.5.2. Phn tch Sensitivity/worst case 3.3.1.6. Phn tch Parametric v nhit 3.3.1.6.1. Phn tch Parametric 3.3.1.6.2. Phn tch nhit 3.3.2. M phng mt mch s


Hng dn s dng phn mm thit k mch in t Orcad 10.5 Orcad Capture


1.1. Tng quan v Orcad Capture Orcad Capture l phn mm dng v mch nguyn l, phn mm ny rt thun tin cho vic tm v chn linh kin v mch nguyn l v th vin ca n cung cp kh y linh kin. 1.2. V mt mch nguyn l bng Orcad Capture 1.2.1. Khi ng Capture Khi ng Orcad vi chng trnh Capture hoc Capture CIS.




1.2.2. To mt project mi 1.2.2.1. Ca s Capture CIS

Mn hnh Capture CIS hin ra nh trn . Tip theo bn to mt project mi lm vic. 1.2.2.2. To mt new project to mt project bn c th lm nh sau:

Chn menu file >> new >> project.




Hoc chn nt lnh create document Hp thoi new project hin ra, nhp tn project, chn ng dn cho project.

Xut hin mt ca s , cho php bn chn v tr t project (Location) v tn project (Name).

Bn c th nhp vo nt Browse chn ng dn cho project.

Ca s tip theo cho php bn chn th mc lm vic. Nu bn mun to mt th mc con cha cc project ca bn, nhp vo nt

Create Dir




Trong hp thoi Create Directory, bn nh tn th mc mnh mun to v bm OK.

Sau khi to v chn th mc con, bn c th t tn cho project. Ti ngh tt nht bn nn chn tn project v tn th mc con trng nhau tin cho vic theo di.

1.2.2.3. Thit lp kch thc cho bn v Sau khi to project lm vic, xut hin mt ca s c cc chm nh. Tip theo bn chn kch thc cho bn v, bn c th thay i sau nhng theo ti bn nn chn trc.

Trong tab Options chn Schematic Page Properties nh sau:




Mt hp thoi Schematic Page Properties hin ra cho php bn chn kh giy nh sau:

Bn c th chn kch thc theo Inches hoc Milimeters. Bn c th chn kh

giy mc nh theo A4,A3,A2,A1,A0 hoc chn theo Custom tu bn, ri bm OK.

1.2.2.4. Mt s cng c hay dng trong vic v mch nguyn l Mt s cng c hay dng trong vic v mch nguyn l vi bn schematic. Dng biu tng trn thanh Tool palette (hoc dng phm tt).




: Tm linh kin (P). : Nt chn. : Chy dy (W). : To net (N). : To im ni (J): .

: Ngun (F). : t (G): : im khng ni (X).

Xoay linh kin (R). Lt linh kin theo trc ngang (H). Lt linh kin theo trc dc (V). 1.2.3. V s nguyn l 1.2.3.1. Tm kim v chn linh kin tm linh kin bn c th lm nh sau:

Nhn P Chn biu tng




Nu l ln u tin bn chy ORCAD th th vin linh kin cha c ADD vo. Do bn chn ADD Library a cc th vin thm vo.

Trong hp thoi Browse File nh trong hnh sau, bn c th ADD cc linh kin vo, bn chn tt c cc file.olb v nhn open.

Sau khi add th vin, bn s thy hp thoi nh sau:

T hp Libraries , cc bn ch chut vo bt k mt trong cc th vin c Add vo th danh sch cc linh kin trn ca s Part List s thay i.




Thng bn khng th no nh linh kin no thuc th vin no c, do bn nn chn ht (bm Ctrl+A). Bn s thy hnh sau:

Bn nh tn linh kin vo hp Part chn linh kin ph hp vi mch nguyn l.

Cc bn nhp OK v ca s ny mt i, linh kin dnh vo chut ca bn. Khi bn nhp chut tri th linh kin c t xung nh hnh v.

Mc d linh kin c t xung giy v vn tip tc dnh vo chut, nu bn nhp tri tip th n tip tc c t .Do ngng vic t linh kin nhn phm ESC trn bn phm.




Bn nn t y linh kin vo kh giy trc ri ni mch li. ni mch cc bn nhp vo ch Z ngc gc phi pha trn ca s lm vic.

Bn bm chut tri vo chn linh kin ny v ni vo chn linh kin khc. Bn cng c th ni dy t chn linh kin vo dy c sn hoc gia cc linh kin

vi nhau. Mun di chuyn linh kin nhp vo linh kin v ko n ni cn. Bn cng c th xoay linh kin Rotate, lt theo trc dc Vertical, lt theo trc

ngang Horizontal. Cui cng l cc chn ca linh kin no khng ni th nh du X vo.

qu trnh hng dn n gin, ti s hng dn thng qua mt mch c th. Mch ti chn l mch nguyn l: Mch iu khin sng n.




Bn thy rng mch ny gm c: 1 cu diode, 3 jack cm 2 chn, 1 t phn cc, 1 diode zener, 6 in tr, 1 quang tr, 1 bin tr, 4 transistor, 1 triac , 2 chn mass.

u tin bn to kh giy v ly tng linh kin ra. V d khi ly in tr:

Bm P

Bm OK.




1.2.3.2. t linh kin

Bn ln lt ly cc linh kin cn li. Sau khi ly ht tt c cc linh kin bn s c hnh sau:




1.2.3.3. Sp xp linh kin By gi bn sp xp cc linh kin theo s mch.

1.2.3.4. Chy dy v hiu chnh linh kin

Chng ta thay i gi tr cho ph hp V d i vi R3

Nhp double click vo gi tr linh kin. Nhp gi tr vo v nhn OK. (theo di hnh bn)




Thc hin ln lt i vi cc linh kin khc. Sau khi xong ta c hnh sau:

1.2.4. Kim tra li s nguyn l

Nhp biu tng minimize trn gc phi ,mn hnh sau xut hin v chn page1.




Nhp biu tng design rules check Hp thoi design rules check, nhp ok v khng thng bo g th bm OK. Nu

c thng bo li bn hy sa li ri tip tc.




1.2.5. To netlist Phn ny ti s hng dn cc bn to netlist t c th chuyn sang v mch in. u tin bn to file.mnl.

Nhp vo biu tng c ch create netlist. Mt hp thoai Create Nestlist hin ra, in y thng tin vo hp thoi ri bm OK.

Ti y bn s thy mt hp thoi khc hin ra cng l c tn l Create Nestlist.




Chn layout. Bm OK.

T y bn c th v mch bng Orcad Layout Plus.




1.3. To linh kin mi t ca s Capture 1.3.1. Gii thiu Vic to ra linh kin mi trong capture rt quan trng, bi v cc chn linh kin in t u sn xut theo mt s tiu chun nht nh. Trong layout th mt s chn linh kin ta khng bit, bn cng c th tm mt linh kin khc m c chn tng t, cn trong capture th cng vic bn khng th thc hin c. 1.3.2. Cc bc to linh kin mi Mt project c th bao gm trong vic to ra linh kin mi, to ra bn v hoc xut mch in. Nh vy vic to ra linh kin mi c th l mt phn trong khi bn v mt bn schematic no . Khi vic to ra linh kin mi l vic lm ph phc v cho bn schematic no . to ra linh kin mi, bn cn phi nhn din linh kin l g, tc l bit datasheet ca n. Gi s bn cn to linh kin l mt con IC 74LS138. 1.3.2.1. Tm datasheet Vic u tin l bn phi i tm datasheet ca 74LS1238 lm c iu ny bn c th ln http://www.google.com. Ri g tm 74LS1238. Sau khi tm bn s c c mt bn datasheet nh sau:




1.3.2.2. Phn tch datasheet Khi c datasheet trong tay, bn xem th chn linh kin ca n b tr ra sao. Vic tip theo l hnh dung cch b tr chn trong schematis.

Nhm chn A B C l nhm chn u vo chn v bt u t chn s 1, cc chn ny u mc cao.

Nhm chn G1 (mc cao), G2A v G2B (mc thp) l nhm chn u vo iu khin, bt u t chn s 4.

Chn VCC chn s 16 v chn GND chn s 8. Nhm chn ng ra Y0Y7 , chn Y7 v tr chn s 7 cn cc chn cn li

Y0(15).Y6(9). Sau khi phn tch v tm hiu v tr cc chn chng ta bt u i thit k. 1.3.2.3. Khi ng capture Bn khi ng Orcad Capture nh hng dn phn 1.2. Bn s c ca s Capture nh sau:




1.3.2.4. To th vin cha linh kin Trc ht bn cn phi to ra mt th vin cha cc linh kin mnh to ra, bn chn tab file >> new >> library. Mt khung thoi Add to Project nh sau hin ra: Sau khi hp thoi hin ra, y l lc Capture hi bn mun to ra th vin u. To ra trong ch trong project hay to ra trong Library.

Nu cc bn to ra ch trong project ang thc hin th chn C:\ORCAD\ORCAD_10.5......

Nu to ra mt linh kin mi b sung vo Library th chn New Project. Ti chn New Project v bm OK. Mt ca s khc hin ra:




Khi ny th vin c to ra v nm trong c s qun l. Cc bn s thy mt th mc Library c to ra,trong c mt file Library.olb.

Nhp chut phi vo v chn New Part chun b to ra linh kin mi.




1.3.2.5. Bt u to linh kin

in tn linh kin vo v y l con chip c th nh ngha kiu n l U Khi cc bn bm OK, t ca s Capture bn s thy mt ng bao ngoi vi nt t. Kiu linh kin c ghi pha trn l U?; Gi tri linh kin c ghi pha di l .




Nh cc bn bit to ra linh kin l to ra cc chn linh kin , ri to ra hnh dng ng bao v t tn cho ph hp.

1.3.2.5.1. To tng nhm chn linh kin Chng ta to ra 3 chn A B C.

Starting Name l A, starting number 1, number of pins l 3, shape l ng v chn linh kin thng l lin tc nn chn l line, type l loi nhm chn chn Input.

Increment l tng Starting Name v Starting number ln, y n v tng ln l 1.

Pin Space cc chn t st nhau nn chn l 1.




Khi cc bn OK th con chut ca bn bin thnh 3 chn linh kin. Trn khi U vung,cc bn t n cnh no n s cnh .

Nu nh s chn linh kin to ra di hn khi U vung th khi ny t ko di ra. Tip theo l 3 chn u vo iu khin , cch lm tng t nh sau.

i vi chn G2A ti chn G2C:




Tip theo l chn Y7




Chn mass(GND) Chn mass l chn ngun nn ta chon kiu Power Chn ny c hai ch hin th v khng hin th,ta chn hin th ra.

Check vo Pin Visible.

N s hin ra nh sau




Cc chn Y0Y6

Cui cng l chn cui cng l chn Vcc




1.3.2.5.2. Chnh sa v v ng bao u tin, bn kch vo biu tng hnh vung thanh tool palette v ng bao. Bn double click vo chn linh kin chnh sa cho hp vi s chn.




1.3.2.5.3. Lu Sau khi ta hon thnh. Chng ta Save v xem li trong mn hnh qun l.


Hng dn s dng phn mm thit k mch in t Orcad 10.5 Orcad Layout Plus

2.1. Gii thiu tng quan v phn mm Orcad layout 10.5: Orcad layout l mt phn mm rt mnh chuyn dng v s mch in t s mch in nguyn l c v bng Orcad capture (hay bng cc phn mm v mch nguyn l chuyn dng khc). Phn mm ny c lp trnh rt thun tin cho ngi s dng trong vic sp t linh kin, i dy v chun b s mch in cho vic sn xut 2.2. Ni dung 2.2.1. Khi ng Layout plus m Layout, vo Start Menu>>Program>>Orcad 10.5 >>Layout Plus




S xut hin hp thoi sau:

2.2.2. Mt s menu lnh c bn 2.2.2.1. File Cha cc lnh lin quan n vic to mi, m, nhp vo hay xut ra cc tp tin i tng vo Layout hay sang cc thnh phn khc(ca phn mm thit k mch khc nh Protel, PCAD PCB ) 2.2.2.1.1. Open Thanh Open lit k tt c cc tp tin.MAX ang nm trong th mc hin hnh. m file .MAX bn ch cn chn file cn m sau chn Open l xong hay bn c th nhp double click chut vo file chn.

2.2.2.1.2. Import Cho php m hay du nhp mt file c to ra t cc phn mm thit k mch khc nh Protel PCB, CadStar PCB




2.2.2.1.2. Export

Cho php xut file .MAX c to ra t OrCAD Layout sang cc phn mm thit k mch in khc nh CadStar PCB, Protel PCB

2.2.2.2. Tools 2.2.2.2.1. Library Manager Cho php bn edit hay to mi mt footprint ca mt linh kin no . T y bn c th to hay su tp mt th vin footprint linh kin m bn hay s dng cho cc thit k sau ny ca mnh. 2.2.2.2.2. OrCAD Capture Cho php bn m chng trnh thit k mch nguyn l OrCAD Capture t chng trnh v board mch OrCAD Layout. Ngoi ra trong Tools cn cc chc nng khc nh SmartRout cho php bn v mch thng minh, Edit App Settings, Reload App Settings. 2.2.3. To project mi to project mi, vo menu File >> New. Bn s thy mt hp thoi hin ra nh hnh v sau:




Ti khung Input Layout TCH ta nhp vo file template c t C:\OrCAD\OrCAD_10.5\tools\layout_plus\data\_default.tch. File template l file nh dng mt s thng s mc nh cho board mch,

nh l s lp board mch, khong cch i dy, kch thc ng mch, quy nh thit k, v...vc s dng xuyn sut trong qu trnh layout.

Nu bn thit k board mch bnh thng th bn load default.tch. Cn nu bn mun thit k board mch ring theo mt hnh dng c th, nh Sound card,Lan card, th load cc file template khc.

Ti khung Input MNL nestlist file bn nhp vo file nestlist c ui l MNL ( c to ra trong Orcad Capture).

Ti khung Output Layout Max file bn nhp vo ng dn v tn file m bn mun file thit k ca mnh c lu. Layout Plus s mc nh tn file output




layout trng tn vi file input nestlist. Nu bn thay i file output th khng c thay i phn m rng (.max).

Sau click Apply ECO. ECO (Engineering Change Order): l mt lnh ca Layout cho php s thay i ca mt trong hai s Layout hay Capture cng s dn n s thay i tng ng ca s kia.

Nu cc linh kin trong mch thit k l cc linh kin mi, v cha tng lin kt n th vin footprint ca Layout ln no, th n yu cu bn phi lin kt n footprint. y l bc kh khn i hi bn phi cn thn. Bn s tin hnh cch lm ny phn bn di. Kinh nghim cho thy s tt hn nu bn thc hin vic gn footprint cho tt c cc linh kin trong sut qu trnh v mch bng Capture. 2.2.3.1. Lin kt Footprint lm tt phn ny th i hi bn phi thng xuyn lm mch, c kinh nghim s nhanh tm c cc footprint trong th vin. 2.2.3.1.1. Mt s footprint thng dng

Th vin TO: TO92(trans.C828,C1815,C535,)TO202 (trans. H1061, IC n p h 78xxx, 79xxx )

Th vin DIP100T: /W.300 (cc IC cm t 14-20 chn) /W.600(cc IC cm t 24-40 chn )

Th vin TM_CAP_P l footprint ca cc loi t in. Th vin TM_CYLND l footprint ca cc loi t in. Th vin JUMPER l footprint ca cc loi in tr, quang tr,bin tr

(JUMPER100,JUMPER200,JUMPER300,) Th vin TM_DIODE l footprint ca cc loi diode hay Led.

2.2.3.1.2. Lin kt footprint Sau mt thi gian ch i, hp thoi nh sau xut hin.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca C1 c tn l:CAP_POL.V th nn tm chn cho linh kin ny bng cch nhp chut vo nt Link existing footprint to component

Hp thoi Footprint for CAPACITOR_POL xut hin ti khung Libraries nhp chn mc JUMPER.

Ti khung Footprints nhp chn mc JUMPER200 (khong cch chn l 200 mils bng 5 mm) chn chn mch in cho T.

Chn xong bm Ok. Tip theo trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca R8 c tn l R. Nhp vo nt Link existing footprint to component




Hp thoi Footprint for R xut hin,ti khung Libraries nhp chn mc JUMPER.

Ti khung Footprints nhp chn mc JUMPER200 chn chn mch in cho in tr ny.

Bm Ok.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca J1 c tn l CON2. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for CON2 xut hin, ti khung Libraries nhp chn mc JUMPER.

Ti khung Footprints nhp chn mc JUMPER100 chn chn mch in cho CON2.

Nhp Ok.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca Q1 c tn l T2323. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for T2323 xut hin, ti khung Libraries nhp chn mc TO.

Ti khung Footprints nhp chn mc TO126 chn chn mch in cho Triac. Nhp Ok.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca Q2 c tn l 2N3904. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for 2N3904 xut hin,ti khung Libraries nhp chn mc TO.

Ti khung Footprints nhp chn mc TO202AB chn chn mch in cho Transistor.

Nhp Ok.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca D1 c tn l RB152. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for RB152 xut hin,ti khung Libraries nhp chn mc BCON100T.

Ti khung Footprints nhp chn mc BLKCON.100/VH/TM1SQ/W.100/4 chn chn mch in cho cu diode.

Nhp Ok.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca D2 c tn l DIODE_ZENER. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for DIODE_ZENER xut hin, ti khung Libraries nhp chn mc JUMPER.

Ti khung Footprints nhp chn mc JUMPER100 chn chn mch in cho DIODE_ZENER.

Nhp Ok




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca R1 c tn l R2. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for R2 xut hin, ti khung Libraries nhp chn mc JUMPER.

Ti khung Footprints nhp chn mc JUMPER200 chn chn mch in cho quang tr.

Nhp Ok.




Trong hp thoi Link Footprint to Component c thng bo l khng th tm thy chn mch in ca R2 c tn l RESISTOR_VAR_2. Nhp vo nt Link existing footprint to component

Hp thoi Footprint for RESISTOR_VAR_2 xut hin, ti khung Libraries nhp chn mc JUMPER.

Ti khung Footprints nhp chn mc JUMPER300 chn chn mch in cho bin tr.

Nhp Ok.




Sau khi thc hin xong cc bc trn xut hin hp thoi:

Nhp chn Accept this ECO. Tip theo nhp OK. Sau khi lin kt cc footprint n ton b cc loi linh kin, Orcad t ng load cc footprint nh hnh v :




2.2.4. t footprint trn board mch Khi cc footprint c load, nu khng ng vi yu cu thit k thc t th bn phi chnh sa hoc to mi chn linh kin cho ph hp. 2.2.4.1. Chnh sa chn linh kin Chn footprint linh kin cn thay i trn board mch va load, sau click chut phi v bn s thy menu dc xut hin, tip theo bn chn Properties.




Sau khi chn Properties th mt hp thoi xut hin cho chng ta chn loi footprint thch hp.

Click chut vo Footprint, sau bn s thy mt hp thoi cho bn chn footprint thch hp. T hp thoi Select Footprint ta c th la chn footprint thch hp theo ca mnh. Tuy nhin, nu cc footprint c trong Select Footprint khng ph hp th chng ta phi to mi footprint cho ph hp v kch thc ca linh kin. 2.2.4.2. To mi chn linh kin Ta c th t to linh kin mi bng cch m Layout ln, vo menu Tools Library manager




to mt footprint mi hon ton bn bm Create New Footprint V d: To footprint cho mt pushbutton (Panasonic part EVQ-PAG04M) bn cn mt s thng tin v kch thc ca n:

hp thoi Create New Footprint

Nhp tn linh kin mi mc Name of footprint, v d l PB

Bm chn English. Mc d kch c cc b phn ca linh kin c cho h mt nhng hu ht kch thc ch to PCB vn bng n v inches ( hay mils = 1/1000 inch).




dng theo h mt bn phi thay i systems settings. (vo Options >>System Settings) xut hin hp thoi bn.

Nhp OK. By gi bn ang lm vic theo h mt.

Switch c tt c 4 chn nhng ta ch cn nh dng cho 1 padstack v cc chn du c c im ging nhau.

u tin vo View Spreadsheet ->Padstacks. Ta thy xut hin hp thoi padstacks, ta double click vo padstack c tn T1 s xut hin hp thoi Edit Padstack cho tt c cc lp ca T1.

Bn thay i tn ca padstack ny, thng th t tn theo tn footprint. iu ny lm cho vic tm kim n d dng hn trong Layout khi c nhiu padstack. Tip nhp chn Undefined trong mc Pad Shape

Nhp OK. Xut hin hp thoi padstacks. Bn thy padstack tn PB vi tt c cc lp ca n khng c nh dng




Da vo Datasheet bn nh dng cho cc lp ca padstack PB. Nu chn nhiu lp cng mt lc th nhn chn tn cc lp ng thi gi phm Ctrl. Bn ch cn nh dng cho nhng lp cn thit .

u tin bn cn nh dng kch thc cho chn l khoan, theo datasheet ng knh chn l khoan l 1 mm.

Ta chn 2 lp DRLDWG, DRILL. Click phi chut chn Properties , xut hin hp thoi Edit Padstack >> nhp

chn Round, sau nhp gi tr 1(=40 mils) vo Height v Width. Nhp OK

Bn thy trong hp thoi padstacks lp DRLDWG, DRILL c nh dng:




Tng t bn nh dng cho cc lp TOP, BOTTOM, INNER. Thng th kch thc ca vng xuyn bao quanh l chn khoan ln hn l khoan khong 20 mils(=0.5 mm). Do nhp gi tr 1.5mm vo Height v Width. V lp gia ca mch l ming ng dnh cho power v ground, trnh hin tng ngn mch ngi ta thng to ra xung quanh cc l khoan mt khong trng, ln hn kch thc l khoan l 35 mils(=1.75 mm). Bn nhp gi tr 2 mm vo Height v Width v chn pad dng round cho lp PLANE. Cui cng bn cn nh dng cho mt hn chn linh kin, thng th n ln hn vng xuyn bao quanh chn l khoan khong 5 mils(=0.125 mm). Do bn chn pad hnh round v nhp gi tr 1.625mm vo Height v Width cho lp SMTOP and SMBOT.

Sau khi nh dng xong cho cc lp ca padstack ny, ta s lu tn ca footprint mi to vo th vin, ta nn to th vin mi d dng tm kim sau ny.

Bng cch click Save As trong hp thoi Library manager. in tn footprint mi to, sau click vo Create New Library to th vin

mi.




Nhp OK th footprint mi to s c lu vo th vin.

Sau chn Text tool xa bt cc ch khng cn thit i, ch li &Comp v &Value. Nhp vo text cn xa v bm phm Delete (trn bn phm). Thm cc chn linh kin vo bng cch chn cng c b.

Click chut phi vo nn en, chn New t chn mi v tr thch hp




Chn thuc tnh cho 2 text cn li bng ko chut bi n, xong click chut phi, chn Properties (phm tt Ctrl+E).

Chn Layer l SSTOP. Chn OK.




Sau bn sp xp li v tr cho cc chn, bn lun lun t v tr ca pad1 ti (x,y) = (0, 0) >> double click vo pad1 xut hin hp thoi EDIT PAD.

Bn da vo Datasheet bit khong cch gia cc chn xc nh v tr cho cc chn cn li. Pad2 = (0, 6.5)




Cc chn khc tng t Pad4 = (4.5, 0) Pad3 = (6.5, 4.5)

Bn c th dng cc cng c o dt nh: Dimension, Measurement trong menu Tool c th to khong cch chnh xc gia cc chn.

Ngoi ra bn cn c th v thm cc ng bao (Obstacle) cho linh kin, y l ng ranh gii gia cc footprint khi sp xp chng khng b chng cho nhau.

v ng bao bn click vo biu tng Obstacle Tool, sau click phi chut chn New, gi chut tri ng thi ko n cc gc chn pad, ng bao bao quanh cc chn pad.




u tin bn t tn cho ng bao, sau chn Place Outline ti Obstacle Type. dy width ty .




Thng bn chn ng bao ny nm lp Global Layer, tc thuc tnh Obstacle Layer l Global Layer. Cui cng click OK lu li cc nh dng cho footprint mi to. Bn hon thnh vic to 1 footprint mi khng c sn trong th vin ca layout. nhanh hn bn c th lt qua th vin ca layout tm nhng footprint tng t footprint m bn cn to sa cha cho ph hp vi thc t ri Save As n li, lu li trong th vin mi m bn to cho d tm kim. 2.2.4.3. Nhng ch khi to mi chn linh kin Khi thit k footprint, ngoi vic bn cn bit chnh xc kch thc thc gia cc chn linh kin thit k k ng, cn phi bit kch thc ca c linh kin c th b tr khong cch gia cc linh kin cho hp l. Mt s kinh nghim chn kch thc cho chn linh kin:

Vi cc linh kin thng nh in tr, t, diode bn chn chn hnh trn (Round), ng knh l 1.8 n 2.1, ty loi linh kin.

Chn 1 ca IC hay cc linh kin c cc tnh nh t hoc diode bn nn chn kiu chn l hnh vung hoc hnh ch nht.

Vi IC ta nn chn chn hnh Oval (vi cc chn 2 tr ln) v hnh ch nht (i vi chn 1). Kch thc thng l 1.7mm Width v 2.2 mm Height.

Vi cc chn linh kin to nh chn ca cc JACK cm, chn ca IC c cn th nn chn b Width(b ngang) to ra mt t, c 1.8mm.

Thc t vic to ra linh kin trong Capture quan trng hn rt nhiu ln so vi vic to ra linh kin trong Layout (hay Layout Plus).

Bi v cc linh kin in t u c sn xut theo mt s tiu chun nht nh, v cc kiu chn ca linh kin c nh chun. Do bn ch cn s dng cc chn layout c nh dng ging vy s dng, khng nht thit phi to ra cc nh dng chn cho tng linh kin ring bit. 2.2.5. Mt s thao tc cn thit trc khi Layout Trc khi i vo cc thao tc chnh khi layout, bn cn lm mt vi vic nh gip mn hnh hin thi d nhn hn.

u tin, bn s tt DRC (Design Rule Check), bn s cn dng chng sau, nhng khng phi by gi. Sau khi tt, khung ch nht nt t s bin mt.

Nhng k hiu xut hin bn cnh cc linh kin c th khng cn thit nhng chng s lm cho mn hnh ca chng ta ri hn. C 2 cch xa chng i: Chn Text Tool trn thanh cng c, click chut vo on k hiu m bn

mun xa i, sau click chut phi v chn delete. Hoc nu bn mun xa hon ton cc k hiu i km, bn lm nh sau:

Chn lp 23 AST nh hnh v, sau tt n i.(s dng phm -)




Sau mn hnh s xut hin nh sau:

2.2.6. Thit lp mi trng thit k 2.2.6.1. Thit lp n v o v hin th y cng l n v th hin rng ca ng mch in trong board mch. Mc ch ca vn ny l gip cho ngi thit k qun l c kch thc ca cc nets trong board mch cng nh kch thc ca board outline. Cch lm nh sau: Vo Options >> System settings. Bn s thy hp thoi sau xut hin:




y bn nn chn n v l Millimeters(mm). Ngoi ra ta cn c th thit lp li v, t li nu cn thit khung Grids. 2.2.6.2. o kch thc board mch Vo Tool >> Dimension >> Select Tool. Sau o di v rng ca ng bao. Mc ch ca cch lm ny l cho ngi thit k bit c board mch mnh thit k c kch thc tht bao nhiu, t c nhng iu chnh hp l trong vic sp xp cc linh kin trong ng bao cho ph hp vi board mch in m mnh ang c.




2.2.6.3. nh ngha Layer Stack nh ngha Layer Stack, bn chn Spreedsheet t Toolbar

Nhp Layers chn lp v, y bn chn lp BOTTOM, click chut phi chn Properties.




Chn nh sau:

Nhp chn OK. 2.2.6.4. Thit lp khong cch gia cc ng mch thit lp nhng lut v khong cch cho pads, tracks v vias. Bn chn Spreedsheet t Toolbar. Chn Strategy >> Route Spacing.




T menu pop up chn Properties, bn s thy:

y bn c th iu chnh cc thng s cho ph hp. Cn ch n v o m bn thit lp trn. Chn OK. 2.2.6.5. Thit lp rng ng mch in Bn lm iu ny iu chnh rng ca cc nets trong mch khc nhau ty theo chc nng ca chng. V d nh: cc ng ngun, mass phi ln hn cc ngun tn hiu, hay cc ng ng vi mch cng sut th b rng cng phi ln hn bnh thng Mun iu chnh cc thng s ny bn c th lm nh sau: Vo Spreedsheet Nets. Bi en tt c:




Kch chut phi chn Properties:

Min Width, Conn Width, Max Width l rng ca nets mch in. Khng nn 3 gi tr ny bng nhau, v khi i mch my s t ng iu chnh rng ca nets. Khi t t th n chn Min, khi nhiu s chn Max, nh vy s linh hot hn. 2.2.6.6. V Board Outline Board Outline l ng bao ngoi cho tt c cc linh kin v cc ng mch trong mch in. v bn tin hnh nh sau:

Click chut vo Obstacle Tool, sau click vo mt gc m bn mun v Outline, con chut chuyn thnh du cng nh, click phi, chn Properties s hin ra hp thoi sau:




Bn chn nh hnh v. Sau chn OK. Click vo 4 gc ca khung m bn mun v, sau nhn ESC.




2.2.7. Sp xp linh kin ln board mch Vic b tr linh kin ln board mch l mt trong nhng yu t quan trng quyt nh n n nh, d v v thm m,v.vca board mch. Bn c th sp xp linh kin bng tay hoc s dng chc nng t ng sp xp ca Layout Plus. 2.2.7.1. Sp xp linh kin bng tay Nhp chut vo biu tng Component Tool trn thanh cng c. di chuyn linh kin no ta nhp chut vo linh kin , sau , khi nh chut ra v di chuyn th linh kin cng s di chuyn theo. n v tr cn t linh kin th nhp chut mt ln na, v linh kin s c c inh. Sau khi sp xp mt lc ta c nh sau:




2.2.7.2. Sp xp linh kin t ng u tin bn cn phi c nh mt s linh kin m bn mun n c t mt v tr xc nh, trnh b thay i v tr trong qu trnh auto. Di chuyn linh kin n v tr xc nh, nhp chut phi chn Lock. Sau khi c nh c cc linh kin theo yu cu, chn Auto >> Place >> Board. 2.2.8. V mch Layout Plus h tr c 2 chc nng v t ng v v bng tay. Thng thng nn kt hp c 2 chc nng ny, v khi v t ng i khi s c nhng ng mch rt phc tp, lc ta nn iu chnh li bng tay. 2.2.8.1. V t ng Vo Auto >> Auto Route >> Board, Layout Plus s t ng v mch. 2.2.8.2. V bng tay Chn Edit Segment Mode.




Kch vo dy mun v, lc dy s gn vi con tr, r chut to ng mch, kch tri chut c nh ng mch. i hng ng i ca mch: kch vo cui on dy, sau i theo hng m bn mun v. Sau khi v xong, nhn ESC kt thc. Nhp F5 refresh bn mch. Sau khi v, bn s c nh sau:

2.2.9. Hon thin bn mch n y, bn hon thnh mch in v mt c bn. Trong phn ny bn s tin hnh mt s thao tc cui cng trc khi xut mch in. 2.2.9.1. Chn mt on text vo mch in

Chn Text Tool t thanh cng c. Click phi vo mn hnh chn New. Hp thoi Text Edit hin ra, trong khung Text String g ni dung cn chn. Lu : nu bn lm mch in th cng th click chn Mirrored khi i khng b ngc.




Chn OK. Di chuyn on text n v tr cn chn, click chut.




2.2.9.2. Ph ng cho mch in Mc ch ca vn ny l chng nhiu cho mch in. Cch lm nh sau:

Chn Obstacle Tool. Nhp chut vo khung mch, con chut co thnh du cng nh th click phi, chn Property.

Mn hnh s xut hin hp thoi Edit Obstacle.

Trong khung Obstacle Type chn: Copper Pour. Trong khung Obstacle Layer chn lp cn ph Copper Pour: c th l TOP hay

BOTTOM. Trong khung Net Attachment th chn l GND hoc POWER, ty theo bn

mun ph theo GND hay POWER. Nhn OK.




2.2.9.3. Kim tra li Sau khi v xong bn cn kim tra li s ng n ca mch in bng cch click chut vo DRC trn thanh cng c. Nu mch c li hoc cnh bo (bng nhng vng trn mu ) th bn phi sa ht cc li th mch in th thit k mi khng m bo b chm nhau. 2.2.10. In mch Layout in mch Layout va v, bn thc hin cc bc sau:

Chn Option >> Post Process Settings




Nhp chut phi vo lp mun in (vd: lp BOTTOM), chn Preview




Vo menu File, chn Print/Plot

Chn nh trn, nhp chn OK.




Kt qu bn t c l:


Hng dn s dng phn mm thit k mch in t Orcad 10.5 Orcad Pspice

3.1. Gii thiu Orcad Pspice 3.1.1. Chc nng ca Pspice Orcad l mt chng trnh ng dng gm y cc cng c cho mt ngi thit k mch. Ngoi cng c v mch nguyn l, v mch in, Orcad bao gm c chng trnh m phng kh mnh, c bit n vi tn Orcad Pspice. Pspice l mt chng trnh m phng hot ng ca mt mch in t. iu ny cho php bn c th kim tra kh nng hot ng ca mt mch va thit k trc khi tin hnh v mch in v lm vic vi cc linh kin tht. Pspice c th m phng mch tng t, mch s hoc mch hn hp c cc linh kin tng t v s. y l mt trong nhng u im quan trng ca Pspice. Bn c th m phng mt mch t chnh ca s Capture hoc Capture CIS, hoc cng c th m phng t cc ca s ca Pspice. Sau khi tin hnh ci t Orcad, t thanh start, vo menu Orcad bn c th thy c rt nhiu mc u c ch Pspice. Mi mc ng vi mt ca s ring bit v mi ca s cho php bn lm vic vi cc dng m phng khc nhau.




Nu bn chn mc Pspice bn ch c th m phng mt mch tng t, nhng nu chn mc Pspice A/D bn c th m phng mch tng t, mch s, hoc mch hn hp gm cc linh kin tng t v s. Pspice A/D c thit k gm cc vng lp hi tip song song bn c th m phng mt mch hn hp gm c linh kin s v tng t mt cch ring l. Bn cnh Pspice v Pspice A/D, b cng c Orcad cng bao gm mt s cng c thm vo quan st kh nng hot ng v nh gi tin cy ca bn thit k trc khi chuyn i n thnh sn phm thc. V d nh Pspice smoke analysis cho php ngi s dng m phng mch theo phn tch smoke dng phn tch mch vi nhng iu kin nguy him nht (stress conditions) ca linh kin. Hoc Pspice Optimizer dng cn chnh cc s liu trong bn thit k sao cho ph hp vi iu kin thc t, gip ngi thit k quan st xem mch va thit k c t c cc mc tiu hot ng m h t ra hay khng. Ngoi ra cn c cc cng c nng cao cho cc cng c va k trn, dng cho mc ch rng hn khi thit k mch st vi thc t v yu cu nhiu linh kin hn. Orcad c a ra vi 2 bn chnh thc, bao gm bn full dnh cho mc ch thng mi v bn lite dnh cho sinh vin, c cung cp min ph. Nu s dng bn Lite th rt t linh kin, v vic m phng s gp nhiu kh khn, ngoi ra trong bn thit k cng gii hn s lng linh kin, rt kh thit k cc mch ln. Do trong ti liu ny trnh by cch m phng s dng bn Orcad full. Pspice ch cho php m phng trong s lng cc linh kin c sn trong th vin cung cp km theo sn phm. Vic to linh kin mi tuy thc hin c nhng rt phc tp, do s khng trnh by k trong ti liu ny. Tuy nhin, th vin ca Pspice rt ln, cho php ngi thit k c th m phng ln n 16.000 linh kin tng t v 1.600 linh kin s, do vi ngi s dng hon ton c th yn tm s dng Pspice m phng hu ht cc loi mch thng thng. Trong ni dung ti liu ny, do thi gian c hn v kinh nghim s dng Orcad Pspice cha nhiu nn ch gii thiu mt s chc nng c bn ca Orcad Pspice. Nhng chc nng nng cao v phn tch thc t (Smoke hay Optimizer) cha th nghin cu r rng nn khng a vo ti liu ny. 3.1.2. u im ca Pspice vi mt s phn mm m phng thng dng Pspice l phn mm mnh v m phng tng t, phn tch dng sng. Mc d th vin linh kin ca Pspice kh ln nhng thiu nhng linh kin hin th trc quan nn rt kh quan st mch s. Tuy nhin phn phn tch mch tng t ca Pspice th kh y , th vin linh kin nhiu v cho nhiu dng phn tch p ng yu cu thc t nn c th s dng hiu qu trong vic thit k mch thc t. Hin nay, phn mm m phng kh ni ting l Proteus. y l phn mm mnh v m phng vi iu khin. Orcad Pspice th khng m phng c vi iu khin. Tuy nhin v th vin linh kin th Orcad Pspice nhiu hn v v th kh nng m phng cng t hiu qu hn, nht l i vi dng mch tng t. Phn mm Protel cng c phn m phng tng t nh Orcad Pspice, v cng c th ly th vin linh kin t Orcad sang nn kh nng m phng cng tng i mnh. Tuy nhin dng phn tch ca Protel th khng a dng bng.




3.2. L thuyt 3.2.1. Cc cng c h tr cho vic m phng 3.2.1.1. Orcad Capture y l cng c chun b bn v cho vic m phng. Trong ca s ca Orcad Capture ngi s dng c th lm nhng cng vic sau phc v cho vic m phng:

To mt project mi. V mch. Thit lp thng s cho cc linh kin trong mch. Thit lp dng sng u vo. Thit lp ch v cc tham s m phng. Chn im m phng.

3.2.1.2. Simulus Editor y l cng c nh dng dng sng u vo ca mch, cng c ny cho php ngi s dng t nh dng dng tn hiu bin i theo thi gian c dng trong qu trnh m phng. chn cng c ny, bn lm nh sau:




Ca s ca cng c ny s xut hin, bn chn biu tng to mt dng sng mi:

to dng sng bn chn biu tng , hp thoi sau s hin ra:




Bn g tn ca dng sng mi, v chn dng sng cn thit lp. Vi Stimulus Editor bn c th thit lp cc dng sng sau:

Cc dng sng tng t: sng sin, xung, sng theo hm m, sng PWL(piecewise linear), SFFM (single-frequency FM).

Vi dng sng s: xung ng h n gin, n cc tn hiu xung phc tp v chui bus.

Sau khi chn dng sng, bn s thit lp thng s cho dng sng mi, bm Ok, mt hp thoi khc hin ra. Bn thit lp cc thng s cho dng sng mi, sau bm apply, bn s c dng sng mi. V d vi cc thng s nh sau s c dng sng mi to l:




Ring i vi dng sng tng t PWL v cc dng sng s, Stimulus Editor cho php bn t v dng sng m khng cn hp thoi thit lp thng s, bng cch nhp chut vo cc im ngay trn mn hnh hp thoi Stimulus Editor. 3.2.1.3. Model Editor y l cng c gip ngi s dng np vo cc thng s ca linh kin phc v cho qu trnh m phng, nhng linh kin ny phi c trong th vin ca Orcad Pspice hoc Orcad Capture, ngi s dng ch thay i cc thng s ca linh kin, km theo l thay i cc c tuyn ca linh kin. Cc thng s np vo c th ly t datasheet ca linh kin. chn cng c ny bn lm nh sau:

T ca s ca Model editor bn chn biu tng chn linh kin, sau thay i thng s linh kin bng cch in cc thng s vo bng xut hin trong hp thoi:




C 2 cch thay i thng s linh kin, dng c tuyn v dng bng tham s:




Tng kt li, chun b cho vic m phng bn cn c cc cng c to ra mt s file d liu, c th tng kt nh hnh v:

3.2.2. M phng 3.2.2.1. M phng t ca s CAPTURE m phng mt mch hon ton mi, cha c lu trong Orcad 10.5, bn m ca s Capture:




T ca s Capture, chn biu tng to mt project mi, hp thoi sau hin ra:

Bn chn tn cho project, chn Analog or Mixed A/D nh dng file m phng (nu khng chn nh trn th file to ra s khng m phng c), ri bm OK. Mt hp thoi khc hin ra:

Nu file m phng to mi hon ton khng km theo hay tha hng t mt file c sn no th bn chn Create a blank project ri bm OK. Nh vy bn to ra mt file m phng mi.




Sau khi v mch (phn v mch c hng dn trong chng 1), bn chn file >> save hoc bm Ctrl+S hoc chn biu tng lu mch va v, bn chn tab Pspice >> New simulation profile thit lp thng s cho qu trnh m phng, mt hp thoi nh sau hin ra:

Bn nh tn ca file m phng s to, nu khng s dng file nh km bn chn none nh hnh v, nu s dng file nh km bn chn biu tng ri ch n ng dn n file nh km. Sau bn chn Create to file m phng.

Hp thoi sau s hin ra, y l hp thoi thit lp thng s cho qu trnh m phng:




Chn dng m phng t tab Analysis. Nu l m phng s th chn tab Options ri chn Gate-level simulation t hp Category nh hnh v:

Sau khi thit lp y thng s cho qu trnh m phng, chn dng m phng, bn bm OK, file hin thi ca bn l mt file m phng. (Vic chn dng m phng no, thit lp ra sao s trnh by trong tng loi m phng phn Cc dng m phng.)

Lc ny, bn c th sa cha mch ca mnh nhng sau phi thit lp li thng s cho file m phng nh trn.

Tip theo bn m Pspice >> Marker v chn mt trong nhng loi cng c c sn t vo im cn quan st khi m phng. Vic chn loi marker no tu thuc vo loi thng s (dng hay p ...) bn mun xem ca s Probe.

Sau khi t cc Marker, bn chn Run t tab Pspice hoc bm F11 bt u m phng. Nu khng c li g xut hin th bn s nhn c mt ca s Pspice hin th dng sng hoc cc thng s cn m phng.

Nu c li xy ra, bn c th xem li hin th ngay pha di khung ca s Pspice mi m:




Lc ny bn c th sa li ri tip tc m phng nh trn. Nu thnh cng bn s nhn c mt ca s Pspice c dng sng kiu nh sau:




3.2.2.3. M phng s dng ca s Pspice hoc Pspice A/D 3.2.2.3.1. Cc bc thc hin Trong phn ny bn c th thc hin m phng t ca s Pspice vi mt file cha mch c v sn.

M ca s Pspice hoc Pspice A/D (nu bn mun m phng mt mch s hoc mt mch hn hp gm c linh kin s v tng t):

Trong ca s Pspice (hoc Pspice A/D) bn chn File >> New >> Simulation profile to ra mt file m phng. Lc ny hp thoi sau s hin ra:




Bn nh tn file m phng s to vo Profile name, v nh tn file c cha mch m bn cn m phng vo Inherit from an existing profile (y phi l mt file Pspice th mi thc hin m phng c), ri bm Create.

Hp thoai Simulation setting s hin ra, bn thit lp thng s m phng nh trong phn m phng t ca s Capture, ri bm OK.

Sau , bn chn Run t menu Simulation chy file m phng.

3.2.2.3.2. Xc nh li loi phn tch t mt file m phng c sn Bn cng c th nh dng li file ang chy thc hin mt dng m phng khc, hoc vi mt tham s m phng khc. T ca s Pspice bn thc hin cc thao tc nh trong phn 2.2.2.3.1. m file cn m phng. thit lp lai thng s cho vic m phng, bn chn Edit profile t menu Simulation. Hp thoi Simulation settings s hin cho php bn chn li dng m phng mong mun. Nh vy v c bn vic thit lp thng s cho cc loi m phng l nh nhau, ch khc trong phn thit lp thng s trong hp thoi Simulation settings. Do , t phn ny tr i, khi thit lp loi m phng, ti ch nhc cc phn thit lp t hp thoi Simulation settings m thi.




3.2.3. Cc dng phn tch c bn Pspice c th thc hin c dng m phng tng t, m phng s v m phng hn hp gm c linh kin tng t v s. i vi mch s, Pspice ch h tr m phng linh kin s theo dng phn tch Transient c bn, bao gm c dng phn tch worst-case (gm 2 trng hp min-max). i vi mch hn hp th tt c cc dng phn tch di y u c thc hin. Pspice c th thc hin cc dng phn tch sau:

Phn tch DC, AC v transient: cc dng phn tch dp ng ca mch i vi nhng u vo khc nhau.

Phn tch Monte Carlo, sensitivity, worst-case, v parametric: phn tch s thay i ca mch i vi cc gi tr khc nhau ca cc linh kin, thnh phn trong mch.

Phn tch Digital worst-case timing: dng phn tch nhng vn v thi gian ch xy ra do s truyn tn hiu nhanh hoc chm.

Cc loi phn tch ca Pspice: Loi phn tch La chn trong Analysis type Bin phn tch Phn tch DC im phn cc c tuyn truyn t tn hiu nh DC nhay DC p ng tn s Nhiu Phn tch Trasient Phn tch Fourier Phn tch tham s Nhit Monte Carlo nhy/ Trng hp khc nghit nht

DC Sweep Bias point Bias point Bias point AC Sweep/Noise AC Sweep/Noise Time domain (Transient) Time domain (Transient) Parametric sweep Temperature Monte Carlo/Worst-case Monte Carlo/Worst-case

Ngun (p hoc dng) Tham s Nhit Tn s Tn s Thi gian Thi gian

3.2.3.1. Phn tch DC Sweep Phn tch DC phn tch hot ng ca mch ng vi trng hp mch s dng ngun mt chiu. Phn tch DC c c th thc hin cc phn tch sau:

DC sweep: Phn tch mt ngun, mt tham s hoc mt s thay i theo nhit ca mt mch c u vo l in p, dng in mt chiu.




Bias point: Tnh ton im phn cc ca mt mch cho trc. DC sensitivity: L mt phn trong kiu phn tch bias point, dng phn tch

nhy ca in p tng hoc in p thnh phn. Small-signal DC transfer: Cng l mt phn trong kiu phn tch Bias point,

dng tnh ton li ca tn hiu nh DC, tr khng vo, tr khng ra. Cc iu kin thc hin phn tch DC:

Loi bin phn tch Yu cu Voltage Source Current Source Temperature Model Parameter Global Parameter

Ngun p mt chiu Ngun dng mt chiu Pspice A/D Model (.MODEL) Tham s tng c nh ngha trong Parameter Block (.PARAM)

thit lp cc loi phn tch DC ni chung, trong hp thoi Simulation settings chn DC Sweep trong hp Analysis type.

Phn tch DC cho php bn phn tch mt ngun (ngun dng hoc ngun p), tham s tng hoc tham s m hnh, hoc nhit trong mt khong gi tr nht nh. im phn cc ca mch c tnh ton i vi mi gi tr phn tch. iu ny rt hu ch khi tm hm truyn t ca mt mch khuych i, ngng cao v ngng thp ca cng logic

thit lp thng s mt chiu (ngun mt chiu, hoc dng mt chiu) th chn Properties t tab Edit, sau chn ct DC ri nh vo gi tr ca ngun:




tnh ton thng s DC ca mt mch tng t, Pspice loi b nhng thng s c lin quan n thi gian ra khi mch. iu ny c thc hin bng cch h mch tt c cc t, ngn mch tt c cc cun cm, v ch s dng cc gi tr mt chiu ca ngun p v ngun dng. Tng t vi cc mch s, tt c cc tr truyn u c thit lp bng 0, v cc ngun pht c a v gi tr ban u.

3.2.3.1.1. Thit lp m phng DC sweep thit lp m phng DC sweep th phi dng nhng ngun c lp v thit lp mc in p hoc dng in 1 chiu cho mi ngun. Dng mt trong nhng thnh phn sau: i vi u vo l in p Dng Khi thc hin... VDC VSRC

Ch phn tch DC Sweep hoc phn tch Bias point (hm truyn t) Phn tch nhiu thnh phn cng lc trong c phn tch DC Sweep hoc Bias point (hm truyn t)

i vi u vo l dng in Dng Khi thc hin ... IDC ISRC

Ch phn tch DC Sweep hoc phn tch Bias point (hm truyn t) Phn tch nhiu thnh phn cng lc trong c phn tch DC Sweep hoc Bias point (hm truyn t)

Cch thit lp hon ton ging cch thit lp chung cho phn tch DC sweep:




3.2.3.1.2. Phn tch bin th cp Phn tch bin th cp c th c thit lp nh cc la chn trong phn phn tch DC sweep. Khi la chn phn tch thm mt bin th cp th mt vng phn tch na c thc hin. Tc l, vi mi s thay i ca bin th cp th bin s cp c kho st qua tt c cc gi tr trong khong phn tch thm mt ln. thit lp loi phn tch ny bn lm nh sau:

Trong Options ca loi phn tch DC Sweep, nh du tick vo Secondary sweep .

in cc gi tr tham s cn thit v nh du vo cc la chn thch hp xc nh kiu phn tch mong mun.

3.2.3.1.3. V h c tuyn vi phn tch DC Sweep C th s dng phn tch DC Sweep vi la chn bin th cp v mt h c tuyn ca mt linh kin bn dn no , ng thi c th v ng ti ca mt in tr hoc ca chnh linh kin bng cch s dng Marker, thng dng marker Current into pin t vo v tr tnh ton ng ti t in p c phn tch. 3.2.3.2. Phn tch Bias point i vi Pspice lc no im phn cc cng c tnh ton khi phn tch mc, bt k loi phn tch m bn chn. Tuy nhin nu khng chn phn tch Bias point th ch nhng im in p tng t v nhng im trng thi s c cho bit t file u ra (file phn




tch c to ra t PSpice hoc PSpice A/D). Nu kch hot loi phn tch Bias point th t file u ra ta c nhng thng s sau:

Danh sch tt c cc im in p tng t. Danh sch tt c cc im trng thi s. Dng in v cng sut ca tt c cc ngun in p. Cc tham s tn hiu nh ca tt c cc linh kin.

Tuy nhin ngay c khi kch hot phn tch Bias point bn vn c th b nhng thng s v im phn cc tng t v trng thi s trong file u ra bng cch chn th Options trong hp thoi Simulation settings, chn Output file trong hp Category, ri b du tick trong Bias point node Voltage (NOBIAS):

thit lp phn tch Bias point, bn c th lm nh sau:

Trong hp thoi Simulation settings, chn tab Analysis, chn Bias point trong Analysis type.

Trong hp Options, chn General settings (thng c nh du tick sn), in cc thng s cn thit vo cc mc v nh du chn cc thch hp cho yu cu m phng ca bn.




Sau bm OK lu thit lp va chn, ri bm Run tr menu Pspice chy m phng.

Ngoi vic phn tch Bias point c bn nh trn, trong mc Bias point cn c th thc hin 2 loi m phng sau: 3.2.3.2.1. Hm truyn tn hiu nh DC Phn tch ny tnh ton hm truyn tn hiu nh v cho bit li tn hiu nh, tr khng ra, tr khng vo.

thc hin phn tch ny th trong mch phi c t nht mt ngun u vo, v d nh VSRC.

Cch thit lp phn tch hm truyn tn hiu nh DC v tnh li tn hiu nh: Trong hp thoi Simulation settings, chn tab Analysis, chn Bias point

trong Analysis type. Trong Options, chn General settings, tick vo chn Calculate

small-signal DC gain (.TF). in tn ca ngun u vo vo From Input Source name. in gi tr cho in p ra hoc dng in ra thng qua mt ngun in p

trong To Output variable. V d: nh V(a,b) ch nh bin u ra l in p gia 2 im a v b trong mch. Hoc nh I (VDRIV) ch bin u ra l mt dng in thng qua ngun p VDRIV.




Tt c cc tnh ton li t ngun u vo ti bin u ra u km theo tr khng vo v tr khng ra. 3.2.3.2.2. Phn tch nhy DC Phn tch nhy DC tc l phn tch nhy ca mt im in p (s thay i ca mt im in p) i vi tham s ca mt trong nhng linh kin sau:

in tr. Ngun dng hoc ngun p c lp. Chuyn mch iu khin bng dng hoc p. Diode. BJT.

Thit lp phn tch nhy DC: Trong hp thoi Simulation settings, chn tab Analysis, chn Bias point trong

Analysis type. Trong Options, chn General settings, tick chn Perform Sensitivity analysis

(.SEN). in cc thng s cn thit vo Output variable.




Bm OK lu thit lp m phng va ci t. Chn Run t menu Pspice hoc bm F11 chy m phng.

3.2.3.3. Phn tch AC Sweep/Noise Phn tch ny tnh ton hot ng ca mch ng vi trng hp mch s dng 1 dng in thay i. Phn tch AC and Noise c th thc hin cc dng phn tch sau:

AC sweep: Phn tch p ng tn s ca mch tn hiu nh. u ra bao gm dng in v in p c v mt ln v pha. Ngoi ra cng c th dng ca s v th bode trong thanh Probe quan st cc dng phn tch ny.

Noise: Cho bit p ng u ra khi c nhiu u vo, ng thi tng hp nhiu u ra khi c nhiu ngun nhiu u vo. ( phn tch nhiu th bn phi dng dng phn tch AC sweep)

2.2.3.3.1. Phn tch AC Sweep Mt s iu cn lu trong phn tch AC Sweep:

Pspice phn tch p ng tn hiu nh ca mch i vi tng hp cc u vo bng cch tnh ton mch quanh im phn cc v coi mch nh mt mch tuyn tnh. Do , nhng linh kin phi tuyn, chuyn mch iu khin bng dng bng bng p, s c chuyn i sang mch tuyn tnh ti im phn cc ca n.

Linh kin s th gi nguyn trng thi khi Pspice tnh ton im phn cc.




V phn tch AC Sweep ch thc hin phn tch tuyn tnh, nn n ch xt ti li v p ng pha ca mch, khng gii hn l dng in hay in p.

Cch tt nht thc hin phn tch AC Sweep l thit lp cho ln ca ngun bng 1, u ra o c bng chnh li, t thy c r mi tng quan gia u ra v u vo.

iu kin thc hin phn tch AC Sweep: Phi s dng mt hoc nhiu ngun c lp. Phi thit lp ln xoay chiu v pha cho mi ngun. Phn tch AC Sweep

khng ging phn tch DC Sweep, y khng c ch thit lp ngun u vo, thay vo ngun c lp trong mch phi cha gi tr xoay chiu v c ln v pha.

Phi c mt trong nhng ngun sau trong mch: i vi u vo l in p Dng Khi thc hin VAC VSRC

ch mnh phn tch AC Sweep nhiu phn tch cng lc trong c phn tch AC Sweep

i vi u vo l dng in Dng Khi thc hin IAC ISRC

ch mnh phn tch AC Sweep nhiu phn tch cng lc trong c phn tch AC Sweep

Kch p 2 ln vo vo biu tng ngun m bng thng s, in vo gi tr thch hp di cc ct. Tu vo loi ngun m ch nh gi tr xoay chiu ca n theo mu sau:

Vi ngun VAC hoc IAC Thit lp gi tr trong ct Gi tr ACMAG ACPHASE

ln xoay chiu tnh bng Volts (i vi in p) v Amps (i vi dng in) pha xoay chiu tnh bng




i vi ngun VSRC hoc ISRC Thit lp gi tr trong ct Gi tr AC -ln (Volts) hoc pha ()




Thit lp phn tch AC Sweep: Chn tab Analysis trong khung hp thoi Simulation settings, trong hp Analysis

type chn AC Sweep/Noise. Trong hp Options, chn General settings (thng c chn sn). Thit lp cc thng s theo mu sau:

3.2.3.3.2. Phn tch nhiu (noise) Khi tin hnh phn tch Noise, Pspice s phn tch cho mi tn s c chn trc trong phn phn tch AC analysis/Noise i vi nhng loi nhiu sau:

Nhiu trong linh kin, bao gm nhiu c to ra u ra bi tt c cc in tr v linh kin bn dn trong mch. Nhiu trong cc linh kin bn dn s c chia ra thnh cc nhiu thnh phn mt s v tr thch hp. V d: Diode s c chia ra thnh nhiu rung, nhiu nhit...

Nhiu tng u ra v nhiu tng ng u vo. Nhiu u ra: Gi tr hiu dng ca tng nhiu gy bi cc thit b i vi

u ra. Nhiu u vo: L nhiu tng ng cn thm vo u vo ca mch l

tng (mch khng c nhiu) to ra mt u ra c nhiu bng nhiu u ra( vic ny dng to ra mt mch gn vi mch thc t). tnh c nhiu u vo, Pspice ly nhiu u ra chia cho li mch(t s gia u ra / u vo).

Thit lp phn tch nhiu: Trong hp thoi Simulation settings, chn AC sweep/noise trong hp Analysis

type. Chn General settings trong hp Options. nh du tick vo hp Enable Noise. Thit lp cc thng s cho vic m phng:




Output Voltage: mt bin in p u ra theo dng V(node,[node]), trong node l v tr bn mun tnh tng nhiu u ra.

I/V Source: Tn ca ngun p hay ngun dng c lp m bn mun tnh tng nhiu u vo tng ng.

Interval: in vo tn s th n (n l mt s nguyn dng), ti nhng tn s bn s thy c nhiu do cc linh kin thnh phn, nhng d liu ny c to ra trong file .OUT ca Pspice. Trong ca s Probe, bn c th quan st c tt c nhiu ca linh kin ti tn s ch nh khi thit lp phn tch AC sweep, Thng s Interval khng nh hng ti nhng g Pspice trnh by trn file d liu Probe.

Bm OK lu thit lp cho file m phng.

Sau khi bm Run hoc F11 thc hin m phng, bn chn Add Trace t menu Trace hoc bm vo biu tng chn nhng i lng mun xem dng sng. Bn c th chn cc i lng theo nhng thng s sau:




xem Dng bin u ra nh sau Nhiu rung cho mi linh kin Nhiu vch cho mi linh kin Nhiu nhit cho RB, RC, RE, RD, RG, RS ca cc thit b trn Nhiu nhit to bi cc in tr tng ng u ra ca thit b s Tng nhiu cho mt thit b Tng nhiu u ra cho mt mch Gi tr hiu dng ca tng nhiu u ra cho mt mch Nhiu tng ng u vo ca mch

NFID(tn-linh-kin) NFIB(tn-linh-kin) NSID(tn-linh-kin) NSIB(tn-linh-kin) NSIC(tn-linh-kin) NRB(tn-linh-kin) NRC(tn-linh-kin) NRD(tn-linh-kin) NRE(tn-linh-kin) NRS(tn-linh-kin) NRG(tn-linh-kin) NRLO(tn-linh-kin) NRHI(tn-linh-kin) NTOT(tn-linh-kin) NTOT(ONOISE) V(ONOISE) V(INOISE)




3.2.3.4. Phn tch Transient v Fourier Dng phn tch ny cho php phn tch hot ng ca mch da trn theo thi gian. Phn tch Transient v Fourier c th thc hin cc dng phn tch sau:

Transient: Phn tch in p, dng in v cc trng thi s theo thi gian. Fourier: Phn tch thnh phn mt chiu v phn tch dng sng theo chui

Fourier (theo kt qu ca phn tch Transient). 3.2.3.4.1. Phn tch Time domain (Transient) iu kin thc hin phn tch Time domain (Transient):

Trong mch phi c mt trong nhng ngun c lp bin i theo thi gian sau(ngun ny c th c to ra t cng c Stimulus Editor hoc c ly t th vin linh kin ca Orcad Pspice):

Ly t K hiu Ch gii Stimulus Editor VSTIM

ISTIM DIGSTIM1 DIGSTIM2 DIGSTIM4 DIGSTIM8 DIGSTIM16 DIGSTIM32

Ngun p Ngun dng Ngun m phng s

Th vin Orcad Pspice

VSRC VEXP VPULSE VPWL VPWL_RE_FOREVER VPWL_F_RE_FOREVER VPWL_N_TIMES VPWL_F_N_TIMES VSFFM VSIN ISRC IEXP IPULSE IPWL IPWL_RE_FOREVER IPWL_F_RE_FOREVER IPWL_N_TIMES IPWL_F_N_TIMES ISFFM ISIN DIGCLOCK

Ngun p Ngun dng Tn hiu xung ng h




STIM1 STIM4 STIM8 STIM16 FILESTIM1 FILESTIM2 FILESTIM4 FILESTIM8 FILESTIM16 FILESTIM32

Ngun m phng s File m phng s

Thit lp iu kin u cho cc phn t th ng. Trong mch phi c mt ngun iu khin theo thi gian.

Thit lp m phng Time domain (Transient): Trong hp thoi Simulation settings, chn Time domain (Transient) trong phn

Analysis type. Chn General settings trong phn Options. Thit lp cc thng s cn thit cho m phng. Bm OK lu cc thit lp va ci t.




3.2.3.4.2. Phn tch Fourier thit lp phn tch Fourier bn phi thc hin phn tch Time domain (Transient). Thit lp phn tch Fourier:

Trong hp thoi Simulation settings, chn Time domain (Transient) trong phn Analysis type.

Chn General settings trong phn Options.

Chn trong phn General settings. Trong hp thoi Transient Output file options, tick chn Perform Fourier

Analysis.

Thit lp cc thng s cn thit cho m phng. Bm OK lu cc thit lp va ci t.




Lu khi phn tch Fourier: Phn chu k ly mu trong phn tch Fourier bng bc nhy c ch nh trong

phn tch Transient. (Phn ny c thit lp bi Print values in the output file)

trng thi mc nh, phn tch Fourier s hin th thnh phn DC v t sng hi th nht n sng hi th 9. Nhng bn cng c th thit lp hin th ton b dng

sng hi ca phn tch Fourier bng cch chn biu tng trong ca s Probe ca Pspice A/D khi tin hnh m phng.

3.2.4. Cc dng phn tch nng cao gm nhiu phn tch cng lc Cc loi phn tch nng cao hoc phn tch nhiu thnh phn mt lc nh phn tch Monte Carlo, parametric, temperature, sensitivity/worst-case, s cho kt qu l hng lot cc phn tch DC sweep, AC sweep, transient tu thuc vo loi phn tch c bn m bn chn. 3.2.4.1. Parametric v Temparature Trong dng phn tch ny, Pspice tnh ton cc tham s khc nhau ca mch ti nhng iu kin khc nhau v tham s hay nhit m ngi s dng ch nh. 3.2.4.1.1. Phn tch Parametric (tham s) Phn tch Parametric l kiu phn tch nhiu thnh phn lp i lp li nhiu ln trong khi thay i bin tham s tng (global parametric), bin mu (model parametric), gi tr thnh phn hay nhit hot ng ca mch. Bn c th c c kt qu tng t bng cch m phng mch nhiu ln, mi ln vi nhng bin phn tch khc nhau. iu kin thit lp phn tch Parametric:




Thit lp mch theo cc iu kin sau tu theo bin phn tch c chn: Loi bin phn tch iu kin Voltage source Temperature Current source model parameter global parameter

phi c ngun in p mt chiu (v d VDC) Khng cn iu kin Phi c ngun dng mt chiu (v d IDC) Cc mu c trong PSpice A/D (PSpice A/D model) tham s tng c nh ngha trong Pspice (c file .PARA)

Phi dng mt trong nhng phn tch sau: DC Sweep, AC Sweep, Transient

Analysis. Thit lp phn tch Parametric:


Trong phn Options, nh du tick chn Parametric Sweep. Thit lp cc thng s cn thit cho vic m phng. Bm OK lu cc thit lp m phng.




3.2.4.1.2. Phn tch nhit Phn tch nhit l phn tch mch nhng iu kin nhit khc nhau, nhng nhit ny c th l mt khong nhit hoc mt vi nhit c ch nh trc. Nu khng thit lp cc gi tr nhit cho m phng th vic m phng s c thc hin nhit 27C. Thit lp phn tch nhit :


Chn Temperature trong phn Options. Thit lp cc thng s cn thit phn tch. Bm OK lu cc thit lp va ci t.

3.2.4.2. Monte Carlo v Sensitivity/worst-case C 2 dng phn tch trn u phn tch u ra ca mch da trn s thay i ca cc linh kin (c chn lm tham s bin i) trong gii hn cho php m ngi s dng t ra. Nhng Monte Carlo th phn tch theo s thay i ngu nhin ca linh kin, cn Sensitivity/worst-case th phn tch theo s thay i ca linh kin theo tng gi tr, c th phn tch theo s thay i ca tng linh kin mt hoc phn tch tng hp tt c cc gi tr thay i ca linh kin cng 1 ln.




3.2.4.2.1. Phn tch Monte Carlo Phn tch ny s cho bit p ng ca mch vi nhng sai s trong gii hn cho php ca linh kin khi thc hin cc phn tch nhiu thnh phn, v c th thc hin vi nhiu loi phn tch khc nhau (AC, DC, Transient). Trc khi tin hnh phn tch bn phi thit lp cc thng s mu cho linh kin v cc sai s ca linh kin. Vic phn tch ny s to ra rt nhiu tham s lm cho file u ra rt ln, nn rt kh cho vic add Trace cng nh d liu file u ra ln s lm cho vic phn tch b chm li kh nhiu. Thit lp phn tch Monte Carlo:

Trong hp thoi Simulation settings chn mt loi phn tch no trong phn Analysis type.

Trong phn Options, chn Monte Carlo/Worst-case. Chn More settings.

Chn danh sch gi tr cc tham s mu. Chn OK lu cc thit lp trn.

Chc nng lu tham s phn tch ca Monte Carlo: (history support) Chc nng ny s gip bn lu cc tham s phn tch bi cc chng trnh

phn tch Monte Carlo vo mt file no , sau ny bn c th ly ra dng li khi thc hin cc phn tch tip theo.

Chc nng ny cng cho php bn thc hin so snh kt qu ca 2 phn tch Monte Carlo bng cch thay i mt hay nhiu gi tr tham s no . Vi loi phn tch ny th cc thng s ngu nhin c gi nguyn.

lu cc file phn tch ny, bn lm nh sau: Sau khi chn phn tch Monte Carlo/ worst case trong phn Options, bn

bm vo nt MC Load/Save.




Trong hp thoi Load/Save Monte Carlo Parameter file, tick chn Save parameter values in filename.

Sau t tn v chn ng dn ti file lu kt qu. Bm Ok lu cc thit lp ca bn.

s dng li mt kt qu c sn ca phn tch trc, bn lm nh sau: Sau khi chn phn tch Monte Carlo/ worst case trong phn Options, bn

bm vo nt MC Load/Save. Trong hp thoi Load/Save Monte Carlo Parameter file, tick chn

Load parameter values in filename.




Chn ng dn ti file kt qu cn dng, file kt qu ny phi c ui l .mcp.

Bm OK lu cc thit lp ca bn. 3.2.4.2.2. Phn tch Worst case Phn tch Worst case dng tm nhng p ng u ra ca mch da trn nhng iu kin gii hn ca cc tham s ca n. Mt s lu khi thc hin phn tch ny:

u vo (Input): Phi m bo y cc thng s sau: Dung sai ca tham s. Thng s cho trng hp xu nht (worst case).

Phn tch ny khng phi thc hin vi mt tp hp nhiu thng s m ch thc hin vi trng hp tt c cc tham s ca mch b y n gii hn cao nht.

Thit lp phn tch Worst case: Trong hp thoi Simulation settings chn mt loi phn tch no trong phn

Analysis type. Trong phn Options, chn Monte Carlo/Worst-case. Tick chn vo Worst-case/Sensityvity. Thit lp cc thng s cho m phng. Bm OK lu cc thng s va thit lp.




3.2.5. M phng s M phng s l m phng nhng p ng ca linh kin s theo thi gian. Vic ny c Pspice thc hin theo phn tch Transient. Nu tnh ton im phn cc th Pspice cng xem linh kin s nh nhng linh kin tng t trong mch. Cc u vo s c dng trong m phng s: Nu mun to u vo s t cng c ...

Th s dng thnh phn ... Cho nhng loi u vo s c th sau ...

Dng Stimulus Editor Dng cc linh kin trong Library

DIGSTIMn DIGCLOCK STIM1 STIM4 STIM8 STIM16 FILESTIM1 FILESTIM2 FILESTIM4 FILESTIM8 FILESTIM16 FILESTIM32

ngun tn hiu hoc bus tn hiu ng h tn hiu kch thch 1 bit tn hiu kch thch 4 bit tn hiu kch thch 8 bit tn hiu kch thch 16 bit tn hiu kch thch dng file 1 bit (1 bit file based) tn hiu kch thch dng file 2 bit (2 bit file based) tn hiu kch thch dng file 4 bit (4 bit file based) tn hiu kch thch dng file 8 bit (8 bit file based) tn hiu kch thch dng file 16 bit (16 bit file based) tn hiu kch thch dng file 32 bit (32 bit file based)

Thit lp mt m phng s:

Trong hp thoi Simulation settings, chn tab Analysis, chn Time domain (transient) trong hp Analysis type.

Thit lp thng s cn thit cho m phng.




Trong tab Options ca hp thoi Simulation settings chn Gate-level simulation.

Bm OK lu cc thit lp va ci t. 3.3. V d 3.3.1. V d m phng mt s mch tng t 3.3.1.1 . M phng mt mch theo phn tch DC 3.3.1.1.1. DC Sweep Thc hin qut DC vi mch K, chn thng s qut l ngun p mt chiu Vin vi gii hn qut t -10 n 20 V, bc nhy 1V.




V

V

R133k

R32.2k

R41k

R210k

V29V

R51k

out

0

0Q2

Q2N2222

in

Vin0

Thit lp Simulation settings nh sau:




Dng sng c c sau khi m phng nh sau:

3.3.1.1.2. DC Sweep/ secondary sweep Thc hin qut th cp vi mch sau:

V

V

R133k

R32.2k

R41k

R210k

V29V

R51k

out

0

0Q2

Q2N2222

in

Vin0




3.3.1.1.3. H c tuyn v ng ti M phng biu din c tuyn ca BJT Q2SC945:

Q1

Q2SC945V10Vdc

V20Vdc

0

Chn ngun s cp V1 : Start value: 0V End value: 1V Increment: 0.01V Chn ngun th cp V2: Start value: 0V End value: 5V Increment: 0.01V





T menu Trace-> Add trace, nhp vo khung Trace Expression phng trnh ng ti nh sau: (5V-V_V2)/50 vi ti c gi tr 50 Kt qu m phng nh sau:




3.3.1.2 . M phng mt mch theo phn tch bias point (im phn cc) 3.3.1.2.1. Phn tch Bias point Phn tch Bias point mch sau :

RBIAS20k

RS2

1k

RS1

1k

Q1Q2N2222

Q2Q2N2222

Q3Q2N2222

Q4Q2N2222

C1

5p

out2out1

V1

V2

12V

V3

-12V

00

VEE

VDD

VEE

VDD

R11k

R21k

0 Thit lp Simulation settings nh sau:




Kt qu c c sau khi m phng nh sau:

3.3.1.3. M phng mt mch theo phn tch AC/Noise 3.3.1.3.1. Phn tch AC Sweep Thc hin phn tch AC Sweep i vi mch sau:

C1

0.1u

C31n

V1

AC = 1VTRAN =

DC = 0V

R16k

R33k

R41k

R22k

V210V

R51k

0

0

Q2

Q2N2222

C4

0.1u

out

V





Trong hp thoai Simulation setting chn AC sweep/Noise trong khung Analysic type.

Chn Logarithmic trong AC Sweep type sau nhp gii tn s cn qut vo, ch l tn s bt u phi >= 1 HZ.

Nn chn bin tn hiu vo l 1V nu chn thang o logarit. Chn: Start frequency: 1HZ End frequency : 100kHZ Points/ decade : 300





3.3.1.3.2. Phn tch nhiu AC/Noise Thc hin phn tch nhiu cho mch sau:

C1

0.1u

C31n

V1

AC = 1VTRAN =

DC = 0V

R16k

R33k

R41k

R22k

V210V

R51k

0

0

Q2

Q2N2222

C4

0.1u

out

V

Thit lp Simulation settings cho phn tch nhiu:

Trong hp thoi Simulation setting chn AC sweep/ Noise trong khung Sweep type. Chn Enable trong khung Noise analysis, cc thng s ca Noise analysis:

Output Voltage: u ra cn xc nh nhiu, c dng V(node,[node]). I/V Sources: Tn ca ngun dng hoc ngun p u vo cn xc nh nhiu. Interval:




3.3.1.4 . M phng mt mch theo phn tch trong min thi gian Thc hin phn tch trong min thi gian (Time domain Transient) i vi mch sau:






3.3.1.5. Phn tch Monte Carlo v Sensitivity/worst case (phn tch nhy) 3.3.1.5.1. Phn tch Monte Carlo Thc hin m phng theo phn tch Monte Carlo mch sau:

Q2Q2N2222

Q1Q2N2222

RS1

1k

RS2

1k

RBIAS20k

Q4Q2N2222

Q3Q2N2222

C1

5p

out2out1

V1

V3

-12V

V2

12V

0

00

VEE

VDD

VEE

VDD

RC1

CRES1k

RC2

CRES1k




Bn c th thc hin phn tch da trn s bin i gi tr in tr RC1 v RC2 bng cch thit lp gi tr cho cc in tr ny l cc bi s gm 5% sai s ca linh kin trn tham s ca R. u tin bn thc hin mt phn tch DC Sweep vi cc gi tr l bi s ca RC1 v RC2. Sau biu din mt tp hp cc gi tr RC1, RC2 bin i c lp trong khong sai s l 5%. Thit lp gi tr nh sau:

Thay RC1 v RC2 vi thnh phn RBREAK t th vin BREAKOUT.OLB, thit lp gi tr cho in tr (VALUE=10k) v thit lp quy chiu cho n tr ti tn ca bin RC1 v RC2.

Chn mt thnh phn RBREAK v chn Pspice Model t menu Edit, ca s Model Editor hin ra.

To ra mt CRES bng cch thay th on m sau .MODEL CRES RES( R=1 DEV=5% TC1=0.02 + TC2=0.0045) vo ch c on m .model Rbreak RES R=1 . Trong TC1 l h s nhit tuyn tnh, TC2 l h s nhit phi tuyn.

T menu File ca Model Editor, chn Save. Trnh editor ny s t ng kt ni CRES vo thnh phn RBREAK bng cch cp nht nhng tnh cht b sung cho linh kin.

Kch p chut vo thnh phn RBREAK hin th spreadsheet ca linh kin. Trong hp c tn IMPLEMENTATION i li thnh CRES, ri kch Apply. ng spreadsheet li.

Thit lp simulation settings cho phn tch Monte Carlo nh sau:




Dng sng m phng nh sau :




Xut ra dng file nh sau :

3.3.1.5.2. Phn tch Sensitivity/worst case Thc hin m phng mch sau :

C1

1u

V1

AC = 1VTRAN =

DC = 0V

Rb110k

Rc1k

Rb2720

V210V

RL1k

0

0

Q2

Q2N2222

Cout

1u

out




Thit lp simulation settings :

Kt qu nh sau :




3.3.1.6. Phn tch Parametric v nhit 3.3.1.6.1. Phn tch Parametric Thc hin phn tch mch sau :

Q1

Q2SC4444

V112VdcR1

560

R2100k

R356k

C1

100uFC2

100uF

Out

V2

FREQ = 1khzVAMPL = 0.5VVOFF = 0V

R450

R5150C3

220u

0 Thit lp simulation settings nh sau :




Dng sng ng ra nh sau :




3.3.1.6.2. Phn tch nhit Cng vi mch trn bn thc hin phn tch nhit . Thit lp simulation settings nh sau:

Ta m phng 25C kt qu V(out) nh sau :




Ta tin hnh m phng 150C kt qu nh sau :




3.3.2. M phng mt mch s Thc hin m phng mt mch gii m 3 sang 8 nh sau:

Thit lp simulation settings nh sau:




Kt qu nh sau:


1. D Nguyn Hong Anh 2. L Hng Hi 3. Ng Vy Hu 4. Nguyn Th Qunh Trang 5. Trn Nguyn Cm T 6. Bp Ph Vng Vilayphon 7. Nguyn Hong V 8. Trn Anh Phng


OrCAD Capture: L Hng Hi

Ng Vy Hu OrCAD Layout: Nguyn Th Qunh Trang

Trn Nguyn Cm T Trn Anh Phng OrCAD Pspice: D Nguyn Hong Anh BpPhVng Vilayphon Nguyn Hong V Bin tp Word: D Nguyn Hong Anh Trnh by Slide: Trn Nguyn Cm T Thit k ba: Nguyn Hong V


TRNG I HC BCH KHOA NNG KHOA IN T-VIN THNG

Thc hin: Nhm 1 04T1 Nng, thng 11 nm 2007

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