IC-CAD 실험IC CAD 실험Lecture 3

장 재 원

주문형 반도체(ASIC*) 설계 흐름도 개요Lecture 2 REVIEW

ASIC Spec.

Lecture 2 REVIEW

Behavioral-leveldesign

Structural-leveldesign

Front-enddesign

design

Logic synthesis Schematic editorTransistor-level

design

Logic design*Analog 회로 설계시

Netlist FPGA구현검증

Auto P&Rlayout

Full-customlayout

Layout verification(LVS, DRC, ERC)

Back-enddesign

Post-simulation

GDS file

Layout 설계

Fabrication &testing

*ASIC(Application Specific Integrated Circuit)

Verilog HDL 코드 예 : 4비트 카운터Lecture 2 REVIEW

module counter(rst, clk, load, enb, din, dout) ;input rst, clk, load, enb;

[ ]

Lecture 2 REVIEW

input[3:0] din;output[3:0] dout;

[3 0] treg[3:0] tmp;

always@(posedge clk or negedge rst)beginbegin

if (~rst)tmp <= 0;

else if (load)else if (load)tmp <= din;

else if (~enb)tmp <= tmp + 1;tmp < tmp + 1;

endassign dout = tmp;

endmoduleendmodule

Verilog HDL 코드 예 : 8비트 카운터Lecture 2 REVIEW

module counter(rst, clk, clr, direct, load, enb, din, dout) ;input rst, clk, load, enb, clr, direct;

[ ]

Lecture 2 REVIEW

input[7:0] din;output[7:0] dout;

[7 0] treg[7:0] tmp;

always@(posedge clk or negedge rst)beginbegin

if (~clr)tmp <= 0;

if (~rst)if (~rst)tmp <= 0;

else if (load)tmp <= din;tmp < din;

else if (~enb)if(~direct) tmp <= tmp + 1;else tmp <= tmp - 1;else tmp < tmp 1;

endassign dout = tmp;

endmodule

Synchronous & Asynchronous

SynchronousClock의동작에맞추어, positive clock일경우해당값에따라동작

clkalways@(posedge clk)begin

if (~rst)

rst

clk

val

Asynchronous

tmp <= 0; reset resetval

Clock에상관없이값이변하면바로동작always@(posedge clk or negedge rst)b i

always@(negedge rst)b ibegin

if (~rst)tmp <= 0;

begintmp <= 0;

Verilog HDL 코드 예 : 테스트 벤치Lecture 2 REVIEW

`timescale 1 ns/1 nsmodule tb_cnt ;

#5000load = 1; din = 4'b1101;

Lecture 2 REVIEW

reg rst, clk, load, enb;reg[3:0] din;wire[3:0] dout;

#500load = 0;#500

b 1counter cnt(rst, clk, load, enb, din, dout);

initial begin

enb = 1;#500enb = 0;

endinitial beginclk = 0;forever #50 clk = ~clk;

end

endendmodule

end

initial beginrst = 0; load = 0; din = 4'b0; enb = 1;rst 0; load 0; din 4 b0; enb 1;#1001rst = 1;#1000#1000enb = 0;

Verilog HDL 코드 예 : 테스트 벤치Lecture 2 REVIEW

`timescale 1 ns/1 nsmodule tb_cnt ;

#5000load = 1; din = 8'b11010010;

Lecture 2 REVIEW

reg rst, clk, load, enb, clk, direct;reg[7:0] din;wire[7:0] dout;

#500load = 0;#500

b 1counter cnt(rst, clk, clr, direct, load, enb,

din, dout);initial begin

enb = 1;direct = 1;#500enb 0;initial begin

clk = 0;forever #50 clk = ~clk;

end

enb = 0;#1050clr = 0;

endend

initial beginrst = 0; load = 0; din = 8'b0; enb = 1;

endendmodule

rst 0; load 0; din 8 b0; enb 1; direct = 0; clr = 1;#1001rst = 1;rst 1;#1000enb = 0;

do파일

vlog.dovlog /hdl design/source/counter v

Testbenchvlog ~/hdl_design/source/counter.vvlog ~/hdl_design/source/tb_cnt.v

vsim -c tb cnt -wlf

Counter

vsim c tb_cnt wlf /home2/commasic/asic_course/train20/hdl_design/results/sim/tbwave.wlflog -r *log r run 10000 nsquit

wav.dovsim -view /home2/commasic/asic_course/train20/hdl_design/results/sim/tbwave.wlf

add wave *dd / t/tadd wave /cnt/tmp

HDL 시뮬레이터(Modelsim) 사용Lecture 2 REVIEW

vlib : 라이브러리디렉토리의생성vlib 경로/작업디렉토리명

log[-r] * : 시뮬레이션결과파형에지정된신호의파형을실어주는역할

Lecture 2 REVIEW

vlib 경로/작업디렉토리명

vmap : 작업디렉토리에대한환경설정vmap 라이브러리명 경로/작업디렉토리명

신 의파형을실어주는역할[-r] 옵션을사용하면테스트벤치 & 내부모듈의신호까지포함됨

log 인스턴스명/신호명vmap 라이브러리명 경로/작업디렉토리명

vlog : Verilog HDL 파일의컴파일vlog [ work 라이브러리명] 경로/verilog파일

log /T1/S1/test

run [시뮬레이션시간] : 기록한시간동안vlog [-work 라이브러리명] 경로/verilog파일

vsim : HDL 시뮬레이터의명령수행옵션 : c do do파일 L 라이브러리명

시뮬레이션실행

add wave * : 테스트벤치에있는모든신옵션 : -c, -do do파일, -L 라이브러리명, -sdf{min|typ|max}, -wlf 경로/wave파일, -view 경로/wave파일

vsim –c –do sim.do

호의파형을보여주는명령add wave /T1/*

quit : 시뮬레이터의종료

논리회로 합성

Synthesis상위수준코드로부터게이트수준네트리스트를생성하는절차

O ti iOptimize기능, 속도, 면적요건을만족하기위해라이브러리셀을이용하여최적의회로를만드는합성과정상의한단계적의회로를만 는합성과정상의한단계

Compilep최적화를수행하는명령으로이를수행하기위해서는일단디자인을읽어들인후필요한작업들을처리한후컴파일러명령을수행한다 그러면게이트수준네트리스트(netlist)가생성된다다. 그러면게이트수준네트리스트(netlist)가생성된다

Design Compiler를 이용한 synthesis 과정

<참고자료>Design Compiler User Guide

디자인 읽기

analyzeReads an HDL source file

Checks it for errors (without building generic logic for the design)

Creates HDL library objects in an HDL-independent intermediate format

Stores the intermediate files in a location you define

elaborateTranslates the design into a technology-independent design (GTECH) from the

intermediate files produced during analysis

Allows changing of parameter values defined in the source codeAllows changing of parameter values defined in the source code

Allows VHDL architecture selection

Replaces the HDL arithmetic operators in the code with DesignWare components

Automatically executes the link command, which resolves design references

readReads several different formats

Performs the same operations as analyze and elaborate in a single stepPerforms the same operations as analyze and elaborate in a single step

Creates .mr and .st intermediate files for VHDL

Does not execute the link command automatically

Does not create any intermediate files for Verilog (However, you can have the read_file command create intermediate files by setting the hdlin auto save templates variable to true)setting the hdlin_auto_save_templates variable to true)

설계제약 조건 설정

operating conditionswire loadsI/O port requirements

set_operating_conditions

timing constraintsarea constraints

set_drive

set_load

design rule constraintsset_driving_cell

set_wire_load

set_fanout_load

Operating Conditions

set_operating_conditionsdc_shell> set_operating_conditions WCCOM -lib classdc_shell> report_lib class

Wire Loads

top (default 설정) 레벨에서정의된 i l d 모델을모두사용top 레벨에서정의된 wire load 모델을모두사용

enclosed배선을완전히포함하는가장작은디자인의 wire load 모델사용배선을완전히포함하는가장작은디자인의 wire load 모델사용

segmented세그먼트를둘러싸는디자인의 wire load 모델사용

30X3020X20

50X50

mode = enclosed

50X50 30X3020X20

50X50 50X50

mode = top mode = segmented

30X3020X20

50X50

30X3020X20

50X50 30X3020X20

I/O port Requirements

set_drive공정라이브러리의셀로입력포트구동능력이기술될수없을때최상위레벨포트의구동저항공정라이브러리의셀로입력포트구동능력이기술될수없을때최상위레벨포트의구동저항을정해준다

set_driving_cell공정라이브러리의셀로만들어진포트의구동특성을나타내기위해사용한다공정라이 러리의셀 만들어진 의구동특성을나타내기위해사용한다

set_load입력과출력포트에서의캐패시턴스값을정한다

set fanout loadset_fanout_load출력포트의팬아웃을결정

set_driveU1

set_driving_cell

top_level_design

U2

I3

I4

IV

AN2

logic

I1

I2

PAD

PAD1.5

1.5

U1

ExternalSystem

sub_designsub_design

Timing Constraints

create_clockdc shell> create clock -period 50 -waveform {0 30} CLKdc_shell> create_clock period 50 waveform {0 30} CLK

set_clock_skewdc_shell> set_clock_skew -plus_uncertainty 0.2 -minus_uncertainty 0.2 {CLK}

set input delayset_input_delaydc_shell>set_input_delay 20 -clock CLK {DATA_IN}

set_output_delayd h ll> d l 15 l k CLK {DATA OUT}dc_shell> set_output_delay 15 -clock CLK {DATA_OUT}

Area Constraints

set_max_aread h ll 100dc_shell> set_max_area 100타이밍과면적제약조건을모두설정되어있으면컴파일할때타이밍이우선적으로고려

Design Rule Constraints

set_max_transition명시된포트에연결되어있는배선이나디자인의모든배선의최대천이시명시된포트에연결되어있는배선이나디자인의모든배선의최대천이시간을설정

set_max_fanout허용가능한최대의팬아웃(fanout)을설정

set_max_capacitancei i 은실제적인배선의캐패시턴스를제한하지는않으므로 set_max_transition은실제적인배선의캐패시턴스를제한하지는않으므로,

이를위해서 max_capacitance 설정

Multiple Instance의 Resolve

uniquify각각의 i 를복사한다각각의 instance를복사한다uniquify를하면중복되어사용되는 instance가복사되어생성

각각을특성화할경우사용

ungroup계층구조를없애고하나의이름으로모든셀에대해최적화를한다각각을특성화하지않을경우 명령을실행후컴파일각각을특성화하지않을경우 ungroup 명령을실행후컴파일

set_dont_touch각서브디자인을재합성할때변경하지않으려면각서브디자인을컴파일한후 set_dont_touch 명령사용

디자인 옵션

map effort : medium

verify design : low

allow boundary optimization : yes

TOP LEVEL TOP LEVEL

LOG

X

Block1 Block2

BA

LOG

X

Block1 Block2

BA

GIC

GIC

실험내용

Page 53~63

리포트 및 공지사항

리포트제출P63~64의실험과제및프로젝트P63~64의실험과제및프로젝트

수정사항 : P64 모듈1 의클럭주파수 : 100 Mhz(10ns)2장에서작성한 verilog 코드가합성이안되면코드를수정할것

옵션 절 주어진 을만족시키지못하면 를수정하여 을맞추옵션조절로주어진 spec.을만족시키지못하면 verilog 코드를수정하여 spec.을맞추도록노력할것

코드를수정했다면, 수정한코드를첨부하고수정사항및개선사항에대한고찰을작성할것작성할것

리포트의종이인쇄본을제출할것

제출기한 : 다음수업시작전까지

조교(장재원) e-mail 주소jaera82@soc.yonsei.ac.kr