A 2.2mW, Continuous-Time Sigma-Delta ADC for Voice Coding with 95dB Dynamic Range in a

65nm CMOS Process

Lukas Dörrer, Franz Kuttner, Andreas Santner, Claus Kropf, Thomas Hartig, Patrick Torta, Patrizia Greco Infineon Technologies Austria AG

Villach, Austria lukas.doerrer@infineon.com

Abstract— A second order continuous time multibit (4bit) ∆Σ-ADC for voice coding is implemented in a 65nm CMOS process. The dynamic range (DR) is 95dB over the voice bandwidth of 20-20 000Hz. Furthermore, by using a feed back architecture the need of an anti aliasing filter is eliminated. The input operational amplifier is chopped to eliminate flicker noise and offset. These improvements give way to a substantial simplification of the analog front end by allowing the absorption of the pre-amplifier and the anti-aliasing filter into the ∆Σ-ADC. Thanks to the feedback structure the slew rate at the quantizer is limited and a power-efficient tracking ADC can be used. The total harmonic distortion (THD) is below -77dB at maximum input signal of 1.4Vpp. The ADC consumes 2.2mW from a 1.2V supply when clocked at 12MHz. The active area is 0.149 mm².

I. INTRODUCTION Sigma delta (∆Σ)-ADCs are often used in audio

applications to achieve high resolutions at low bandwidth signals. Battery powered systems like mobile telephones require a low power solution. Although continuous time sigma delta (CT∆Σ)-ADCs offer the possibility to convert voice with extreme low power consumption, they suffer from the high sensitivity to clock jitter.

The circuit presented in this paper reduces the jitter sensitivity and demonstrates a way to build a low power ADC with high dynamic range, low input noise floor, high THD at adequate area.

A typical input stage of a mobile telephone voice coder is seen in Fig. 1. It consists of a preamplifier, an anti aliasing filter and discrete time-∆Σ-ADCs.

Fig. 1 Block diagram of a voice coder

The presented solution takes advantage of the inherent anti aliasing filter functionality of the CT∆Σ-ADC, which allows to absorb the prefilter and even the preamplifier

into the first integrator [1]. Therefore the system can be optimized by connecting the ADC directly to the microphone, at the price of a higher performing ADC with high resolution and a low noise input stage.

In Sec. III, the circuit implementation is described. The loop filter implementation is explained in Sec. IIIA and methods to reduce the noise with adequate area are highlighted. Sec. IIIB describes a low noise large THD DAC. In Sec. IIIC, a low area and low power architecture of the quantizer is shown.

II. SYSTEM CONSIDERATIONS Fig. 2 shows the architecture of the presented CT∆Σ-

ADC. The loop filter circuit is a second order filter with two integrators. The quantizer is a 4bit tracking ADC which is very efficient in terms of power and area. The DAC in the first and second stage consist of 15 differential current steering DAC cells.

Fig. 2: 2nd order 4bit CT-architecture

The oversampling ratio was chosen to be at OSR=300. This results in a clock frequency of 12MHz and an analog bandwidth of 20kHz. Large OSR reduces the area of the capacitors but enhance the requirements for the DC-gain of the operational amplifier [2].

In comparison to a feedforward (FF)-structure, the implemented feedback (FB)-structure reduces the power consumption of the ADC. In an FF structure there is only one loop and any additional delay of the blocks (DAC, integrators …) decreases the stability of the loop. To achieve a low noise input stage large operational amplifier transistors and large integration capacitors are required. The parasitic capacitances increase the excess loop delay

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and lower the stability. On the other hand, the stability in the FB-topology is affected by the inner loop (DAC2, integrator2, quantizer). The outer loop (DAC1, integrator1, integrator2, quantizer) is less sensible to delay in terms of stability. As a result the bandwidth of the first integrator is reduced, which lowers considerably the current consumption.

Thanks to the pre-shuffling DEM technique [3] where the largest part of the digital feedback signal is already shuffled in advance, the loop delay of the inner loop can be kept small.

Comparing the FF- with the FB-topology, the FB-structure has a better out of band signal suppression [4]. The filter was designed to have a signal transfer function (STF) which approximates a second order butterworth filter with a 3dB-bandwidth of 1.4MHz. The filter acts as an anti-aliasing filter for the following quantizer. The STF of the FB-topology decreases beyond the 3dB corner frequency with -40dB/decade which is typical for a 2nd order feedback architecture.

High STF out of band attenuation results in a low 3dB corner frequency. For a given noise limited input resistor R1, a low frequency pole results in a large input capacitor C1. That is a trade off between a low input capacitance (area) and high out of band attenuation.

As can be seen in the ADC layout (Fig. 10), the quantizer is much smaller than the second integrator and DAC. In this design it is more area efficient to use 2nd order multibit design than a high filter order single bit structure.

The multibit quantizer was selected to reduce the jitter sensibility of the ADC. The jitter of the ADC clock increases the inband noise floor of the output spectrum and will degrade the dynamic range. Using a multibit DAC instead of a single bit one, will relax the jitter requirements of the ADC to 100ps.

III. I. ANALOG IMPLEMENTATION

A. Loop Filter, Integrators: All analog modules of the converter are implemented

fully differentially. The whole architecture was optimized at system level to achieve the required stability and SNR with minimum gain bandwidth (GBW) and DC-gain (A0) of the amplifiers. For system simulations the operational amplifiers were described using a two pole model (GBW, A0) which included the parasitic capacitances at the virtual ground.

The thermal and flicker noise floor of the modulator is determined by the noise contributions of the DAC, the input resistor and the first operational amplifier. In this design, the required dynamic range of more than 90dB is achieved using an input resistor of 8kΩ.

In new technologies the transistor flicker noise is getting worse [5]. The flicker noise can be reduced by increasing the area of the input stage transistors of the operational amplifier. This high dynamic range requires a low noise floor and a large area of the first operational amplifier. Keeping the area of the integrator small, the first

stage of the first operational amplifier has to be chopped to reduce flicker noise and offset (Fig. 3) [ 6]. By switching the first stage alone, the output of the first integrator produces less switching noise which results in a lower noise floor.

The linearity of DAC1 and the first integrator limits the linearity of the whole ADC. The DC-gain A0 of the operational amplifier determines the linearity of the integrator. In this technology, the transistor’s output conductance is very poor. Therefore, a simple operational amplifier has a DC-gain of about 30dB. This low DC-gain decreases the total harmonic distortion. A cascode in the input stage boost the DC gain to more than 50dB.

Fig. 3 Operational Amplifier of the 1st integrator

The time constant of the RC-Integrator is determined

by the absolute value of the resistor and the capacitor, which can vary in the range of ±30%. Due to the high oversampling ratio and the multibit quantizer, the quantization noise floor is more than 20dB lower than the thermal noise floor. Due to the large difference between the quantization noise and all other noise contributors, any variation of the coefficients will not degrade the dynamic range. Therefore, no tuning of the coefficients is necessary.

B. Multi bit DAC: The first DAC is the most critical part of the whole

ADC. Any nonlinearity or noise will be added to the input signal. This noise cannot be distinguished from an input signal and therefore cannot be suppressed by CT∆Σ loop. This lowers the SNR of the ADC. The static mismatches of the current source transistors (MP, MN) in the DAC current cells cause nonlinear distortion (Fig. 4). This effect can be reduced by the dynamic element matching block (Fig. 2). This block randomizes the signal dependent harmonics and converts them into white noise. In addition to the static mismatch errors, there are additional dynamic switching effects which create spurious frequencies. Due to the mismatch in the rising and falling edges in a fully differential NRZ-DAC, harmonics will occur and lowers the total harmonic distortion (THD),[7]. To eliminate this effect, a return to zero (RZ)-code is implemented in the first DAC. Because of the noise shaping effect in the second stage, the nonlinear effects in the second DAC are not critical anymore. Therefore, a simple non return to zero (NRZ) is implemented in the second stage.

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Fig. 4 Implementation of one DAC cell

The flicker and thermal noise of the DAC must be low

to implement an ADC with a wide dynamic range. Low noise and matching requirements lead to a long shaped current transistor with an high overdrive voltage. To keep the area of the DAC small, the width of the current transistor is not increased proportional to the length and the saturation voltage rise. Due to the increased saturation voltage of the current transistor, there is no voltage headroom for a cascode transistor anymore.

One of 15 DAC-cells of the first and second DAC is shown in Fig. 4. When the DAC clock (clk_dac) is low the latch of the DAC cell changes the state. The nand gate isolates the changing latch output signal from the current cell. During this time the output current I(outp), I(outn) of the DAC is switched off. When the new state has settled, the DAC clock goes high and switches the nand gate transparent. The DAC output current is switched on to +I or –I, depending on the new latch output code dat. During the time that the DAC current is switched off, the current is bypassed via the transistors MPB, MNB. In the second DAC stage, there is a NRZ-DAC. Therefore, the clk_dac is always switched on. This lowers the dynamic current consumption and the excess loop delay.

C. 4bit Quantizer The 4bit quantizer is implemented by a tracking ADC

with 3 comparators (Fig. 5), [3]. It consists of the three comparators, a counter, an R-string reference ladder and a switching matrix to connect the reference voltage to the comparator’s inputs. For small input changes, only the middle comparator will make the decision. The state of the counter will be unchanged. For signals larger than one LSB, one of the adjacent comparators will change the state. The logic will detect this situation and increase or decrease the counter.

The tracking ADC has an inherent maximum slew rate limitation. The quantizer must track the input signal. If the slew rate of the quantizer input voltage is too high, the quantizer will fail. Therefore, the maximum input slope of the quantizer input signal has to be limited.

In comparison to a feedforward filter structure, the feedback-structure has an important advantage: Signals, higher than the corner frequency of the signal transfer function (STF) are better suppressed. In addition, the feed back structure has no peaking in the STF [4]. The band limited behavior of the STF avoids the appearance of high slew rate quantizer input signals even at full scale high

frequency out of band signals. As a result, the tracking quantizer allows higher out of band signals with feedback filter structure in comparison to a feed forward structure.

Fig. 5 Three comparator tracking ADC (4bit)

IV. MEASUREMENT RESULTS Measurement results are shown in Fig. 6 to Fig. 8. The

clock frequency is 12MHz. Fig. 6 depicts the measured output spectral density plot for an input sine wave of 4.85kHz at an input amplitude of -4dBFs (Fs=1.4Vpp). the chopper frequency is at 46kHz. Fig. 7 shows the idle channel noise (ICN) measurement with chopped first stage of the filter. At low frequencies the noise floor increases due to the 50Hz hum and the flicker noise. The integrated inband noise is -95dB. The remaining flicker noise shown in Fig. 7 is caused by the DAC and the input resistor. Chopping creates no idle tones within the band of interest. The SNR, the SNDR and the THD are depicted in Fig. 8 as a function of the input-signal amplitude. The peak SNR of 77dB is achieved with an input signal of 0dBFs. The noise increase when the signal generator (Audio Precision, Cascaded Two System) is connected to the . This limits the DR to -90dB.

Fig. 6 Measured Output Spectrum; N=131072

The die micrograph and the layout of the ADC core are

shown in (Fig. 9) and (Fig. 10). The core area is 465µm*328µm (0.149mm2). It can be clearly seen that the chip size is pad limited. The area not occupied by the ADC core is filled with capacitors. The area used for decoupling the voltage supply. Due to noise requirements, the first integrator (41%) and the first DAC (14.5%) consume more than half of the area. The second integrator is completely surrounded by the first stage. The area of the quantizer is much smaller than the area of second integrator. That

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confirms the assumption that the area can be reduced by replacing the third integrator stage by a tracking quantizer.

Fig. 7 Measured idle channel noise spectrum with

chopping fchopp = 46kHz

Fig. 8 SNR, SNDR THD versus signal level

Fig. 9 Chip micrograph

V. CONCLUSION A continuous time 2nd-order multi-bit (4bit) Σ∆ ADC

for audio applications has been implemented. It contains a feedback topology with a chopped first operational amplifier and a tracking quantizier and a RZ-DAC in the first stage. Thanks to this topology the ADC can directly process the microphone input signal without the need of any preamplifier or anti-aliasing filter which leads to considerable ar and power saving of the system. A performance summary is shown in Table 1.

456um

328u

m

INT1INT2

DAC1 DAC2

QUANT

BIA

SD

IGITA

LR

EF

Fig. 10 Layout of the ADC core

Table 1 Performance Summary

Power consumption 2.2mW at 1.2V Signal bandwidth 20-2000Hz

Sampling frequency 12MHz Oversampling ratio 300

Dynamic range 95dB Peak THD 82dB Peak SNR 77dB

Peak SNDR 74dB Core area 0.149 mm2

CMOS Technology 65nm lp, P1M1M6 Max. diff. input level 1.4Vpp (0dBFS)

VI. AKNOLWEDGEMENTS

The authors would like to thank Manfred Punzenberger and Mario Motz for valuable discussions.

REFERENCES [1] E. van der Zwan E. Dijkmans, “A 0.2-mW CMOS Σ∆ Modulator for Speech Coding with 80 dB Dynamic Range” IEEE J. of Solid State Circuits, vol.31 No. 12, December 1996 [2] A. Rodríguez-Vázquez, F. Medeiro, ”Low Pass Sigma-Delta Modulators: Continuous-Time Sigma Delta Modulators”, http://www.imse.cnm.es/esd-msd/PUBLIC_DELIV/MIXMODEST/CT_SDM_overview.PDF [3] L. Dörrer, F. Kuttner, P. Greco, P. Torta, T. Hartig “A 3mW 74dB SNR 2 MHz Continuous Time Delta Sigma ADC with a Tracking-ADC-Quantizer in 0.13µm CMOS”, IEEE Journal of Solid–State Circuits, vol. 40, no.12, pp.2416-2427, Dec. 2005 [4] L. Breems, J. H. Huijsing “Continuous-Time Sigma Delta Modulation For A/D Conversion in Radio Receivers”, Kluwer Academic Publishers, Boston, 2001 [5] H. Eul “ICs for Multimedia Communications”, Proc. of IEEE Solid-State Circuits Conference, San Francisco, Feb. 2006 [ 6] C. Enz, G. Temes “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization”, Proceedings of IEEE, Nov. 1996 [7] M. Clara, A. Wiesbauer, W. Klatzer, “Nonlinear Distortion in Current-Steering D/A-Converters due to Asymmetrical Switching Errors”, Proc. of Int. Symposium on Circuits and Systems, May 2004

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