STRESS-INDUCED LIFT-OFF METHOD FOR KERF-LOSS-FREE WAFERING OF ULTRA-THIN (-50 101m) CRYSTALLINE SI WAFERS

Frederic Dross1, Aurelien Milhe1.2, Jo Robbelein 1, Ivan Gordon 1, Pierre-Olivier Bouchard 2, Guy Beaucarne 1, Jef Poortmans 1

1 IMEC, V.Z.w- Belgium, 2 Ecole des Mines de Paris (CEMEF) - France e-mail: frederic.dross@imec.be

ABSTRACT

We present a new wafering method for the production of ultra-thin crystalline silicon. This new lift-off process, named SLIM-cut (for Stress-induced Lift-off Method), requires only the use of a screen-printer and a belt furnace; no ion-implanted, porous layer or additional thickening by epitaxy is needed to obtain high quality wafers in the thickness range of 50 IJm without kerf loss. We deposit on a thick substrate a layer with mismatched coefficient of thermal expansion with respect to the substrate (for instance a metal layer). Upon cooling, the differential contraction induces a large stress field, which is released by the initiation and the propagation of a crack parallel to the surface. The concept has already been demonstrated successfully on both single and multi-crystalline silicon. Ve~ clean self-standing crystalline films with an area of 25 cm have been obtained from a high quality wafer. Some Si layers were further processed into solar cells. The first unoptimized solar cell device with a very simple process (no back-surface field, no intentional texturing, heterojunction emitter) showed an energy conversion efficiency of 10.0% (1 cm 2). This represents a silicon consumption already as low as 3.1 g/Wp (taking into account a polishing loss of 50 IJm), and proves the conservation of the material quality during the process. The potential of the method is estimated by the development of a custom-made numerical model. The model uses a 2D finite element method and is able to propagate a crack in a multi-layered structure. The model proposes a concentric re-meshing in the region of the crack tip at every increment and a crack initiation and propagation based on maximum stress criteria.

INTRODUCTION

The high price of polysilicon feedstock impedes currently the reduction of production costs and keeps the module cost as high as two years ago. Processing of thinner wafers remains a priority in the photovoltaic community. More and more solutions are developed to improve at industrial level the light trapping, rear-surface passivation and handling of wafers as thin as 100 IJm. Processing technology improves surely, but what are the options to fabricate such ultra-thin substrates? We present a literature review to understand why 50 IJm would be a very good thickness for a solar cell. Then we review the methods proposed nowadays to produce such thin wafers. A new method for the production of -50-lJm­thick wafers was recently developed at IMEC, and we will

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describe in details how this method works and what the status of development so far is. Finally, an evaluation of the new material for solar cell processing (surface study and solar cell processing) is performed and the conclusions are presented.

WHY IS 50 !-1m A GOOD THICKNESS FOR A SILICON SOLAR CELL?

From the 70's already, the question of the ultimate possible efficiency with a single Si homojunction was studied. Different parameters were considered as limiting the cell efficiency, and it was concluded that Auger recombination was the ultimate intrinsic limiting recombination process in silicon solar cells [1]. It was shown in Ref [1], that reducing the thickness, although imposing more severe demands on the quality of surface passivation to achieve the ultimate efficiency, would relax constraints on bulk quality and thus increase the efficiency limit. Over the years the different limiting intrinsic phenomena were summed up and the recent papers on the subject derive an efficiency limit fundamentally peaking for a thickness well below 100 IJm, in the range 40-60 IJm [2]. These theoretical calculations remain far from experimental values and especially far from what is achievable with cost effective methods encountered in industry. In particular the limited surface passivation shifts the optimum thickness to higher values. Nonetheless, there are still a number of arguments valid to choose wafer thicknesses below 100 IJm if they become available. For boron-doped Czochralsky material, the bulk lifetime is limited by the formation of a boron-oxygen complex activated under UV-light illumination. Since this degradation results from a bulk-related process, limiting the influence of the bulk by decreasing the thickness limits the degradation. It was indeed observed experimentally that the degradation was reduced when the cell thickness was decreased and that the optimum thickness shifts to thinner values (in certain experimental cases thinner than 100 IJm) after stabilization of the efficiency under light illumination [3,4]. Rear-junction cells are also an illustration of a specific configuration where the experimental efficiency increases when the thickness decreases, with a maximum efficiency experimentally obtained below 100 IJm [4]. There again, the efficiency increases when the ratio cell thickness/diffusion length decreases. As a rule of thumb, the diffusion length should be at least 3 times as large as the cell thickness to hope for decent cell result. With a

diffusion length in p-type Cz material currently observed around 300 to 400 !-1m, a cell thickness of 100 !-1m constitute an upper limit. But the decisive argument is the cost of the silicon substrate. The optimum thickness for highest efficiency surely depends on the surface passivation and thus on the technology. With today's standard technology the optimum thickness probably lies in the range 150 to 200 !-1m. But the decrease in material-related cost compensates largely the decrease in efficiency when targeting a cell thickness of 50 !-1m. To illustrate this fact, figure 1 shows the efficiency calculated by the software PC1 D for a mutlicrystalline cell with standard technology (bulk lifetime is 15 !-Is, and surface-recombination velocities are 1000 cm.s- 1). On the same graph is plotted the wafer cost estimated considering a silicon cost (purified and cut into wafers) of $500/kg.

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10 100 1000

Cel thickness (!.1m)

Figure 1: wafer cost and cell efficiency as a function of the cell thickness

While reducing the thickness from 200 !-1m to 50 !-1m, the cell efficiency is reduced by half a percent (absolute) whereas the material use is divided by 4. The wafer cost per Wp (which is the figure of merit commonly admitted nowadays) is thus decreased by a factor of 3. Last but not least, below 100 !-1m, silicon becomes notably flexible [5] and flexible light-weight solar cells are a decisive advantage for the design of new applications. This list of argument tends to prove that a wafer thinner than 100 !-1m would be desirable for solar cell production, and that 50 !-1m constitute a good compromise before the limited surface passivation dramatically reduces the efficiency and before the wafer handling becomes too problematic.

HOW TO PRODUCE 50 !-1m-THICK WAFERS?

Once convinced that 50 !-1m would be a good thickness for Si solar cells, we can still raise the question on how to produce such thin wafers? The mainstream technology (Le. wire sawing) is indeed nowadays limited to thicknesses in the range of 150 !-1m, with a kerf-loss of more than 100 !-1m. In the most optimistic outlooks, the silicon consumption for sawing one wafer does not go below 200 !-1m (including 50% kerf loss) [6]. A number of techniques have been tried to produce thinner wafers in a cost-effective way.

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Among them, silicon ribbons are a very interesting concept. Silicon is directly solidified from a silicon melt in the form of a wafer ready to be processed. As opposed to the wire­saw technology, there is no kerf loss of silicon during the process. The main silicon-ribbon technologies described in the literature are the following:

- Edge-Defined Film-Fed Grown Ribbons (EFG) - String Ribbons (SR) - Ribbon Growth on Substrate (RGS) - Ribbon on Sacrificial Template (RST)

The two first ones enable high material quality but do not allow for very thin wafers (they nonetheless become a very interesting alternative to wire-saw when the thickness goes below the silicon consumption of wire-sawn wafers including kerf-loss). The two later ones have the potential to make very thin wafers but the quality of the material obtained remains relatively limited so far. The Fraunhofer ISE attempted to achieve wafering of an ingot with a laser-cut. The attractive technique developed uses a chemical jet to guide the laser to the cut part of the ingot. A cut of 7 cm deep was achieved, but the process still exhibits some kerf-loss [7]. Another attractive concept relies on the epitaxial growth of the active region. This group of techniques combines the advantage of providing a custom thickness of active material of very good quality directly from silane or chlorosilane, while by-passing the expensive process of polysilicon fabrication, Czochralsky pulling and wafering. The fabrication of polysilicon is in addition nowadays the bottleneck of high-purity silicon supply. Several research groups have studied the possibility of growing epitaxially silicon on a high-quality template [8,9,10]. The techniques include the formation of a weak layer (either by growing porous silicon, or by implanting ions), and if the layer is not thick enough to be processed free-standing, a transfer of the layer to a carrier substrate. The efficiency reported are usually quite good even for thin wafers, proving that 1) the quality of epitaxial silicon is very good, and 2) it is possible to maintain very high efficiencies (>19%) with silicon solar cells thinner than 50 !-1m [8]. Another worth-noticing attempt was undergone by the Australian National University with a completely new cell and module concept: the SLIVER cells. Latest publication show very high efficiencies and a method specifically developed to handle the numerous very thin individual cells into sub-modules that can then be encapsulated in a standard way [11]. Finally, a new method has been proposed, but it is at present very unclear what the technique actually involves. A glimpse of the concept has been announced by SunPower in December 2007 in Fukuoka on behalf of the US company SiGen on a new method to directly cleave 50 !-1m wafers from an ingot [12].

DESCRIPTION OF THE PROCESS

In addition to these techniques which all exhibit strong and weak points on the way to fabricate ultra-thin wafers, we have recently developed a completely new technique with

the potential to produce 50-!..Im wafers with no kerf-loss. The technique is schematically described in Fig.2.

The starting material is a silicon substrate. A metallic layer is screen-printed on top of it and the wafer is annealed at high temperature in a belt furnace. Upon cooling down, the metal layer, as well as the silicon substrate, undergo a thermal contraction, but the mismatch in coefficient of thermal expansion between the metal and the silicon induces a high stress field in the substrate (Fig. 2 b/).

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d/

._-----Figure 2: Description of the method to produce thin silicon films. a/ metal deposition, b/ decrease in temperature to induce stress c/ peeling of the top layer, dl cleaning and

stress removal by chemical etching.

Figure 3: Photograph of the structure after the top layer is peeled off the parent substrate (25 cm 2).

To release the stress in the system the metal layer snaps off the parent substrate, peeling off at the same time a silicon layer of approximately 40-50 !..1m (Fig. 2 c/). Fig. 3 shows a photograph of the resulting substrate (a/) and of the silicon layer that has been lifted-off, still attached to the metal layer (b/). The substrate is cut along the whole surface but remains otherwise intact. It can be re-used for further additional layer lift-off. Starting the process from an ingot or from a very thick (several cm) substrate, the aim is to produce a big number for such thin daughter wafers from one mother substrate. The metal layer is then removed in a metal-etching solution resulting in a clean and stress-free silicon layer (Fig. 2 d/).' Scanning Electron Microscopy pictures revealed a thickness of -40-50 !..1m relatively constant over the wafer (ct. Fig. 4).

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Figure 3: SEM pictures of the film after flattening and metal-cleaning of the bi-material.

NUMERICAL MODEL

A 2D thermo-mechanical model based on a finite element method was developed to understand the parameters influencing the crack trajectory. The software was developed in house and adapted specifically for this purpose. At each step of the crack propagation, the software calculates the absolute value and the direction of the principal stress at the crack tip. The principal stress is defined as the stress at a given location expressed in a space base for which the shear stress is zero. If this stress exceeds a given critical stress, the crack propagates for a given distance perpendicularly to the principal stress d~rection (maximum circumferential stress criterion). The direct calculation of the principal stress exactly at the crack tip is numerically impossible because the absolute value tends to infinity. The calculation includes therefore an integration of the stress value over a given number of points in the neighborhood of the crack tip to avoid this diverging behavior. The mesh is readapted to the new structure, refined and centered on the crack tip at every step of the crack propagation.

We observed the theoretical behavior of a 300-!..Im-thick substrate coated with a 60-!..Im-thick metal layer. Fig. 5 shows the structure deformed by the stress during crack propagation. The crack propagates indeed parallel to the surface proving that the phenomenon is purely mechanical and does not require any weak layer or inhomogeneity to produce very thin crystalline silicon substrates. Since the process was proved to be purely from mechanical origin, a change in the mechanical parameters/properties of the system will directly influence the thickness of the Si film created. Therefore the thickness of the daughter wafer produced can be tailored to the application by changing the mechanical properties of the system (mainly Young modulus and thickness of the stress-inducing layer).

Figure 5: Examples of principal stress maps during crack propagation: (a) the mesh is centered and refined around

the crack tip at every propagation step; (b) and (c) the crack propagates parallel to the surface.

EVALUATION OF THE WAFERS PRODUCED

This novel method makes available a new kind of substrate that needs to be characterized in order to evaluate its potential for solar cell processing.

In particular, a study of the surface roughness and state of the sample produced appeared to be of particular relevance for this method of production. Already with a human eye it is clear that the two surfaces of the daughter wafers produced exhibit different features. The one in contact with the metal (surface A) is less shiny than the one cracked deep into the silicon (surface B). Surface A exhibits smaller features which are believed to originate from the etching process of the metal pastes. Surface B is a "wavy" surface following the propagation of the crack in the parent substrate. The higher roughness of surface A was confirmed with an optical profilometer as presented in Table I.

Table I: RMS and peak-to-peak roughness values measured with an optical deflection-based profilometer for b th rf d· t f 500 0 su aces over a IS ance 0 um.

RMS Peak-to-Peak Surface A 3um 10 um Surface B 4um 15um

This roughness which is possibly intrinsic to the process can be seen as a drawback. Nonetheless, a rough front surface can be an asset for solar cells. Reflectivity measurements were performed on both surfaces showing an improved light transmission, especially for surface A. The roughness obtained on the first samples is not optimized for solar cells and does not compare to state-of­the-art texturing. Nonetheless, since the roughness of surface A is likely to originate from the metal etching process, an optimized etching process could possibly provide an advantageous texture.

Since the process is purely mechanical, the characteristics of the resulting daughter wafer will depend on the mechanical properties of the parent substrate. In particular, since the mechanical properties of silicon are highly

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anisotropic, the crystal orientation plays an important role. Whereas all the previous roughness results are performed on <100>-oriented parent wafers, we applied the process to a <111 >-oriented substrate. <111> is known to be the weakest plane in the silicon crystal. As a consequence cleaving along this plane is energetically favorable and occurs with a higher probability. A fracture parallel to the surface will therefore be favored in a substrate oriented as such. Figure 6 shows the comparison of the profile of surface B (crack surface in the silicon substrate) in the case of a parent substrate oriented <100> and oriented <111> over a length of 1 cm. It appears very clearly that a <111 >-oriented substrate will produce daughter wafers with a much lower roughness and is thus favorable for the SLIM-cut method.

Figure 6: Comparison of the roughness (measured with a Dektak profilometer) of surface B in the case of processing

on a <100>-oriented and on a <111 >-oriented parent substrate.

Contamination of surface A was also an issue on forehand. TXRF (Total-reflection X-ray Fluorescence) tests were performed and showed no harmful contamination.

In photovoltaic research and development, a very good way of evaluating the potential of a new material is to process a solar cell structure on the new material. One of the resulting thin Cz daughter wafers was therefore further processed into a solar cell with a heterojunction emitter process described elsewhere [13). The 1 cm 2 cell reached an efficiency of 10.0% (FF=67.8%, Jsc=26.7 mA.cm- 2,

Voc=550 mV) [14). There was no rear-surface passivation, and no intentional surface texturing (surface B was exposed to sun light). These results indicate that the electronic quality of the material is largely preserved during the lift-off process in spite of the high stress involved. Much higher efficiencies are expected when surface passivation and texturing are introduced.

In view of calculating the silicon consumption of such device, we assume that 50 IJm of silicon are lost in a cleaning step to prepare the surface between two lift-off process. Then we compare the silicon consumption of one 40-lJm cell of 10% with a 250-lJm cell of 15.5% (obtained with 200 IJm of kerf loss). We obtain a factor of 3.2. Assuming a silicon consumption of 10 gMJp for the standard technology, we reach already, for the unoptimized cell produced from the SLIM-cut method, a Si consumption of 3.1 gMJp. This figure is expected to decrease even more as a more refined process is applied.

CONCLUSIONS

The process described for the production of thin crystalline wafer is completely new. It is potentially kerf-loss free, enables the production of very thin crystalline silicon wafers (-40-50 !-1m), and uses only industrial tools (screen-printer, belt fumace). The thickness of the lifted-off film can be tuned to custom needs within a certain range by changing the mechanical parameters and/or the thickness of the stress-inducing paste. For photovoltaic applications the thickness of -40-50 !-1m experimentally obtained is close to the theoretical optimum value needed to obtain the highest efficiency under 1-sun illumination when the performances are limited by Auger recombination. Applying a very simple process with no texturing and no rear-surface passivation (which are nonetheless crucial for such ultra-thin wafers), a 1 cm 2 solar cell was fabricated, exhibiting a conversion efficiency of 10.0%. The estimated silicon consumption lies already in the range of 3 g/Wp.

ACKNOWLEDGMENTS

The authors acknowledge the help of Dries Van Gestel, and Izabela Kuzma for the SEM pictures, Niels Posthuma and Koen De Keersmaecker for roughness measurements, Didier Dehertoghe and Andre Janssens for help during processing, Emmanuel Van Kerschaver and Kris Baert for fruitful discussion.

REFERENCES

[1] MA Green, ED-31 , No 5, 1984 [2] M.J. Kerr et al. IEEE, 2002 [3] K.A. Munzer, vol. 46, No 10, 1999 [4] D. Kray et al. EUPVSEC, 2004 [5] B. Micciche, EUPVSEC, 2006 [6] M. Jetschny, SiThinSolar Workshop, 2007 [7] D. Kray et aI., EUPVSEC22, 2007 [8] C. Hebling et aI., EUPVSEC14, 1997 [9] Brendel, EMRS, 2007 [10] H.J. Kim et al. IEEE WCPEC, 2006 [11] A. Blakers et aI., PVSEC17, 2007 [12] R. Swanson, PVSEC17, 2007 [13] L. Carnel, et aI., J. Appl. Phys. 100,063702 (2006) [14] F. Dross et al. Applied Physics A, 2007

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