Investigating the Linearity of MOSFET-only Switched-capacitor �� Modulators Under

Low-voltage Condition

Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar Electrical Engineering Department

Iran University of Science & Technology (IUST) Tehran, Iran

farhad_parsan@ieee.org

Abstract— Effect of asymmetric operating condition of depletion-mode MOS capacitors on the linearity of MOSFET-only switched-capacitor �� modulators is investigated. In very low-voltage switched-capacitor circuits the opamp input and output common-mode levels are separated to provide maximum overdrive voltage for MOS switches. This causes an asymmetric voltage drop on capacitors during operation. On the other hand, the depletion-mode MOS capacitors are most linear when operated under a symmetric condition. The effect of this increased nonlinearity on a �� modulator which is operated under an asymmetric condition is simulated and the results are compared with a �� modulator which is operated under a symmetric condition.

Keywords- MOS capacitor; MOSFET-only; �� modulator

I. INTRODUCTION To integrate analog parts of a mainly digital circuit on a

single chip, in a standard digital CMOS technology, MOS gate-to-bulk capacitors (MOSCAPs) are more desirable than standard interlayer capacitors (poly-metal or metal-metal capacitors). It’s because they are more area-efficient and they yield less parasitic capacitance to the substrate. However, they are strongly voltage-dependant because of the various charge distributions in the accumulation, depletion, and strong inversion regions. Fortunately, there are some compensation techniques to reduce the nonlinearity of these capacitors [1].

Compensated MOSCAPs which are operated in the accumulation or strong inversion regions have a large capacitance per unit area compared to the depletion-mode MOSCAPs, but they need a high switched bias voltage to be acceptably linear, hence they are not suitable for low-voltage applications. Depletion-mode MOSCAPs [2]–[5], on the other hand, don’t need any bias voltage. In reality, applying a bias voltage will increase their nonlinearity.

Depletion-mode compensated MOSCAPs show best linearity when their operating region is symmetric. But in a very low-voltage switched-capacitor application a symmetric operation is not possible. That is because, in these applications, the opamp input and output common-mode levels should be

separated [6]. The opamp input common-mode level is usually adjusted to VSS to provide maximum overdrive voltage for nMOS switches. The opamp output common-mode level is adjusted to the middle of the supply voltage rails for the maximum output swing. This requirement will increase the nonlinearity of depletion-mode MOSCAPs significantly. In this paper we have studied the linearity of series and parallel compensated depletion-mode MOSCAPs under a symmetric and asymmetric operating condition. Also, we have examined the effect of this increased nonlinearity on the behavior of hybrid-compensated switched-capacitor �� modulators.

In section II, series compensated depletion-mode (SCDM) MOSCAPs, and parallel compensated depletion-mode (PCDM) MOSCAPs, are investigated under symmetric and asymmetric operating conditions using the simulation results. In section III, these capacitors are used to realize two �� modulators which one of them incorporates opamps with equal common-mode levels and the other one incorporates opamps with different common-mode levels. In section IV simulation results for the two �� modulators are compared.

II. SERIES AND PARALLEL COMPENSATION TECHNIQUES

A. Series Compensation Technique In a series compensation technique [2], two MOS

capacitors are connected anti-serially. Fig. 1 and Fig. 2 show this configuration for two p-channel MOS capacitors. The usable capacitance is available between nodes A and B. To have a low parasitic capacitance at the floating node (C), the gates of M1 and M2 are connected together. Also, an additional transistor (M3) is used which is biased in the subthreshold region and acts as a high resistance element to prevent the floating node from charging. The area of M3 should be small relative to M1 and M2 to avoid a significant parasitic capacitance at node C. A large parasitic capacitance at node C will prevent a balanced voltage drop on the MOSCAPs M1 and M2 and it will result in more nonlinearity. The resistance of M3 may vary in a wide range by changing its size or its gate-to-source bias voltage but it should not deteriorate the MOSCAP characteristic.

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The CV plot of a SCDM-MOSCAP operating under a symmetric condition is shown in Fig. 1. We used a 0.18μm standard digital CMOS technology with tox= 4.1nm for all the simulations in this paper (BSIM3v3.1 MOSFET model). The threshold voltage for nMOS transistors is VTn=0.5V and for pMOS transistors is VTp=–0.51V. For M1 and M2, we used W1=W2=10μm and L1=L2=50μm. Also, we used VSS=–0.5V and VDD=0.5V. GNDA is the analog ground which is adjusted to the middle of the supply voltage rails (GNDA=[VDD+VSS]/2=0V). If we define nonlinearity to be the percentage difference between the capacitor maximum value to the minimum value in a specific voltage interval then:

max min 100max

C CNonlinearity

C

� ��� �� �� �

(1)

According to the CV plot of Fig. 1, the nonlinearity of the SCDM-MOSCAP for a symmetric operating region (VAB=±0.5v) is about 1.54 %. Fig. 1 also shows that even under a symmetric operating condition, the CV plot of the SCDM-MOSCAP is not symmetric. The capacitance per unit area for this MOSCAP is about 0.71 fF/μm2.

In a very low-voltage switched-capacitor application a symmetric operation is not possible, because in these applications, the input and output common-mode levels of the opamps are not equal. Fig. 2 shows the CV plot of a SCDM-MOSCAP operating under an asymmetric condition (VAB=0v…1v). The nonlinearity is now about 1.46 %. Thus, in a SCDM-MOSCAP the nonlinearity doesn't change notably for an asymmetric operation because the CV characteristic of a SCDM-MOSCAP operating under a symmetric condition is also asymmetric. The capacitance per unit area for this MOSCAP is about 0.61 fF/μm2.

B. Parallel Compensation Technique In a parallel compensation technique [3], two MOS

capacitors are connected in an anti-parallel form. Fig. 3 and Fig. 4 show this configuration for two p-channel MOS capacitors. The usable capacitance is available between nodes A and B. Fig. 3 shows the CV plot of a PCDM-MOSCAP operating under a symmetric condition (VAB=±0.5v). A nonlinearity of about 9.3 % occurs under this condition. The CV plot of a PCDM-MOSCAP operating under an asymmetric condition (VAB=0v…1v) is shown in Fig. 4. Now the nonlinearity is about 39.6 %. We see that the nonlinearity has increased severely. This amount of nonlinearity is unacceptable

in some applications and makes serious matching problems. However, in some applications including the hybrid-compensated MOSFET-only �� modulator which is investigated in this paper, we will show that the increased nonlinearity will have no noticeable effect. The capacitance per unit area for the symmetrically operated MOSCAP is about 2.49 fF/μm2 and for the asymmetrically operated MOSCAP is about 2.81 fF/μm2.

III. LOW-VOLTAGE MOSFET-ONLY SWITCHED-CAPACITOR �� MODULATOR DESIGN

In a MOSFET-only �� modulator, several compensation schemes can be used: series compensation, parallel compensation, and hybrid compensation. In a series compensation scheme all the capacitors are replaced with SCDM-MOSCAPs. This leads to the maximum linearity, hence the minimum output distortion. But this approach is not area-efficient comparing to a parallel compensation scheme. In a parallel compensation scheme, all the capacitors are replaced with PCDM-MOSCAPs. This leads to the maximum area-efficiency but a higher output distortion. In order to make a compromise between the linearity and the area-efficiency, the hybrid compensation technique is used [4]. In the hybrid compensation scheme, the input sampling capacitor which is used to convert the input voltage to the charge and has the most effect on the output distortion [7], is replaced with a SCDM-MOSCAP and the other capacitors are replaced with PCDM-MOSCAPs.

In order to investigate the effect of increased nonlinearity of PCDM-MOSCAPs due to an asymmetric operating condition on switched-capacitor �� modulators, two different �� modulators were designed. A second-order non-cascaded architecture is used for both �� modulators (Fig. 5 and Fig. 6). Non-cascaded architectures are less sensitive to coefficient mismatch than cascaded architectures and this is a very desirable characteristic for modulators which contain MOSCAPs because realizing an accurate capacitor ratio for nonlinear MOSCAPs is hard.

In the first modulator, the opamp input and output common-mode voltages are the same (VCMI=VCMO=GNDA= [VDD+VSS]/2). As a result, in this modulator the operating condition for MOSCAPs is symmetric. However, equal opamp input and output common-mode voltages calls for a higher supply voltage to ensure a sufficient overdrive voltage for the MOS switches. We used a 1.8V supply voltage (VSS=–0.9V,

C[ f

]

C[ f

]

C[ f

]

C[ f

]

Figure 1. CV plot of a SCDM-MOSCAP operating under a symmetric condition (W1=W2=10μm, L1=L2=50μm)

Figure 2. CV plot of a SCDM-MOSCAP operating under an asymmetric condition (W1=W2=10μm, L1=L2=50μm)

Figure 4. CV plot of a PCDM-MOSCAP operating under an asymmetric condition (W1=W2=10μm, L1=L2=50μm)

Figure 3. CV plot of a PCDM-MOSCAP operating under a symmetric condition (W1=W2=10μm, L1=L2=50μm)

VDD=0.9V) together with complementary MOS switches in our modulator. The on-resistance of the switches in our case is below 3 K� to have a sufficiently small time-constants. For the rest of the paper we call this modulator the symmetric modulator. The architecture of the symmetric modulator is shown in Fig. 5.

The second modulator is a very low-voltage one. We used a 1 V supply voltage (VSS=–0.5V, VDD=0.5V) in this modulator. Here, the opamp input common-mode voltage is adjusted to VSS and the opamp output common-mode voltage is adjusted to the middle of the supply voltage rails (VCMI=VSS, VCMO= [VDD+VSS]/2). In fact, this condition is imposed by the low-voltage limitations. As a result, in this modulator the operating condition for MOSCAPs is asymmetric. An input common-mode voltage of VSS permits us to use single nMOS switches at the opamp input. But it is not possible to switch the opamp output signal path using a single nMOS switch or complementary MOS switches because the supply voltage is now less than VTn+ |VTp|. However, the switched-opamp technique can be used to overcome the problem. For the rest of the paper we call this modulator the asymmetric modulator. The architecture of the asymmetric modulator is shown in Fig. 6. Although the asymmetric modulator architecture seems to be different from the symmetric modulator architecture but these two architectures are exactly the same in terms of the magnitude of the transform function of the output to the input and the output to the quantization noise. This difference is caused by the fact that in the symmetric modulator the opamps are not switched while in the asymmetric modulator the opamps are switched and hence their outputs are accessible in just a half clock period.

The output signal-to-noise-plus-distortion ratio (SNDR) is used to characterize the effect of MOSCAPs nonlinearity on the modulators outputs. To make a comparison between the symmetric and asymmetric modulators, their opamps and comparators should have the same characteristic. Thus we have used similar ideal opamps and comparators for both modulators. The opamps used have the same gain (66 dB) and the same output saturation voltages (± 0.5 V) and the only difference is that the opamps used in the asymmetric modulator are switchable. There is no need to have positive and negative supply voltages for the modulators and this choice is just for the sake of simplicity. As the modulators have the same architectures, the same opamps, and the same comparators, they should have the same characteristics when linear capacitors are used.

IV. SIMULATION RESULTS The circuit implementation of the symmetric �� modulator

is shown in Fig. 7. Only half of the fully differential circuit is shown for simplicity. This modulator is similar to the one used in [4]. As it can be seen, the opamps input and output common-mode voltages are GNDA=0V. Thus the MOSCAPs are operated symmetrically in this modulator. The output SNDR versus input signal amplitude for this modulator is shown in Fig. 8. The maximum achieved SNDR for the modulator with linear capacitors is 71.7 dB and for the MOSFET-only modulator with hybrid compensation is 65.5 dB.

The circuit implementation of the asymmetric �� modulator is shown in Fig. 9. Only half of the fully differential circuit is shown for simplicity. This modulator is similar to the one used in [5]. In this modulator, CDC1 and CDC2 are used for DC voltage correction [6]. Also, bootstrapped clock signals (�b) are used for the input switches. Here, the opamps input common-mode voltages are adjusted to VSS=–0.5V and the opamps output common-mode voltages are adjusted to GNDA=0V. Thus the MOSCAPs are operated asymmetrically in this modulator. In a practical application, CDC3 and CS3 are used to shift the opamp output common-mode level to VSS for the comparator input. The output SNDR versus input signal amplitude for this modulator is shown in Fig. 10. The maximum achieved SNDR for the modulator with linear capacitors is 73 dB and for the MOSFET-only modulator with hybrid compensation is 70 dB.

In spite of trying to make the two modulators as similar as possible, they don’t have exactly the same output SNDR versus input signal amplitude even when linear capacitors are used. This is partly due to the different circuit implementations and non-ideal parts and partly due to the random variations when computing the FFT of a random quantity such as the in-band noise [8]. To make a comparison between the symmetric and asymmetric modulators, the SNDR difference between a modulator when it contains linear capacitors and the same modulator when it contains MOSCAPs is calculated for each input amplitude. The results are shown in Fig. 11. As it is clear, there is no absolute advantage for any of the two modulators. The SNDR difference for the two modulators is mostly between 0 dB to 6 dB for various input amplitudes. Thus we can conclude that the asymmetric operating condition for MOSCAPs in a hybrid-compensated MOSFET-only �� modulator seems to have no noticeable effect on the output SNDR and so this type of modulators seem to be in good compatibility with very low-voltage applications.

A 4096-point FFT (Hanning windowed) was used to calculate the SNDR for various input amplitudes. The non-overlapping clock signal frequency was 8.192 MHz which yields a 64 KHz bandwidth with an oversampling ratio of 64. The input was a 24 KHz sinusoidal signal. Fig. 12 shows the output power spectral density (PSD) for the asymmetric MOSFET-only �� modulator for an input signal amplitude of -2 dBFS. The value of integrating capacitors was chosen 2 pF. The value of the other capacitors is calculated in regard to the modulator coefficients. For the MOSCAPs, the mean capacitance value is used.

+-

1/5

+-

1/4

1/31/4 Z -1

1– Z -1Z -1

1– Z -1VIN(z) VOUT(z)

FP FP Figure 5. The symmetric modulator architecture

Figure 6. The asymmetric modulator architecture

V. CONCLUSION The effect of symmetric and asymmetric operation on the

linearity of series and parallel compensated depletion-mode MOSCAPs was investigated. It was shown that the linearity of a SCDM-MOSCAP does not change significantly due to an asymmetric operating condition but the linearity of a PCDM-MOSCAP will be deteriorated severely under an asymmetric operating condition. The effect of this increased nonlinearity on hybrid-compensated MOSFET-only �� modulators was investigated. It was shown that for a hybrid-compensated �� modulator this increased nonlinearity has no noticeable effect on the output SNDR. However, this increased nonlinearity might have a significant effect on other types of �� modulators or other precise applications.

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only switched-capacitor circuits in digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 734 – 747, June 1999.

[2] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel, “A 1.8-V MOSFET-only �� modulator using substrate biased depletion-mode MOS capacitors in series compensation,” IEEE J. Solid-State Circuits, vol. 36, pp. 1041–1047, July 2001.

[3] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel, “A low-voltage MOSFET-only �� modulator for speech band applications using depletion-mode MOS capacitors in combined series and parallel compensation,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 376 – 379, May 2001.

[4] T. Tille, J. Sauerbrey, M. Mauthe, and D. Schmitt-Landsiedel, “Design of low-voltage MOSFET-only �� modulators in standard digital CMOS technology,” IEEE Trans. on Circuits and Systems, vol. 51, no. 1, pp. 96 – 109, January 2004.

[5] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, “A 0.7-V MOSFET-only switched-opamp delta-sigma modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662 – 1669, December 2002.

[6] A. Baschirotto, R. Castello, and F. Montecchi, “Design strategy for low-voltage SC circuits,” IEE Electronics Letters, vol. 30, pp. 378–379, March 1994.

[7] J.M.G. Cama, S.A. Bota, E. Montane, and J. Samitier, “A MOSFET-only second order delta-sigma modulator for capacitive sensor interfaces,” in Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, vol. 3, pp. 1689 – 1692, September 1999.

[8] R. Schreier, and G. C. Temes, Understanding Delta–sigma Data Converters. Piscataway, NJ: Wiley-IEEE Press, 2005.

Figure 11. The SNDR difference of the modulators when they use

linear capacitors and MOSCAPs

Figure 12. Simulated output power spectral density (PSD) for the

asymmetric MOSFET-only �� modulator

Figur Figure 7. The symmetric �� modulator

Figur Figure 9. The asymmetric �� modulator

Figure 10. Simulated SNDR versus input signal amplitude

for the asymmetric �� modulator

Figure 8. Simulated SNDR versus input signal amplitude

for the symmetric �� modulator