A Fourth-Order, Low-pass, MASH �� Modulator with CBSC Technique in 0.18μm CMOS

Majid Zamani1, Massoud Dousti1, Mehdi Taghizadeh2 and Amir Hossein Abdollahi3

(1-Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran) E-mail – m.zamani@srbiau.ac.ir

(2 – Department of Electrical Engineering, Islamic Azad University- Kazerun Branch) (3 –Member of Scientific Association of Electrical & Electronic Engineering, Islamic Azad University Central Tehran Branch)

Abstract— In this paper a new gain stage for comparator-based switched-capacitor circuits (CBSC) is presented. In contrast with the conventional structure the proposed structure utilizes an extra comparator to make a variable comparator threshold, in order to attenuating the overshoot at the end of the coarse phase. To verify the idea, we designed a 2-1-1 cascaded Multi-Stage (MASH) �� modulator, based on the proposed architecture in a 0.18-�m 1P6M standard CMOS process. It achieves 76-dB signal-to noise-and-distortion ratio (SNDR) and 78-dB dynamic range (DR) at input 132.81 KHz. In addition it consumes 3.65mW from a 1.8-V power supply at 32MS/s (OSR=16).

Keywords- Comparator-based switched-capacitor (CBSC), Gain stage, Common-mode feedback (CMFB), MASH Delta-sigma (��) modulator, Process variation.

I.INTRODUCTION Technology scaling which is the most challenging factor in nonoscale processes makes some issues on design of high performance op-amps which are one of the crucial analog building blocks in the sc-circuits like Analog-to- Digital Converters (ADCs). It decreases intrinsic gain (lower output resistance), voltage headroom and SNR while it increases device leakage and mismatch [1-3].The most important problem is decreasing the device gain. It causes that, the precision in the feedback circuits are dramatically reduced, because in the traditional switched-capacitor circuits a high gain op-amp determines the accuracy of the charge transfer. A method for achieving higher gain without reducing voltage headroom is to cascade several gain stages but it leads to stability problem. High gain op-amp can be realized by cascoding transistors, but voltage headroom will be reduced. With decreasing the signal amplitude a larger capacitance and also more power consumption is needed to maintain the same SNR [4]. Different solutions have been introduced for solving the power issue. The time-to-digital converter (TDC) [5], incomplete settling [6] and open-loop amplifiers [7]. Recently, a comparator-based switched-capacitor (CBSC) technique was reported in [8-10] to replace the op-amp with comparator and current sources which has same operation

like as opamp-based architecture without the problems mentioned before. In CBSC technique, a comparator and switched current sources are used to sense the virtual ground condition, instead of forcing it with an op-amp. One of the issues which conventional architectures [8-10] suffer from it is overshoot at the end of the coarse phase. It decreases the speed and accuracy. The use of the CBSC gain stage helps us to attenuate the primary overshoot in order to increase the speed (fastest settling) and decrease power consumption. This paper is organized as follows: Section II describes the operation of fully differential architecture with variable comparator threshold in detail during its charge transfer phase. Section III proposes the design of key building blocks. Section IV proposes the design of a 2-1-1 cascaded Multi-Stage (MASH) �� modulator as a design example. Section V covers the simulation results and section VI concludes.

II. GAIN STAGE DESCRIPTION Fig. 1 shows the gain stage (G=2) and its timing diagram with variable comparator threshold. As it is seen from timing diagram, �1 is sampling phase and �2 is charge transfer phase. In �1 phase, the input signal is sampled by input capacitors (CS1, 2 and Cf1, 2). The charge Transfer phase is divided into four following sub-phases: 1) preset phase for preset switches (P1), 2) preset phase for driving the state logic units (P2), 3) coarse transfer phase (E1) and 4) fine transfer phase (E2). After sampling, the outputs (op,on)are preset to VREFP and VREFN. Preset phase sets the outputs nodes to preset levels away from common voltage level (VCM). P2 is used to compensate for the delay in the state logic units and driver switches of the current sources. After preset phase, state logic units produce (E1p,n) and trigger coarse current sources to charge the capacitor network. Ia charges the positive half circuit and discharges the negative half circuit. As a result input nodes of the comparator (Vc and Vd) are charged in opposite directions to cross each other for making first decision as seen in Fig.1 (b). However, there is overshoot in the output due to the finite delay in the comparators and ramp rate (Vovp).For this reason, two comparators have been

IEEE CCECE 2011 - 000048

����������������� � � �� ������ � � �����������������������������

M1 M2

M3

M4

M5

M6

M7

M8M9 M10

M11

M13 M14

M15 M16

M17

VinVip

Vbias

Vout

VDD

Preamplification(Input Stage)

Decision Circuit

Postamplification(Output Buffer)

M12

S

Fig. 3. Threshold-detection comparator.

Fig. 1: (a) Gain stage with variable comparator threshold (b)

Timing diagram.

Fig. 2. Proposed Levels.

used in this design (K1, K2), so we can already adjust the comparison levels for delay compensation and attenuating the primary overshoot as seen in Fig.2. Also to calculate Vcm' and Vcm", we follow the below procedure:

delayTa tCIX )./(�� (1) Here, tdelay is the delay of the comparator estimated from simulations, Ia is the coarse current and CT is the total loading capacitance at the output of the gain stage, given by:

LYT CCC �� (2) CY is the series combination of CS and CF, and CL is the equivalent capacitance of the next stage. Also nominal comparison levels are (VCM'=VCM-�X, VCM" =VCM+ �X). To achieve more accurate output, the fine transfer phase is used. During this phase, fine current sources are turned on to

reduce the final overshoot and also achieve to second detection as seen in Fig.1 (b). Accuracy of the fine current sources determines the final error which determines the offset and nonlinearity of the ADC. Also at E2 phase we set (VCM=VCM'=VCM"), so we will have an ideal condition to correct final overshoot (Vovf). Variable comparator threshold was used for single ended architecture in [8]. To produce a very highly accurate CBSC gain stage, a three-step pattern was our objective in this report as it is seen from input waves of the comparators in Fig.1 (b). By using this technique more constant output voltage would be achieved which can be used in high precision and high frequency applications.

IV. DESIGN OF KEY BUILDUING BLOCKS

A. Threshold-Detection Comparator The voltage comparator [11], is depicted in Fig.3, it consists of three stages: an input pre-amplifier (M1-M7), a decision stage (M8-M12) and an output buffer (M13-M17). The input stage converts the input voltages to currents level needed to drive the decision stage. The decision stage is a bitsable cross-coupled circuit which switches from one state to another in accordance with the magnitude of the input currents, the positive feedback speed up the switching. The output stage is used to convert the output voltage of the decision circuit into digital logic signal. To reduce static power consumption, the comparator is controlled by signal S. When signal S is active (S=1) M12 is connected to circuit and the comparator is in the operation mode. If S is not active, (S=0) path between M12 and circuit is disconnected and the comparator turns of. With this work static current of the comparator during the settling phase (S) is negligible.

B. Current Sources and CMFB For coarse current sources which generate a large amount of current we used cascade current sources to achieve high output resistance for increasing the accuracy and linearity. A PMOS current source was used for the pull- up current, and a NMOS current source was used for the pull-down current during the coarse charge transfer phase. Also the effective open-loop gain Ao of a CBSC circuit [8] is modeled as:

tdRCAo T

..

��� (3)

Where CT is the total capacitance at the output of each stage,

IEEE CCECE 2011 - 000049

(1- )-1-1-Z -Z 2

(1- )-1-Z 3

U(Z) 1/2 1 1/2

1/2 1/2

1/4 1

1

1/2

11/2

1

1/2

E1(Z)

E2(Z)

H1(Z)

H2(Z)

H3(Z)

Y(Z)

-1Z1-Z-1

-1Z1-Z-1

-1Z1-Z-1

-1Z1-Z-1

Analog DigitalQuantizer

Quantizer

Quantizer

1b

1b

1b

-2Z

Fig. 5. Block diagram of a 2-1-1 cascade �� modulator.

�1

�1

�1 �1Ca

Ca

Cb

Cb

E2

Vfine

IaIb

VB

IAS

E2

E1

Vcoarse

Roc

Rof

IaIb

Vfine

E1

Vcoarse

Vctrl

SS

SS

S

E1

E1

Fig. 4: Current sources with CMFB circuit.

Ro is the output resistance of the current source, td is the delay of the threshold-detection comparator, and � denotes the feedback factor. As mentioned before output voltage changes are smaller in the fine charge transfer phase because the fine current (Ib) is much smaller than coarse current (Ia). As a result we use a single transistor for generating the fine current (Rof<Roc). For enhancing the accuracy in the fine current source [12], the controlling switch is connected to the drain. As a result when E2 is active (E2=1), it makes a cascade combination. So we have good accuracy in accordance with (3). The proposed technique is shown in Fig. 3. During the settling phase (S), a switched-capacitor common-mode feedback (CMFB) is used to control the pull down coarse current source. In order to control the common-mode voltage accurately, an amplifier is added in the CMFB loop to achieve sufficient loop gain [13]. The CMFB circuit and current sources are shown in Fig. 4.

IV. DESIGN EXAMPLE

The proposed CBSC gain stage is used to implement a 4nd, 2-1-1 cascade �� modulator with single bit quantizer. The block diagram of the 2-1-1 modulator structure is shown in Fig.5. In this step we calculate the optimized values for the coefficients of each stage in 2-1-1 cascade configuration. The optimized coefficients will let us reach the best DR for the designed system. This set of coefficients ensures that the quantization error from the first and second stages is completely cancelled at the modulator output. This procedure was guided at every step by SIMULINK, using the �� Toolbox [14]. With [14] every modulator can be modeled in real state with adding the nonideal effects. The modulator coefficients after voltage scaling are shown in Fig.5. The signal and noise transfer functions of the modulator are STF(z) =z-3 and NTF(z) =(1-z-1)4, respectively. The digital filters are implemented in MATLAB in such away the errors

in stages first and second (E1(z), E2(z)) are cancelled. The switched-capacitor implementation of the analog part of the modulator with the proposed CBSC gain stage is shown in Fig.6. In the traditional circuits because of usage of op-amp we have some problems like: Finite op-amp gain, bandwidth and slew-rate. Unlike the above mentioned problems, nonlinear settling of the op-amp can decrease the SNDR significantly because it makes some harmonics in the output spectrum. As a result, to achieve linear settling, power consumption has to be increased. In CBSC technique we will not have same problems. For instance, in CBSC technique coarse and fine phases are totally linear. One of the problems in CBSC technique is offset due to finite threshold-detection comparator delay and voltage drops across switches with finite on-resistance [8]. The offset of the first integrator is directly added to the input signal and is equal to the digital output while the offset of the second integrator is referred to the input of the modulator by dividing it by the transfer function of the first block and it is less effective [15]. Therefore, simulations show that the offset does not decrease the �� performance.

V. SIMULATION RESULTS A. mash delta sigma modulator

In this section the results obtained from system level simulation (MATLAB) and circuit level simulation using HSPICE in a 0.18�m CMOS process are compared. The voltage amplitudes at the input terminals (Vc and Vd) of the proposed CBSC architecture during the charge transfer phase are depicted in Fig. 7. The simulated output spectrum of these approaches via 4096-point with input signal amplitude -4 dBFS and 132.81KHz are both shown in Fig. 8. �� with proposed gain stage achieves a peak SNDR of 76 dB and �� simulated in MATLAB achieves a peak SNDR of 85 dB When sampled at 32MS/s (OSR=16), this yields a signal bandwidth (BW) of 2MHz. The SNDR of the two modulators as a function of the input signal amplitude is depicted in Fig. 9. Fig. 10 shows the SNDR degradation versus the mismatch of the sampling capacitors. As it is seen, the SNDR

IEEE CCECE 2011 - 000050

0 0.5 1 1.5 2 2.5 3 3.5 440

45

50

55

60

65

70

75

80

Capacitor Mismatch(%)

SND

R(d

B)

1st Sampling Capacitor Mismatch2st Sampling Capacitor Mismatch3st Sampling Capacitor Mismatch

Fig. 10. SNDR degradation versus the sampling capacitors mismatch.

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 00

1020304050

60708090

100

Input Amplitude[dBFS]

SND

R[d

B]

Matlab simulation (DR=89 dB)SPICE implimentation (DR=78 dB)

Input Frequency:132.81 KHz

FFT Points: 4096

Fig. 9. SNDR versus input signal amplitude of the modulator.

2.2 2.3 2.4 2.5 2.6 2.7x 10-7

0

0.5

1

1.5

2

Time (S)

Ampl

itude

(V)

VcVdE1E2P1

Fig. 7. Voltage amplitudes at the input terminals (Vc and Vd) of the proposed architecture during the charge transfer phase.

105 106 107-200

-150

-100

-50

0 -4dBFS Input Sinwave with

132.81 KHz for 4096 FFT Points

Frequency [Hz]

PSD

[dB]

Hspice Simulation(SNDR=76dB)Matlab Simulation(SNDR=85dB)

InputBandwidth

Fig. 8. Simulated output spectrum of the modulators.

Fig. 6: Switched-capacitor implementation of the 2-1-1 cascade CBSC �� modulator and clocking scheme.

degradation of the proposed cascade 2-1-1 is negligible with extremely 1% mismatch error for first sampling capacitor. The simulated power dissipation is 3.65 mW from a 1.8-V power supply, which obtains a figure of merit of 177 fJ/step. Fig. 11 shows the FOM comparison between our work and state-of-the-art �� modulators. Table I shows the performance comparison between previous published �� modulators and this work.

IEEE CCECE 2011 - 000051

Table I: Performance comparison Parameter This work [16] b [17] b [18] b Signal BW

(MHz) 2 1.92 2.5 2.2

OSR 16 16 16 16

Peak SNDR (dB)

76 (1bit-

quantizer)

77 (1bit-

quantizer)

78.5 (3level-

quantizer)

72.7 (1bit-

quantizer) DR (dB) 78 79 86 78

Power (mW) 3.65 7.4 62.5 65.8

FOM a 0.17pJ/ step

0.33pJ/ step

0.77pJ/ step

2.3pJ/ step

Architecture 2-1-1 2-2 2-1-1 2-1-1 Supply (V) 1.8 1.2 2.5 2.5

CMOS Tech. 0.18�m 0.13�m 0.25m 0.25m

(a) –FOM=POWER/2.BW.2(SNDR-1.76)/6.02 (b)–Mean experimental results. 0 20 40 60 80 1000

1

2

3

4

5

6

7

sampling frequency, MHz

FoM

, pJ/

conv

-ste

p

90-nm130-nm180-nm250-nm>250-nm

State-of-the-art FOM comparison

This work

ISSCC07

b-TCASI08

ISSCC00a-ISSCC07

b-ISSCC07

ISSCC02

ISSCC05

TCASI09

TCASI10

TCASI04

TCASI05

a-TCASI08ISCAS02

ISSCC99

ICECS01

ISSCC99

ISSCC09

Fig. 11. Figure-of-Merit Comparison.

More FinalOvershoot

Vo,ideal Vovp

Presetphase

Coarsephase

Vo,actual

This situation causes that the SNDR decreases significantly and instability contributes in the next stages

Finephase

(a)

Uns

tabl

esit

uatio

n

More fine currant

Ib is not enough andThe Fine transfer phase is

not completed

Wor

st ca

se in

SS

corn

er

Vovf for TT mode

Vo,actual

Presetphase

Coarsephase

Finephase

Vo,ideal VovpVovf for TT mode

Tp1+TE1+td1>Ttransfer

Tp1+TE1+td1+�.TE2>Ttransfer

Tsettele>Ttransfer

(b)

Worst case in FF corner

�.TE2 is the fraction of the fine charge transfer phase

Transfer phase �2

Transfer phase �2

Fig. 12.The effect of process variation: (a) ‘SS’ corner effect

(b) ‘FF’ corner effect.

B. Impact of Process Variation In this part our goal is acquiring a relationship which shows the impact of process variation on the performance of the CBSC architecture. The factors that influence on CBSC efficiency are overshoot voltage and voltage drop that we will do analysis on overshoot voltage. The sensitivity list of Vov consists of two parameters; td and CT. Under process variation, net capacitance (CT) and comparator delay (td) vary but charging current variations because of finite output resistance is low and we neglect its variations in our relation. Hence, with considering the impact of process variations on td and CT by �td and �CT, respectively, results in:

)1(1

1

..

.)()(

nomnom

nom

nom

nom

nom

nom

nom

VovVovVov

CC

tdtd

IaCtd

IaCCtdtdVov

���

����

����

�

��

��

�����

�

(4)

Where the nom subscript shows the nominal value of the parameter. Also the accuracy of the gain stage is given by:

nhcphc VovVovVov ��� (5) Where Vovphc is the overshoot of the positive half circuit under process variation and Vovnhc is the overshoot of the negative half circuit under process variation. Worst-case analysis wil be done with min (CT) and ‘SS’ (transistor mode) combination. In this situation slope of ramp (M=I/CT) and also comparator delay are maximum. In this mode, gain stage sometimes cannot control the primary overshoot because fine current is not enough for achieving to the second cross in the transfer phase; as a result it becomes unstable. On the other side, max (CT) and ‘FF’ (transistor mode) combination cause minimum slope of ramp (M=I/CT) and also comparator delay. With decreasing the ramp rate it is probable that fine transfer phase (E2) is not completed during the transfer phase (TP1+TE1+TE2>TTransfer phase), so we have more final overshoot.

More final overshoot is resulted in stronger even and odd harmonics and reduced accuracy. Fig.12 indicates the above analysis. Comparison between the proposed and conventional CBSC architectures under process variation is summarized in Table II.

VI. CONCLUSION

We have presented a new gain stage for CBSC circuits. The proposed architecture utilizes an extra comparator to attenuate the primary overshoot at the end of the coarse phase for increasing the speed and accuracy. To validate our design a multi-stage �� modulator was implemented with proposed architecture using HSPICE in a 0.18�m 1P6M CMOS process. Also, to showing the effectiveness of our structure, we compared the performances of the proposed and conventional architectures under process variation. According to the simulation results, this technique is suitable for �� implementation.

IEEE CCECE 2011 - 000052

Table II: Comparison between CBSC architectures under process variation.

Architecture STP CBSC Conventional CBSC

Sampling frequency

20 MHz

20 MHz

20 MHz

20 MHz

Coarse charge current

230 �A

230 �A

230 �A

250 �A

Fine charge current 58 �A 58 �A 58 �A 90 �A

Capacitor Model min typ max typ

Transistor Model SS/120 TT/27 FF/-40 TT

Primary overshoot(Vovp) at the input nodes of the

comparators (Vc - Vd )

79.7 mV

54.7 mV

27.4 mV 83.3 mV

Final overshoot(Vovf) at the input nodes of the

comparators (Vc - Vd )

34 mV 31.2 mV

24.2 mV

34.1 mV

(*) – For comparison, gain stages (G=2) are considered. (**) – Conventional CBSC has been reported in [10].

References

[1] A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, “Analog circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 132–143, Jan. 2005.

[2] B. Murmann et al., “Impact of scaling on analog performance and associatedmodeling needs,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2160–2167, Sep. 2006.

[3] Y. Chiu, B. Nikolic, and P. R. Gray, "Scaling of analog-to-digital converters into ultra-deep-submicron CMOS," in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2005, pp. 375-382.

[4] A. Matsuzawa, “Design challenges of analog-to-digital converters in nanoscale CMOS,” IEICE Trans. Electron., vol.E90-C, no.4, pp.779–785 , April 2007.

[5] Y. Arai and T. Baba, “A CMOStime to digital converter VLSI for highenergyphysics,” in VLSI Circuits Symp. Dig., Aug. 1988, pp. 121– 122.

[6] E. Iroaga and B. Murmann, “A 12-bit 75-MS/s pipelined ADC using incomplete settling,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 748–756, Apr. 2007.

[7] B. Murmann and B. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040–2050, Dec. 2003.

[8] T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” in ISSCC Digest of Technical Papers, 2006, pp. 220–221.

[9] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies, ”IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658–2668,2006. K. Elissa, “Title of paper if known,” unpublished.

[10] S.-K. Shin, Y.-S. You, S.-H. Lee, K.-H. Moon, J.-W. Kim, L. Brooks, and H.-S. Lee, “A fully-differential zero-crossing-based 1.2 V 10 b 26 MS/ pipelined ADC in 65 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits Dig Tech. Papers, Jun. 2008, pp. 218–219.

[11] R. J. Baker et al., CMOS Circuit Design, Layout and Simulation, Wiley Interscience, 1st Edition, 1998.

[12] M.-C. Huang, and S.- I. Liu, “A 10MS/s to 100kS/s power-scalable fully-differential CBSC 10-bit pipelined ADC with adaptive biasing,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 57, pp. 11-15, Jan. 2010.

[13] H. Roh, H. Lee, Y. Choi and J. Roh, “A 0.8-V 816-nW delta–sigma modulator for low-power biomedical applications,” Analog Integrated Circuits and Signal Processing, pp. 101- 106, Jul. 2009.

[14] Schreier, R. �� toolbox. MATLAB Central File Exchange, http:// www.mathworks.com/matlabcentral/fileexchange/.

[15] F. Maloberti, Data Converters. Springer, 2007. [16] T. Christen, T. Burger, Q. Huang, “A 0.13�m

CMOSEDGE/UMTS/WLAN Tri-Mode �� ADC with -92dB THD” in IEEEISSCC Dig. Tech. Papers, pp.240-241, Feb. 2007.

[17] T.-H. Chang, and L.-R. Dung, “Fourth-Order Cascade Sigma-Delta Modulator Using Tri-Level Quantization and Bandpass Noise Shaping for Broadband Telecommunication Applications,” IEEE Transactions on Circuits and Systems, July. 2008, pp.1722-1732.

[18] R. delRio, “Highly linear 2.5-V CMOS �� modulator for ADSL+,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 47–62, Jan. 2004.

IEEE CCECE 2011 - 000053