A 0.5V Start-up 87% Efficiency 0.75mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery

and Solar Cell Operation Sensor Network Micro-Computer Integration

Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, and Toru Shimizu

Renesas Electronics Corporation, Japan.

Abstract – An on-chip low power single-inductor dual-output DC-DC converter is proposed for battery and solar cell operating sensor network applications. By a new feed-forward control, a test chip fabricated by 190nm CMOS achieves a high efficiency of 87% at the practical load condition with a small area size of 0.75mm2 without any compensation capacitor. In addition, the fluctuation of the output voltage remains within 100mV when the input voltage changes from 1V to 2V. For a solar cell operation, 0.5V start-up is achieved with a process technology of flash-memory embedded micro-computers by utilizing forward back bias. A super capacitor is charged up to 5V from a solar cell with an implemented MPPT.

I. Requirements for SIDO DC-DC Converter Design Recently, wireless sensor networks have been widely used

to improve energy efficiency by controlling building, office and home environments [1]. A large amount of sensor nodes are distributed to monitor the environmental parameters such as temperature, humidity, illumination intensity and so on. Each node consists of a micro-computer controlling the node operation, sensors and sensor interfaces and an RF module to send the measured data. As the sensor nodes are placed everywhere indoors, battery operation is required for the flexibility of the placement. A single-inductor dual-output (SIDO) architecture is suitable as shown in Fig.1. One output supplies the power between 3V and 5V with around 10mA for sensors. The other supplies the power of 3V with more than 25mA for a micro-computer, the control circuits (Cntrl CKT) and a sensor network RF module such as ZigBee. The SIDO converter is better to be embedded with a micro-computer in a small area because of size limitation of the sensor nodes. Feed back control is not chosen because it requires additional capacitors outside in many cases for compensation. Its slow response of almost 1ms is another reason [2]. Many types of discontinuous current mode (DCM) operation have been proposed as non feed back control methods. Fig.2 (i) shows the case in which each output is alternately charged in every cycle [3, 4]. During the clock MCLK is high (ton), the inductor stores current. During the clock MCLK is low (toff), the current is delivered to the output VCCX or VCCY when the signal CLKX or CLKY is low, respectively. In Fig.2 (ii), both outputs are charged in every cycle [5]. Fig.2 (iii) shows the pseudo continuous current mode (CCM) which was proposed to reduce the peak inductor current IL [6]. DCM requires a large transistor size to obtain a high efficiency due to a large inductor peak current. The efficiencies of 88.4% and 89.4% were shown with the chip sizes of 2.4mm2 [3] and 4.25mm2 [6], which are too large for micro-computer

integration. Furthermore, the obtained efficiency is only when each output supplies almost same amount of load current. This is another constraint for sensor network application.

Cntrl CKT

Sensors

Micro-computer

VCCX(3-5V)

VCCY(3V)IL CLKX

RF

>25mAMCLKCLKY

Fig.1 SIDO DC-DC converter for battery operating sensor node.

Fig.2 Conventional non-feed back controls of charging outputs.

Fig.3 SIDO DC-DC converter for solar cell operating sensor node.

When the sensor nodes are placed outdoors, a solar cell

is used to supply power because of battery maintenance freedom. The electric power generated by a solar cell is stored in a super capacitor when the sensor node is sleeping. The super capacitor supplies power to the sensor node when it is working through a low drop-out regulator (LDO) as shown in Fig.3. The clock pulse width is modulated by a maximum power point tracking (MPPT) control to extract maximum power from a solar cell. The SIDO architecture also has advantage that one output charges a super capacitor and the other supplies the power for control circuits in parallel. The converter is required to start up from a single cell voltage of 0.5V [7]. Previously it is implemented by a low threshold voltage process technology [8] or using a dedicated start-up IC [9] which are not suitable for micro-computer integration.

This paper describes an on-chip low power SIDO DC-DC converter operating with both a battery and a single solar cell. A high efficiency of 87% is achieved with a small area size of 0.75mm2 and no external components for compensation by

978-1-4673-1556-2/12/$31.00@2012 IEEE

using a new feed-forward control [10]. The efficiency is obtained at the practical load current condition owing to the low power control circuits. Quick response is also realized because the duty ratio is determined immediately from the input voltage. 0.5V start-up without a special process technology or any additional ICs is realized with two-stage start-up architecture. A simple MPPT function is also implemented. This converter is applicable to a power supplier for a sensor node both indoor and outdoor systems with small foot-print.

II. New SIDO Architecture with Feed-Forward Control The block diagram of the proposed converter is shown in

Fig.4. VBAT is an input voltage. The first output VCCX can be set between 3V and 5V to deal with a wide variety of supply voltage for sensors. The voltage of the second output VCCY is predefined at 3V. DVCCY supplies the power for the internal control circuits. When VCCY reaches 3V, power lines become available by setting the signal PWS at low. The PMOS PX1 and PY1 have two roles. One is slew rate control of VCCX and VCCY and the other is to shut down the power lines when large load current flows. For each cycle, an inductor stores the current and delivers the current to either one of outputs. Each output is alternately charged for several cycles in CCM as shown in Fig.5.

Fig.4 Block diagram of SIDO DC-DC boost converter.

Fig.5 Proposed feed-forward control of charging outputs.

The control circuits (Cntrl CKT) are composed of two parts

as shown in Fig.6, the feed forward pulse width modulator (FF-PWM) and the clock signal generator (CLK Gen). FF-PWM generates the basic clock CLK as shown in Fig.7. The duty ratio is obtained immediately when the output

changed. A precise ratio is obtained even at low VBAT since ton and toff periods are determined separately.

Fig.6 Control circuits (Cntrl CKT) in Fig.4 composed of two parts.

Fig.7 Feed-forward pulse width modulation (FF-PWM).

In an ideal case, ton/toff ratio is set as (Vout/ Vin – 1) [11]

as follows.

VRVC

IaVC

tonBAT

REFREF ⋅⋅=

⋅= ,

VRIcsRVC

IaIcsVC

toffBAT

REFREF−⋅

⋅⋅=

−⋅

=

Therefore,

1V

RIcstoffton

BAT

Y −⋅

= for VCCY,

( )

1V

RRIcstoffton

BAT

YX −+⋅

= for VCCX.

The resistor R is equal to RY or RX + RY when VCCY or

VCCX is selected due to the signal SCTY. By setting RY = (expected VCCY = 3V) / Ics and RX + RY = (expected center value of VCCX = 4V) / Ics, desired duty ratio is obtained. Expected VCCX can be set accordingly to VREF2 since Ics can be given by VREF2 when VCCX is selected. If VREF2 is set as same with VREF, VCCX = 4V is obtained. By setting VREF2 as 1.25*VREF or 0.75*VREF, VCCX =5V or VCCX = 3V is obtained, respectively.

In the case of solar cell operation, MPPT control is used instead of FF-PWM control. The converter has a simple version of MPPT. When VBAT becomes lower than 80% of its open voltage, the operation is halted. This case occurs when

more current is pulled from the solar cell than that it can afford. After the input voltage recovered, it resumes the operation again. The converter stops when VBAT becomes below 0.4V. As results, the duty ratio is automatically determined to obtain the maximum solar power.

CLK Gen generates the main clock MCLK and the rectifier PMOS control signals CLKX and CLKY from CLK through non-overlap circuits as shown in Fig.8. The short current can be prevented since the NMOS driver and the PMOS rectifiers do not turn on at the same time. Whenever the VCCY is lower than the expected voltage, SCTY is set at high. The signal CLKY becomes active and VCCY is charged in prior to VCCX. As a result, the control circuits Cntrl CKT operate stably. After VCCY reaches to 3V, VCCX will be selected. When both outputs reach to the expected voltages, the operation stops by setting the NOP signal high.

Fig.8 Clock generator (CLK Gen).

III. 0.5V Start-up Circuits

The start-up block is composed of charge pump and ring oscillator as shown in Fig.9. When VBAT is below 1.5V, the output of Vin detector is high. When VBAT is above 0.5V, NMOS N1 and PMOSs P1 and P2 turn on, then the power is supplied both to the local oscillator and the charge pump. The back gate voltages VB1 and VB2 are given as VBAT – VF, where VF is a forward voltage drop of a parasitic PN diode between the source and back gate of the PMOS P1. The voltage of VP is VBAT because P1 turns on. Therefore, PMOSs in the local oscillator are deeply forward biased. The voltage VCP is raised and supplied as VRNG via PMOS P3. VRNG is the supply voltage for the ring oscillator which generates the sub clock SCLK with a duty of 50%.

When VBAT is in the range between 1.5V and 3V, the local oscillator and the charge pump are isolated from VBAT because P1 and P2 turn off. VBAT is supplied directly as VRNG. The back gate voltages VB1 and VB2 become equal to VBAT and VBAT / 2 due to the resistors R2. Since N1 and N3 are off and N2 is on, the gate and source voltages of P2 are also equal to VBAT / 2 due to the resistors R1. As a result, the voltage between any nodes in thin oxide transistors never exceeds VBAT / 2. They do not suffer from larger voltage than the breakdown of 2V.

Both of the control signals CLKX and CLKY remain high

and the back gates of PMOS PX0 and PY0 in Fig.5 are connected together to DVCCY during the start-up period. Consequently DVCCY is charged up through parasitic PN diodes between the back gate and source of PX0 and PY0. When VCCY reaches to 2.5V, FF-PWM begins to operate instead of the ring oscillator.

Fig.9 Start-up circuits.

VI. Implementation and Experimental Results

A test chip was fabricated by a 190nm CMOS technology as shown in Fig.10. The threshold voltage is 0.7V. The area size is 1.7mm x 0.44mm.

Fig.10 Micrograph of SIDO DC-DC converter test chip.

Fig.11 Start-up waveforms when VBAT equal to 0.5V.

Fig.11 shows the start-up waveforms when VBAT is equal

to 0.5V. The charge pump starts to charge VCP. When the voltage VCP reaches to 1.2V, ring oscillator works. This result also shows that DVCCY is charged up first. It takes 13sec to obtain the expected output voltages.

Fig.12 Experimental results of efficiency for IloadX.

Fig.13 Experimental results of efficiency for IloadY.

Fig.14 Measured waveforms of line regulation at IloadX=1mA,

IlaodY=6mA. X and Y mean charging VCCX and VCCY.

Fig.12 and Fig.13 are the measured results of efficiency dependence on IloadX and IloadY. In Fig.13, IloadY is kept at 4mA. VCCX maintains within 5V - 10% while supplies 10mA, 20mA and 40mA to IloadX at VBAT of 1V, 1.5V and 2V, respectively. In Fig.13, IloadX is kept at 6mA. VCCY maintains within 3V - 10% while supplies 15mA, 40mA and more than 50mA to IloadY at VBAT of 1V, 1.5V and 2V, respectively. The efficiency of 87% is achieved at the practical load condition, namely VBAT of 2V and IloadY of 15mA. The power consumption of no load condition is 0.5mW measured

at the input node. Fig.14 is the line regulation results. Both VBAT and

charging output are changed. VBAT changes from 1V to 2V periodically. The output voltage fluctuation is less than 100mV.

Fig.15 shows the measured result of charging a super capacitor from a solar cell. The open voltage is 1.03V and the short current is 83mA under an indoor light condition. A super capacitor of 0.4F is charged from 0V to 5V within 80sec. VBAT level is stable at 0.77V due to the implemented MPPT.

Fig.15 Experimental results of charging super capacitor with MPPT

V. Summary

An on-chip low power SIDO DC-DC converter is developed. High efficiency is achieved with a small area size by employing feed-forward control. Long battery-life sensor node operation is realized with the minimum cost reducing external components for compensation. In addition, this converter is also applicable for a compact solar cell operating sensor node since 0.5V start-up with a process technology of flash-memory embedded micro-computer implementation.

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