A 36V Precision Programmable Gain Amplifier with CMRR Exceeding 120dB in all Gains

V. Schäffer, M. F. Snoeij, M. V. Ivanov

Texas Instruments GmbH Erlangen, Germany

schaffer_viola@ti.com, m-snoeij@ti.com, ivanov_misha@ti.com

Abstract-A 36V programmable gain amplifier (PGA) is presented with sub-20μV offset and CMRR exceeding 120dB in all gains. It is the first 36V capable precision PGA that is implemented in a high-voltage CMOS process, allowing for several important additional functions, such as the detection of input and output fault conditions and an input switch network. This switch network in addition to acting as a 2-channel multiplexer also allows for various system-level diagnostic features. All opamps used in the PGA use chopper stabilization with a notch filter that removes chopping glitches, leading to very low offset for all gains and low 1/f noise. The input referred offset voltage is below 20μV (G=128). The PGA is implemented in a 0.35um CMOS process with a 36V extension, and has a total quiescent current of 2.7mA.

I. INTRODUCTION

While many application-specific sensor interface ICs [1]

and integrated smart sensors [2] have been published in recent years, there is still a strong need for a more universal interface circuit for industrial applications. Here, apart from sensor outputs of a few millivolts, also larger signals of up to ±10V exist, such as those coming from remote transmitter outputs. These need to be processed and translated to the low voltage domain in which most A/D converters and microcontrollers operate. Moreover, these signals can have up to 10V of common mode voltage due to long signal lines, therefore common-mode rejection up to 100Hz is critical. Due to the variety of signal sources, high input impedance is essential, making systems based on resistor dividers at the input impractical. The PGAs and instrumentation amplifiers (IA) that are currently available for use in such a signal acquisition system can generally be divided into two categories. Firstly, many IAs and PGAs exists that are capable of handling the high input voltages, such as ±15V, that are still commonplace in industrial applications. In order to be able to handle such voltages, they are made in bipolar technologies, and use laser-trimming to get the required DC precision [3]. A second class of PGAs is implemented in analog CMOS technologies [4]. This allows for the use of dynamic offset cancellation techniques to improve the DC precision of the PGA, thus eliminating the need for trimming. Moreover, the use of CMOS technologies allows for the addition of several digital functions. The most important of such additional functions is the ability of the PGA to detect internal fault conditions, such as an internal amplifier railing, that might otherwise not be directly noticeable in its analog output voltage. The detection of such a fault condition can then easily

be reported to the outside world via a digital output pin or digital bus. Since this can make the overall readout system much more robust against errors, there has been a considerable interest in PGAs with such additional functionality. However, until now, the supply voltage of such PGAs is relatively low, preventing their use in many industrial applications, where an input range of ±15V is required.

In this paper, we present the first precision PGA capable of handling up to 32V inputs that is implemented in a CMOS technology, and has many additional digital control and diagnostics functions required to create a flexible and robust system. Moreover, the PGA has an unprecedented CMRR of over 120dB in all gains, and a gain linearity better than 0.001%. In order to ensure low offsets for all gains, both the input and output amplifiers use chopper stabilization to reduce their offset to the microvolt level. In order to remove chopping glitches in the output of the amplifiers, a notch filter in the chopped high-gain path of the amplifier is used [5]. This paper is organized as follows. Section II presents the system-level design of the PGA, and discusses the overall topology, amplifier topology, and design approach to enable the 36V operation of the amplifier. In section III, the key additional functionality that the use of CMOS technology allows, such as error detection circuitry, is described. In section IV, measurement results are shown. Finally, conclusions are presented in section V.

LEVEL TRANSLATION

DIGITAL I/O

GMUX

MUX

SUPPORTING CIRCUITRY

CLK

LEVEL TRANSLATION

MUX CNTRL GAIN CNTRLERROR

DET.

LTRANS

LV ANALOG

HV ANALOG

LV DIGITAL

LV_VSS

VOUT

VO_REF

VOUT

LV_VSS

HV_VDD

INPUT

INPUT

INPUT

INPUT

HV_VSS

DVDD

DGND

4x SPI7x GPIO

Fig. 1. Block diagram of the PGA presented.

978-1-4244-2362-0/08/$25.00 ©2008 IEEE. 310

II. SYSTEM LEVEL DESIGN A. Device Architecture

Of the several possible instrumentation amplifier topologies, the 3-amp topology is the best-known approach [4,6]. However, it has two important drawbacks. Firstly, the use of voltage gain in the input amplifiers reduces the input common-mode voltage range for high gains, since the outputs of the input amplifiers can rail. Secondly, the common-mode rejection ratio (CMRR) of a 3-amp topology is limited to about 80dB in low gains by the degree of matching between the gain resistors around the output amplifier. Because of these limitations, a different approach was used, as shown in Fig. 1. The input amplifiers induce the input voltage across an adjustable resistor. The current through the resistor, and thus through the output stage of the input amplifiers, is mirrored and fed into the output amplifiers, where it is converted back into a differential output voltage. Through the use of this V-I and I-V conversion, the input CM range becomes independent of the gain, and the CMRR does not depend on resistor matching, but mainly on the CMRR of the individual amplifiers and the output impedance of the mirrors. In order to ensure low overall offset for all gains, both input and output amplifiers use dynamic offset cancellation. Moreover, the DC precision of the current mirrors is critical for the overall offset, gain accuracy and linearity. Therefore, as shown on Fig. 2, these current mirrors are implemented with matched thin film resistors and amplifiers that also use dynamic offset cancellation. B. Opamp topology

The PGA topology requires a total of 8 amplifiers, that all need dynamic offset correction. In all cases, a 3-stage amplifier with chopper stabilization is used (Fig. 3), in which a chopped high-gain path ensures low offset, while a parallel feed-forward stage ensures a wide bandwidth. A notch filter in the high gain path of the amplifier filters out the chopping glitches [5]. The resulting opamps have very low offset, no 1/f noise, low white noise, and no measurable chopping glitches at the output.

C. High-Voltage Design

The design goal for the PGA was to be able to operate on a ±18V supply, with an input common-mode range of ±16V. In order to achieve this specification, a CMOS process is used that has both 5V thin-oxide and 36V thick-oxide gate transistors, all with extended drains for high-voltage (HV) operation. However, all these HV-capable transistors have a degraded performance and matching, making them unsuitable for use in gain stages of amplifiers and other places where precision is required. However, the process also allowed for the use of the better performance low-voltage CMOS transistors that can be isolated from the substrate. Therefore, throughout the device, the approach was to use isolated low-voltage transistors in the signal path for circuit blocks that are driven by on-chip voltage regulators, VREG, as illustrated in Fig. 4. A floating subregulator is used for the first stage of the input amplifier, which output voltage depends on input common mode. The output current of the input stage is cascoded, and passed to the 2nd stage current mirrors which operate at a supply voltage of 5V from the negative rail. Only the output stage of the input amplifier operates at the full 36V supply; the current mirrors again operate at 5V from either the positive or negative rail. The output amplifiers operate at a separate supply voltage of 3 to 5V, which is essential to be able to drive a low-voltage ADC. This output supply voltage can be freely chosen to be anywhere within the high voltage supplies. Similarly, the digital support circuitry also operates at a low supply of 3 to 5V that can also be freely chosen within the high voltage supply range.

Thin Film Resistors

Thin Film Resistors

Current to output amplifiers

Class AB output stage

Current fromgain network

Fig. 2. Current mirror structure.

gmin Σ

gmff

IN

INOUTgm2

notch filter

chopping switches

Fig. 3. Amplifier structure.

10V

to 3

6V

3V to

5V

3V to

5V

VREG

VREG

CURRENT MIRROR AMPLIFIERS

REST OF INPUT

AMPLIFIERS

INP

UT

AMPL

IFIE

R

OU

TPU

T S

TAG

E A

ND

M

IRR

OR

CA

SC

OD

E

INPUT STAGES

CURRENT MIRROR AMPLIFIERS

IN

VREG

VREGOUT

IN

HV_VSS

LV_VSS

LV_VDD

HV_VDD

DVDD

DGND

Fig. 4. On chip supply domains and regulators, VREG.

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III. KEY AUXILLARY FUNCTIONS

A. Detection of out-of-range conditions

A common problem in instrumentation amplifiers is detecting various conditions that can cause signal corruption while the amplifier output remains within its linear range. These can include input common-mode range violations, clipping or limiting in the intermediate stages and input faults. System-level indication and diagnostic capabilities are desired to alert the controller of a potentially invalid voltage at the amplifier output. A common way to implement this is to add comparators at the critical nodes (e.g. inputs and outputs of internal opamps) [4]. However, there are significant drawbacks: such comparators have a lot of circuitry, additional reference-generation is needed, and margins for mismatches, temperature and process variation reduce usable dynamic range.

Overload conditions can be detected within the amplifiers with minimal amount of additional circuits by detecting when an internal control loop is broken. This approach also maximizes the dynamic range and perfectly traces over temperature and process variation. Fig. 5 shows an example of indicating the negative opamp input common-mode range violation by detecting the railing of the amplifier that is driving the regulated cascode.

Similar functions were incorporated in internal opamps of the PGA to detect input common mode violation, input overload, output rail, output short and input clamp activation with corresponding digital flags and registers for system-level diagnostics.

B. Improving system level settling time

Most high voltage amplifiers incorporate protection clamps to protect the precision input transistors from overload conditions and fast input transients [3,7]. These clamps draw current from the signal source when activated. In a multiplexed system, where each channel has an RC-filter, the input to the amplifier can change instantaneously when the channels are switched. During amplifier’s slew and settling the input protection clamps are activated and drain charge from the input filter capacitor. Depending on the filter and source characteristics the capacitor re-charging can lead to a long settling time.

To avoid input current and thus improve system level

settling time, a slew buffer was added (Fig 6). This low precision buffer contains thick 36V oxide MOS transistors that tolerate large differential voltages, and is switched into the signal path when an overload condition is anticipated. It supplies the current for the clamps of the precision stage thus preventing current drawn from the input. It is removed from the signal path after the clamp activating condition disappears and does not affect system accuracy and noise.

C. Input switch network

The use of the high voltage CMOS process enables unique functionality not previously integrated on precision industrial IAs. The integrated input switch network shown on Fig. 6. serves as a 2 channel multiplexer and provides means of reconfiguring the amplifier for system level trouble shooting and “housekeeping”. For example the inputs can be shorted for calibration, an absolute voltage can be measured at either of the inputs or a wire-break at the input can be detected by connecting current sources to the input pins.

Fig. 7. Chip micrograph of the 36V precision PGA.

HV_VSS

HV_VDD

BUF

BUF

PGA

INPU

TS

Fig. 6. The input switch network and the slew-buffer.

VDSAT

Folded cascode

MIN1 MIN2

MS

MSCI1

IN

ERRCM A1

IN

V_C

M

VDMSC

VGMSC

Fig. 5. Detection of the violation of the input common mode range. When the input common mode voltage V_CM approaches the negative rail, MSC starts to triode until the amplifier can’t correct for this at its gate and rails.

INPUT OPAMPS

INPUT SWITCH NETWORK

OUTPUT OPAMPS

CURRENT MIRRORS

CURRENT

GAIN NETWORK

GAIN NETWORK

INPUT OPAMPS

OU

TPU

T

OPA

MPS

CURRENT MIRROR

CURRENT MIRROR

SWITCH NETWORK

DIGITAL INTERFACE

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IV. MEASUREMENT RESULTS

A chip micrograph of the PGA fabricated in a 0.35um analog CMOS process with a 36V extension is shown in Fig. 7. The chip has an area of 3.6 x 2.4mm2. The common mode rejection ratio (CMRR) distribution is shown on Fig. 8. The untrimmed CMRR exceeds 120dB (<1μV/V error) in all gains. The input offset voltage is better than 20μV (G=128). The 0.1Hz to 10Hz peak-to-peak input referred noise is measured to be 460nVpp (G=128). Since the noise spectral density is flat due to the chopped architecture, the total noise can be reduced by longer integration. Despite the V-I and I-V conversions and the multiple supply domains in the signal path the gain linearity is better than 0.001%. The PGA has a gain range of 0.125 to 128 in binary steps with an auxiliary gain of 1 or 1.375 in the output stage. The less than 0.1% gain error and less than 2ppm/°C gain error drift is determined by the matching of the untrimmed thin-film resistors. The total quiescent current is 2.2mA from the high voltage input supplies and 730uA from the low voltage output supplies. The 3dB bandwidth in G<4 is 2MHz. For gains larger than 4 the 3dB bandwidth is reduced by half for each 6dB gain step. Due to the notch filters used in the amplifiers the chopping glitches are practically invisible even in high gain. This is illustrated on the scope photo on Fig. 9.

C M R R (G=1)

0

50

100

150

200

250

<-1.

00

<-0.

70

<-0.

40

<-0.

10

<0.2

0

<0.5

0

<0.8

0

>1.0

0

uV /V

Sam

ple

Cou

nt

M ean = -0.18S td. dev. = 0.24

C M R R (G=128)

<-1.

00

<-0.

70

<-0.

40

<-0.

10

<0.2

0

<0.5

0

<0.8

0

>1.0

0

uV /V

M ean = -0.03S td. dev. = 0.05

Fig. 8. The CMRR distribution (over 300 samples).

V. CONCLUSIONS

A precision 36V programmable gain amplifier was presented targeted for industrial signal acquisition applications. By using an architecture that converts the input voltage to a current, mirrors this current by precision current mirrors and then converts the current back to voltage at the output stage an untrimmed common-mode rejection ratio over 120dB in all gains was achieved. Additionally, this architecture increases the input common-mode range and provides for level translation between the input and output supply domains. The offset voltage and 1/f noise were eliminated by the use of chopper stabilization in the internal amplifiers. Virtually no chopping glitches are visible at the output due to the utilization of notch-filters inside the amplifiers.

ACKNOWLEDGMENTS

The authors would like to thank J. Metzger, D. Trifonov, J. Doorenbos, S. Gulas, G. Haug and R. Burt for their design and characterization support and the layout team J. Graner, B. Young, R. Emrich, D. Bellemare, T. Lis.

REFERENCES

[1] M. Kämäräinen et al. , “A 1.5µW 1V 2nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer”, ISSCC Digest Techn. Papers, 2008, pp. 578-579 [2] C. Schott et al. , “CMOS Single-Chip Electronic Compass with Microcontroller”, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2923-2933, Dec. 2007 [3] PGA205 Data Sheet, Texas Instruments Inc., Dallas, TX, 1993 [4] A.T.K. Tang, ‘‘Enhanced Programmable Instrumentation Amplifier’’, Proceedings of IEEE Sensors, 2005, pp. 955-958

[5] R. Burt and J. Zhang, “A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path”, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2729-2736, Dec. 2006 [6] E. Nash, “A Practical Review of Common Mode Voltages and Instrumentation Amplifiers”, Sensors Magazine, July 1998. [7] AD8250 Data Sheet, Analog Devices Inc., Norwood, MA, 2007

Table 2. Comparison to other similar High-Voltage PGAs.

Parameter THIS PGA PGA205 AD825x

Supply Voltage Range 10-36V 9-36V 10-30V Input Referred Offset Voltage (high gain) VOS Temperature Drift

20μV 0.1μV/C

62μV 0.6μV/C

260μV 1.7μV/C

Common Mode Rejection Ratio (G=1) 120dB 80dB 80dB

On Chip MUX and Diagnostic Functions yes no no

Table 1. Summary of the measured PGA performance.

Parameter Mean Std. dev. Input Referred Offset Voltage (VOS) (G=128) VOS Temperature Drift

-0.4μV -0.01μV/C

6.3μV 0.06μV /C

Gain Non-linearity 0.0003% 0.0002% Gain Error (GE) (G=128) GE Temperature Drift

-0.036% -1.7ppm/C

0.022% 0.1ppm/C

Common Mode Rejection (CMRR) (G=128) (G=1)

-0.03μV/V -0.18μV/V

0.05 μV/V 0.24 μV/V

Supply Current (High Voltage Input Supplies) (Low Voltage Output Supplies)

2.2mA 0.75mA

Gain Range 1/8 to 128 in binary steps x (1 or 1.375)

0.1-10Hz Input Referred Noise (G=128) 460nVp-p

CMRR @ 1KHz 90dB

Bandwidth (G<=4) 2MHz * The statistical data is from 330 samples measured. The drift statistics are from 12 samples measured.

Fig. 9. Scope photograph showing no differential output glitch (G=128).

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