ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA - 1 - Interconnect Working Group Whats up with wires? 14 July 2010 San Francisco USA Christopher

ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA - 1 -

Interconnect Working Interconnect Working GroupGroupInterconnect Working Interconnect Working GroupGroup

What’s up with wires?14 July 2010

San Francisco USAChristopher Case


ITWG Regional Chairs

US Christopher Case US Christopher Case

Japan Tomo Nakamura Hideki Shibata

Japan Tomo Nakamura Hideki Shibata

EuropeHans-Joachim BarthAlexis Farcy

EuropeHans-Joachim BarthAlexis Farcy

Korea Hyeon-Deok Lee Sibum Kim

Korea Hyeon-Deok Lee Sibum Kim

TaiwanDouglas CH Yu

TaiwanDouglas CH Yu


Partial List of Contributors

• Shuhei Amakawa• Nobuo Aoi• Sitaram Arkalgud• Lucile Arnaud• Koji Ban • Hans-Joachim Barth• Eric Beyne• Christopher Case • Chung-Liang Chang• Hsien-Wei Chen• Gilheyun Choi• Jinn-P. Chu• Mike Corbett • Alexis Farcy• Paul Feeney• Masayuki Hiroi• Harold Hosack

• Masayoshi Imai• Raymond Jao • Shin-Puu Jeng • Sibum Kim• Mauro Kobrinsky• Nohjung Kwak • Hyeon Deok Lee• Scott List• Anderson Liu• Didier Louis• JD Luttmer• Toshiro Maekawa• Akira Matsumoto• Azad Naeemi • NS Nagaraj• Tomoji Nakamura • Yuichi Nakao

• Akira Ouchi• Peter Ramm• Rick Reidy • Scott Pozder • Philip Pieters • Andy Rudack • Larry Smith• Mark Scannell• Hideki Shibata• Michele Stucchi• Wen-Chih Chiou• Weng Hong Teh• Thomas Toms • Manabu Tsujimura • Kazuyoshi Ueno• Detlef Weber• Osamu Yamazaki

0710


Interconnect scope• Conductors and dielectrics

– Starts at contacts– Metal 1 through global levels – Includes the pre-metal dielectric (PMD)

• Associated planarization • Necessary etch, strip and cleans• Embedded passives• Global and intermediate TSVs for 3D • Reliability and system and performance issues• “Needs” based replaced by – scaled,

equivalently scaled or functional diversity drivers.

ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA

MPU Cross-Section

Dielectric Capping

Layer

Copper Conductor with

Barrier / Nucleation

Layer

Pre-Metal Dielectric

Tungsten Contact Plug

Inter-Mediate(=M1x1)


Metal 1Metal 1

Passivation

Dielectric

Etch Stop Layer

ASIC Cross-Section

Semi-Global (=M1x2)

Semi-Global (=M1x2)

Metal 1 Pitch

Via

Wire

Via

Wire

Via

Wire

Metal 1 Pitch

Global (=IMx1.5~2µm)Global (=IMx1.5~2µm)



Metal 1Metal 1

Global (=IMx1.5~2µm)

Global (=IMx1.5~2µm)

1) MPU : Revised hierarchy2) ASIC : No drastic change, however semi-global should be kept at 2 x M1

Hierarchical Cross Sections


Technology RequirementsNow restated and organized as• General requirements

– Resistivity– Dielectric constant– Metal levels– Reliability metrics

• Level specific requirements (M1, intermediate, global)– Geometrical

• Via size and aspect ratio• Barrier/cladding thickness• Planarization specs

– Materials requirements• Conductor effective resistivity and scattering effects

– Electrical characteristics• Delay, capacitance, crosstalk, power index


Difficult challenges (1 of 2)Difficult challenges (1 of 2)• Meeting the requirements of scaled metal/dielectric systems

– Managing RC delay and power• New dielectrics (including air gap)• Controlling conductivity (liners and scattering)

– Filling small features• Barriers and nucleation layer• Conductor deposition

– Reliability• Electrical and thermo-mechanical

• Engineering a manufacturable interconnect stack compatible with new materials and processes – Defects– Metrology– Variability


Difficult challenges (2 of 2)• Meeting the requirements with equivalent scaling

– Interconnect design and architecture (includes multi-core benefits)

– Alternative metal/dielectric assemblies• 3D with TSV

– Interconnects beyond metal/dielectrics• 3D• Optical wiring• CNT/Graphene

– Reliability• Electrical and thermo-mechanical

• Engineering a CMOS-compatible manufacturable interconnect system– Non-traditional materials (for optical, CNT etc.)– Unique metrology (alignment, chirality measurements,

turning radius etc)


Eff

ecti

ve D

iele

ctr

ic C

on

sta

nt;

keff

Year of 1st Shipment

ITRS1999

ITRS2001

ITRS2005

ITRS2003

Before 2001,unreasonable RM

without logical basis

Before 2001,unreasonable RM

without logical basis

ITRS2007-2010

Historical Transition of ITRS Low-k Roadmap

2009 decreased max bulk by 0.1 - no significant change on eff in 2009

2010 no changes

2009 decreased max bulk by 0.1 - no significant change on eff in 2009

2010 no changes

Since 2003, based on wiring capacitance calculation of three kinds of dielectric structures and validated against publicationsSince 2003, based on wiring capacitance calculation of three kinds of dielectric structures and validated against publications

2009 Summer Conference


2010 Low k or nothing?

Air gap architectures will be required for bulk <2.0•No viable materials expected to be available.•Mechanical requirements easier to achieve with air-gaps.

•End of the material solution and the beginning of an architecture solution.

Year of Production 2010 2011 2012 2013 2014 2015

MPU/ASIC Metal 1 ½ Pitch (nm)(contacted)

45 38 32 27 24 21

Interlevel metal insulator – bulk dielectric constant (κ)

2.3-2.5 2.3-2.5 2.3-2.5 2.1-2.3 2.1-2.3 2.1-2.3

Year of Production 2016 2017 2018 2019 2020 2021 2022 2023 2024


18.9 16.9 15.0 13.4 11.9 10.6 9.5 8.4 7.5

Interlevel metal insulator – bulk dielectric constant (κ)

1.9–2.1 1.9–2.1 1.9–2.1 1.7–1.9 1.7–1.9 1.7–1.9 1.5–1.7 1.5–1.7 1.5–1.7


Air Gap

Pictures (top left, clockwise): NXP, IBM, Panasonic, TSMC

Approaches•Creation of air gaps with non-conformal deposition

•Removal of sacrificial materials after multi-level interconnects


2010 Barrier/Nucleation/Resistivity

• ALD barrier processes and metal capping layers for Cu are lagging in introduction – key challenge

• Resistivity increases due to scattering and impact of liners

•No known practical solutions

Year of Production 2010 2011 2012 2013 2014 2015

MPU/ASIC Metal 1 ½ Pitch (nm)(contacted) 45 38 32 27 24 21

Barrier cladding thickness Metal 1 (nm)

3.3 2.9 2.6 2.4 2.1 1.9

Conductor effective resistivity (µΩ‑cm) Cu Metal 1

4.08 4.30 4.53 4.83 5.2 5.58

Year of Production 2016 2017 2018 2019 2020 2021 2022 2023 2024


18.9 16.9 15.0 13.4 11.9 10.6 9.5 8.4 7.5

Barrier cladding thickness Metal 1 (nm)

1.7 1.5 1.3` 1.2 1.1 1.0 0.9 0.8 0.7

Conductor effective resistivity (µΩ‑cm) Cu Metal 1

6.01 6.33 6.7 7.34 8.19 8.51 9.84 11.30 12.91


Cu Contact Transition Prospective 5% of total parasitic resistance for contact resistance

(agreed with PIDS, FEP and INTC in 2008)

Estimation of contact resistance used to forecast timing for Cu

TargetW-plugCu-plug

45/40nm 32/28nm 22/20nm

marginal

W-plug will be applicable until 22/20nm node at 2013. 　

Cu-plug will be able to satisfy the requirement beyond 15/14nm node after 2016.

OK

0

50

100

150

200

2007 2010 2013 2016Year

Re

sis

tan

ce

(

/c

on

tac

t)

15nm

NG

65~54nm 45~32nm 27~21nm 19nm~ITRSCommercial

Assumption•Aspect ratio=5.5•Barrier for W-plug

PVD-Ti 10nm@btm, 2nm@sideCVD-TiN5nm@btm/side

•Barrier for Cu-plugPVD-Ta(X) 5nm@btm, 1nm@sideCVD-Ru(X) 2nm@btm/side


0.1

1.0

10.0

2009 2012 2015 2018 2021 2024Year

Jmax

JEM

- 15 -

Wire current limit – width dependence

• The color boundaries may actually be width-dependent.– Hu et al., Microelectronics Reliability, vol.46, pp.213-231, 2006.

• Jmax will increase with frequency and reducing cross-section, while JEM will scale with the product w*h according to EM lifetime dependence on wiring width

0.1

1.0

10.0

100.0

2005 2010 2015 2020 2025

Year

Jmax

(M

A/c

m2)

Jmax 2008

Jmax 2007

2008 Update 2010 To be revised


H. Shibata added published data based on Yokogawa et. Al. IEEE Trans on ED.2008

EM

Lif

etim

e Im

pro

vem

ent

Rat

io

Normalized Resistance Increase Ratio

CuSiN

CuAl

CoWP

CuSiN （ 1 ）

CuSiN （ 2 ）

CuGeN

CuSi(N)+ Ti-BM

＜ CoWP-Cap ＞

Si

Si

SiSi

SiSi Si

SiSi

Si

Si

SiSi

Al

Al Al

Al

Al

Al

Al

Al

AlAl

AlAl

AlAlAl Al

＜ CuAl-Alloy ＞

＜ CuSiN-Cap ＞

＜ CuGeN-Cap ＞

Ge GeGeGe

＜ CuSiN-Cap+Ti＞

Metal CappingVarious lifetime improvement approaches against the resistivity increase


High Density TSV Roadmap or“enabling terabits/sec at femtojoules/bit”

• The Interconnect perspective - examples:– High bandwidth/low energy interfaces between memory and logic– Heterogeneous integration with minimal parasitics (analog/digital, mixed substrate materials, etc.)– “Re-architect” chip by placing macros (functional units) on multiple tiers (wafers) and connect using HD

TSVs• Defined a 3D interconnect hierarchy

• TSV dimensions• Minimum contact pitches• Overlay accuracy

– Described process modules


Emerging Interconnect Changes

OUT:• Air gaps Process Module Section

•Increasing maturity of integrated air gap solutions

• 3D Process Module and Architecture Sections•3D with TSVs nearing production

IN:• Focus on Cu Replacements

• Section on Native Device Interconnects

• Identified need to jointly consider switch and interconnect properties of new switch options


All roads lead to C?

- 19 -


Native Device InterconnectsNanowires GNRs

CNTs Spin Transport

• Doped NWs require silicidation for lengths > 1µm

•Multi-fanouts are very difficult

•Serial, multi-input AND gates are easy

•Multi-fanouts are easy•Multi-layer routability incurs quantum resistance

•Diffusion and spin wave transport are 1000 times slower than electron transport

•Spin relaxation lengths are ~ 1µm

1k/µm

1 M

12k

mfp


Potential interconnect state variables

GA Tech is using a Benchmarking Approach:

Define possible transportation mechanisms in general

Model delay and energy per bit for various transport mechanisms.

Benchmark new state variables against their conventional counterpart as a function interconnect length.

From Naeemi et al.

Transport Mode

Information Token

Diffusion Direct ExcitonsIndirect ExcitonsSpinPseudoSpin

Drift Indirect ExitonsSpinPseudospin

Ballistic Transport (Fermi Velocity)

SpinPseudospin

Spin Wave Spin

EM Waves Photons Plasmons


Delay versus Length

Communications of new state variables are all slow compared to conventional CMOS interconnects.

Interconnect Length (Gate Pitch)

Del

ay (

ps)

CMOS (Min-Size Driver)

Diffusio

n

Drift Ballistic

CMOS (5x Driver)

Spin Waves (104 m/s)

Spin Waves (105 m/s)Two spin wave phase velocities of 104 (realistic) and 105 m/s (optimistic) are considered.

Driver delay is not included for new state variables (upper bound performance)


Required Area Down-Scaling

Important implications at the Device and architecture levels.

Novel interconnects can compete with their conventional counterparts only if the new circuits occupy smaller areas.

To have smaller circuits switches must be smaller or same functions can be obtained with fewer switches.

For longer interconnects larger circuit area scaling is needed.

For a given area scaling, maximum circuit size with no signal conversion can be obtained.

Diffusion

Drift, 0.8V

Ballistic

Spin Waves (105 m/s)

Interconnect Length (Gate Pitch)

Nee

ded

Are

a S

calin

g A

CM

OS/

AP

ost-

CM

OS


Energy per bit

ESWB 0M .HextV

0 410-7H / m

M magnetization change A/m

Hext External magnetic field Oe

V= Volume of the interconnectm3

For a Co30Fe70 SWB, energy is taken to be 1aJ/um*

* A. Khitun et al, Nanotechnology, vol. 18, no. 46, 2007.

CMOS

DIFFUSION

DRIFT,0.8V

SWB

The excitation energy has been optimistically assumed to be negligible.


Emerging Interconnect Summary Table• Interconnect options include Cu Extensions, Cu

Replacements and Native Device Interconnects

Option Potential Advantages Primary ConcernsOther metals (W, Ag, silicides)

Potential lower resistance in fine geometries

Grain boundary scattering, integration issues, reliability

Nanowires Ballistic conduction in narrow lines

Quantum contact resistance, controlled placement, low density, substrate interactions

Carbon Nanotubes

Ballistic conduction in narrow lines

Quantum contact resistance, controlled placement, low density

Graphene Nanoribbons

Ballistic conduction in narrow films, planar growth

Quantum contact resistance, control of edges, deposition and stacking

Optical (interchip)

High bandwidth, low power and latency, noise immunity

Connection and alignment between die and package, optical /electrical conversions

Optical (intrachip)

Latency and power reduction for long lines, high bandwidth with WDM

Benefits only for long lines, need compact components, integration issues, need WDM

Wireless Available with current technology, wireless

Very limited bandwidth, intra-die communication difficult, large area and power overhead

Superconductors Zero resistance interconnect, high Q passives

Cryogenic cooling, frequency dependent resistance, defects, low critical current density

~Example of Approaches for Cu Replacements ~


Formidable Task: Fabricating Dense Bundles of SWNTs

Fabricating Bundles of Densely Packed SWNTs for interconnects has proven very challenging.

Making contacts to horizontal bundles of SWNTs is very difficult.

Promising progress in creating aligned isolated SWNTs by transferring SWNTs grown on sapphire to other substrates.

Single SWNTs are too resistive for general purpose CMOS circuits.

Y. Nishi and H.-S. Philip Wong (Stanford) 26

Young Lae Kim et al. (RPI, RICE & NorthEastern Univ


Graphene – a promising interconnect option beyond Cu/Low k?

Graphene Potentials•Device/interconnect synergism•Tunable bandgap•Ballistic transport for > 10m•Planar technology•Excellent Jmax

•Potential CVD deposition process

Graphene Areas for Research•Layer to layer coupling/scattering•Low T CVD deposition•Effective bandgap control


PrognosisInterconnects can impose major limits on both charge and non-charge based devices.

Most transport mechanisms for novel state-variables are relatively slow.

For the same speed, the new circuits must be smaller in terms of physical area.

The new devices must offer better delay-energy trade-offs compared with conventional CMOS devices.

Interconnects have important implications at the device, circuit and architecture levels.


Summary 2010• 3D and air gaps moved out of emerging sections • Low-k – unchanged – second time in 10 years

– Air gaps expected to be solution for kbulk <2.0• Jmax current limits are width dependent - a new concern• Barriers and nucleation layers are a critical challenge

– ALD barrier process is lagging in introduction – sub 1 nm specs– Ru hybrid approaches proliferating– Capping metal for reliability improvement

• New Interconnect 3D TSV roadmap tables• Cu contact need expected >2013• Emerging Interconnect Properties being developed• First principle consideration of interconnects properties for new switches – CNT, graphene, nanowires etc.

Documents

ITRS 2010 Summer Conference – 14 July 2010 San Francisco, CA - 1 - Interconnect Working Group Whats up with wires? 14 July 2010 San Francisco USA Christopher