Lab in Semiconductor Devices - 中興大學教職員工網頁web.nchu.edu.tw/pweb/users/fansen_wang/lesson/2970.pdf · 2007/9/13 Lab in Semiconductor Devices / NCHE EE / Prof. F

Lab in Semiconductor Devices

Thin-Film Transistor

元件及製程簡介

NCHU EENCHU EE, 汪芳興

2007/9/13 Lab in Semiconductor Devices / NCHE EE / Prof. F. H. Wang Page 2/84

課程大綱課程大綱

江雨龍、汪芳興期末報告(每人)1/818

助教TFT製程實作10/23~7~17

江雨龍、汪芳興期中報告(每組)10/166

助教半導體實驗室參觀10/95

江雨龍半導體實驗室環境與設備簡介10/24

中秋節(放假)9/253

汪芳興TFT製程及元件介紹9/182

講師上課內容日期週次


Outlines

Introduction

TFT Device Structure

General TFT Process

TFT Device Physics

TFT Experiment


IntroductionThin-Film Transistor

TFT vs. SOI vs. MOSFET

Glass

GateDrainSource

SiOx

GateDrainSource

C-Si C-Si

Gate

DrainSourceBody


TFT Applications

TFT-LCDA-Si TFT

Poly-Si TFT

High Density SRAM

Nonvolatile Memory

Photo Detector Amplifier

Thermal Printer Head

Image Sensor

Finger Print Sensor


Outlines

Introduction


General TFT Process

TFT Device Physics

TFT Experiment


Electrical Characteristics of TFT

Device MOSFET LTPS TFT a-Si TFT Base

material Crystal Si Polycrystalline

-Si Amorphous

-Si Mobility 650 20-500 0.5

Design rule 0.09 um 2 um 4 um Frequency 1GHz 10MHz 100KHz Substrate Si wafer Glass Glass

Circuit CMOS CMOS NMOS


Qualitative Comparison

Crystalline Poly-Si Amorphous Si

Vds = 5 V

-10 -5 0 5 10 15

Gate-source voltage [V]

10-1410-1310-1210-1110-1010-910-810-710-610-510-410-3

Dra

in c

urr

ent

[A

]

Vds = 5 V

-10 -5 0 5 10 15


10-1410-1310-1210-1110-1010-910-810-710-610-510-410-3

Dra

in c

urr

ent

Vds = 5 V

-10 -5 0 5 10 15


10-1410-1310-1210-1110-1010-910-810-710-610-510-410-3

Dra

in c

urr

ent


TFT Structures

四種常見的TFT結構

Normal(正常型) Inverted(反轉型)

Staggered(堆疊型)

Coplanar(共平面)

Drain Source

Gate

Drain Source

Drain Source

Gate

Drain Source

insulator a-Si:H layer glass metal

Gate

Gate

BCE

CHPorIS


Inverted Staggered Structure(Back-channel-etch type)

Relatively simple fabrication procedure

Relatively thick(~0.3um) a-Si:H layer, light sensitive

a-Si:H

Gate

SiNx

SourceDrain

n+


Inverted Staggered Structure(Etch-stop type)

a-Si:H and n+ must be deposited in separate PECVD runs.

Thin a-Si:H layer(~10nm), photo sensitivity reduced

Gate

SiNx

SourceDrainSiNx

n+

SiNx

a-Si:H


Top-Gate TFT Structure

TypesSelf-alignment I.I.

High leakage

Offset

Large variation

Lightly doped drain

Typical poly-Si TFT structures

Glass Substrate

Drain

Gate

Gate Insulator

Si Thin film

Source

Offset or LDD


Double-Gate Structure

Larger current-carrying capability

Extra cost of producing the second gate

Gate2

DrainSourceSiNx

n+ a-Si

a-SiSiNx

Gate1


Outlines

Introduction


General TFT Process

TFT Device Physics

TFT Experiment


TFT Processes

A-Si TFTs

Inverted Staggered Structures

Back-channel-etch type

Etch-stop type

Poly-Si TFTs

Top-gate structure

Bottom-gate structure


Substrate Input－Glass

PEP>5PEP=1

To Cell

NoPEP++

Yes

Thin Film

PhotoEtching

Tester

General Process Flow


Back-channel-etch a-Si TFT

Gate metal (mask 1)

Active island (mask 2)

Gate insulator / a-Si / n+ a-Si

ITO (mask 3)

ITO-in-middle


Back-channel-etch a-Si TFT

Data metal (mask 4) / back channel etch

Passivation / contact etch (mask 5)

ITO-in-middle


Back-channel-etch a-Si TFTITO on Top - Process Flow

Glass Substrate

Glass clean

Gate metal dep.

Gate

Gate etch

SiNx/a-Si/n+a-Si dep.

A-Si etch

S/D metal dep.

S/D etch

N+ a-Si etch

SiNx dep.

SiNx etch

ITO dep.

ITO etch


Glass Substrate

GateS D

A-Si

GateSiNx

Back-channel-etch a-Si TFTITO on Top - X-Section View

SiNxITO (pixel electrode)

SiNx

To data line


5 PEP BCE TFT Array Process Flow

GE

AS

SD

BP

ITO


五層之基本功用介紹

GE : 1.掃描線( Scan line ) 決定畫面更新,可控制AS層開關之開啟或關閉

2.作外圍金屬線路之用,避雷針……..

AS : 1.Pixel之開關,決定SD 訊號輸入pixel裡,來決定pixel之亮暗程度

2.Dummy pattern,mark,numbers,…….not for circuit layout.3.絕緣層,i.e.Repair Line cross-over pads.

SD : 1.信號線( Data line ),決定每個pixel需要到達之電壓值決定其亮度

2.作外圍金屬線路之用,避雷針……..

BP : 1.電路橋接點,將金屬層藉由BP挖Via洞將各層金屬連接,以構成所想要之電路

2.絕緣層,Dummy pattern,mark,numbers,…….not for circuit layout.

ITO : 1.Pixel之電極板,可用來控制液晶,以決定pixel透光程度

2.作外圍金屬線路串接用,因厚度較薄,通常用來作測試信號間之串接,於後段較易切斷,避免因cut線造成過多金屬屑影響電路


Etch-stop a-Si TFT

Gate metal (mask 1)

Etch stop (mask 2) / Active island (mask 3)

Gate insulator / a-Si / interlayer dielectric

ITO-on-top


Etch-stop a-Si TFT

n+ a-Si / data metal (mask 4)

ITO (mask 5)

Passivation / contact etch (mask 6)

ITO-on-top


5 PEP I/S TFT X-section view

SignalLine

TFT PixelArea

Cs

M1-Gate line (Mo/AlNd)

Channel (α-Si)

I Stop (SiNx)

Pixel(ITO)

M2-Signal line (Mo/Al/Mo)

Passivation (P-SiNx)

SiONG-SiNx

N+-α-Si


Back Channel Etch (BCE) vs. Etching Stop (Channel Protect,CHP )


IS and BCE channel process compare

IS structure might have better electric

characteristic (Ioff / µn) than BCE process.

IS structure might have lower photo current

effect.

IS structure is easily to control channel length.

Use BCE process can gain CVD capacity.

If we want to use 4 PEP, we need to use BCE

process.


Process Flow Comparison5PEPs CHP Type 5PEPs BCE Type 4PEPs BCE Type

PEP 1 1. Gate Metal Dep. 1. Gate Metal Dep. 1. Gate Metal Dep.2. Photolithography 2. Photolithography 2. Photolithography3. Dry Etching 3. Dry Etching 3. Dry Etching

PEP 2 1. SiNx/a-Si/SiNx Dep. 1. SiNx/a-Si/n+ a-Si Dep. 1. SiNx/a-Si/n+ a-Si Dep.2. Photolithography 2. Photolithography 2. S/D Metal Dep.3. Wet Etching 3. Dry Etching 3. Photolithography

4. Island and S/D Dry Etching

PEP 3 1. N+ a-Si dep. 1. S/D Metal Dep. 1. SiNx Dep.2. S/D Metal Dep. 2. Photolithography 2. Photolithography3. Photolithography 3. Dry Etching 3.Dry Etching4. Dry and Wet Etching

PEP 4 1. SiNx Dep. 1. SiNx Dep. 1. ITO Dep.2. Photolithography 2. Photolithography 2. Photolithography3. Wet Etching 3. Wet Etching 3. Wet Etching

PEP 5 1. ITO Dep. 1. ITO Dep.2. Photolithography 2. Photolithography3. Wet Etching 3. Wet Etching


Top-gate Poly-Si TFT

Laser / Island (mask 1) / Threshold voltage adjustment (mask 2)

n+ doping (mask 3)

Gate insulator / Metal 1 (mask 4) / n- doping

Buried layer (Buffer layer)


Top-gate Structurep+ doping (mask 5)

Interlayer / Contact etching (mask 6) / Metal 2 (mask 7)

Passivation (mask 8) / ITO (mask 9)


Outlines

Introduction


General TFT Process

TFT Device Physics

TFT Experiment


TFT Device Physics

Concept of band diagram

Effects of defect states

Different regimes of operation


Band DiagramWhat is a band diagram?

Ec/Ev distribution in space

What is a band diagram for?potential distribution

carriers distribution

carrier concentrations

Low Vgnon-degenerate: n = NcExp{-[Ec-Ef(Vg)]/kT}

High Vgdegenerate: n = Ci Vg/q

External bias Vg

Ef_s

Ef_m

Ec-Efat interface

Ec_s

Ec_i

Ev_s

Vacuum level

Ev_i


Band Diagram of a TFT

Ec at interfaceEf

Vg

Vg

EfEc

Ec at interface

Ev at interface


Device Operation (w/o defect states)

Vg induced carrier band bendingfree e-


Device Operation (with fast states)

Vg induced carrier band bendingfree e-

trapped e-


Different Regimes of Operation

-14

-12

-10

-8

-6

-4

Log

[Dra

in C

urre

nt (

Am

ps)]

-30 -20 -10 0 10 20 30 Gate Voltage [Volts]

Vds = 10V

Leakage Above-ThresholdSub-Threshold

- 1 0 - 5 0 5 1 0 1 5 2 01 0

-1 2

1 0-1 1

1 0-1 0

1 0-9

1 0-8

1 0 -7

1 0-6

1 0-5

1 0 -4

1 0-3

1 0-2

V d = 1 0 V

V d = 0 .1 V

s a tu r a t io n

s a tu r a t io n l in e a r

l in e a r

S S

Id (

A)

V g (V )

non-degenerate: n = NcExp{-[Ec-Ef(Vg)]/kT}(Exponential dependence)

degenerate: n = Ci Vg/q(Linear dependence)

Linear region : Vds<Vgs-Vt


a-Si TFT Example

Topmost curve: Vgs = 20 V; Step: -2.5 V

0 10 20 30

Drain-source voltage [V]

0u

2u

4u

6u

8u

10u

Dra

in c

urr

ent

[A

]

Vds = 0.1 V

Vds = 10 V

-20 -10 0 10 20


10 -15

10 -14

10-13

10 -12

10 -11

10 -10

10 -9

10-8

10-7

10 -6

10 -5

10-4

Dra

in c

urr

ent

[A

]

W / L = 150µm / 7.5µm


Transfer (VDS=0.1V, 5V, 10V) and drain current characteristic (VGS=2V, 4V, 6V, 8V, 10V) of n channel polysilicon TFT with W/L = 50µm/6µm.

Poly-Si TFT Example

0.0

0.2

0.4

0.6

0.8

1.0

Dra

in C

urre

nt [

mA

]

0 2 4 6 8 10 Vds [V]

-12.0

-10.0

-8.0

-6.0

-4.0

-2.0

log(

Id

[A]

)

-10 -5 0 5 10 Vgs [V]


Testing for TFTs

Probe station

Main Control PC for test system

Microscope

DUTSource measure units

– Tester – Prober– Controller

Device test for parameter extraction


Testing for TFTs

ProberChuck

Probe tip

Tip holder

Cable

Manipulator

Microscope

Dark box



Testing for TFTs

ControllerInstrument control interface (GPIB)

Data storage

Data analysis

Data fitting

TesterControl bus

Source

Meter

SMU

CV

Cable

Agilent Technologies

4156C

Keithley Instrument

4200-SCS



OutlinesIntroductionTFT Device StructureGeneral TFT ProcessTFT Device PhysicsTFT Experiment

Clean/Wet EtchThermal EvaporationPECVDPhotolithographyI-V MeasurementMasks


Clean Bench (Wet Bench)


Standard RCA Clean


Wet Etch (濕蝕刻)原理

(a)

(b)

(c) 以濕式法進行薄膜蝕刻時，蝕刻溶液（即反應物）與薄膜所進行的反應機制。(a)蝕刻前

(b)濕蝕刻-等向性蝕刻(isotropic etching )

(c)乾蝕刻-非等向性蝕刻(anisotropic

etching )


應用-Al Wet Etching

現今鋁金屬蝕刻一般採用濕式蝕刻，所用之蝕刻液由不同比例的磷

酸、硝酸、醋酸和水所組成，其蝕刻機制乃是利用硝酸與鋁反應形成

氧化鋁，再與磷酸反應形成水溶性的磷酸鋁，醋酸在此作為緩衝液，

其功用主要防止硝酸在水中解離而改變蝕刻率。其中，硝酸雖只佔蝕

刻液1~3%，但其肩負將鋁氧化的工作，因其揮發性高而造成鋁蝕刻液

不穩定主因。

蝕刻液成份=20% acetic acid+77% phosphoric acid+3% nitric

acid(加熱40~50℃)

註:鋁蝕刻製程中難以完全去除鋁合金，如鋁矽銅合金(AlSiCu)


應用-a-Si wet etching

一般選用Secco etching solution蝕刻非晶矽及矽化

物。(SiO2只用HF加水即可蝕刻)

蝕刻液內容為硝酸、氫氟酸加水調配而成。

HNO3:HF:H2O = 4:1:50

蝕刻過程可加入BHF當Buffer溶液，其組成為

NH4F=NH3+HF


應用-PR Strip

通常光阻去除劑(strippers)分成三類：通用型、正

光阻專用型、負光阻專用型。

將丙酮倒入結晶皿內，並置入待去除光阻之試片，用

玻棒加以攪拌，可明顯看到光阻剝離，亦可將結晶皿

置入超音波震盪器中以加速光阻的去除。


化學清洗槽使用注意事項

1.所有化學藥品取用應在化學清洗槽上，使用後應立

即將瓶子蓋緊，以避免有毒氣體外洩；化學清洗槽

使用後須擦拭乾靜並保持乾燥。

2.除酸、鹼與純水外，其餘物品不可倒入化學清洗

槽；酸鹼倒入化學清洗槽前須先用大量清水稀釋。

3.切忌碰觸不明液體，因為那可能是HF或其他強酸、

強鹼。


Thermal Evaporation System


設備原理

Thermal Evaporation System操作程序

1. 破真空

2. 置入試片

3. 抽真空

4. 鍍金屬


Chamber


Thermal evaporation in vacuum

In the evaporation deposition technique, the material is heated until fusion by means of an electrical current passing through a filament or metal plate where the material is deposited (Joule effect). The evaporated material is then condensed on the substrate. Other ways of heating are used, such as a RF coil surrounding a graphite or BN crucible, where the material to be evaporated is fused. The assemby of the technique is simple and results appropriate for depositing metals and some compounds whith low fusion temperature (Al, Ag, Au, SiO, etc.). Typical metals used as heating resistance are tantalus (Ta), Molibdene (Mo) and wolfram (W), with vapor pressure praticallyzero at the evaporation temperature (Tevap = 1000-2000 °C). When a helicoidal filament surrounds the material it is convenient that the evaporant material wets the metal.


Plasma-Enhanced Chemical Vapor Deposition (PECVD)

PECVD 1PECVD 2


PECVD 設備原理

PECVD系統使用射頻（radio-frequency，簡

稱RF）電源供應器提供RF電磁波(13.56MHZ)

產生電漿，而腔體內部是以上下兩片極板所構

成，此兩片極板通常為鋁製電極，晶片則是放

置於下方電極基板上。

兩個電極間外加一個射頻(RF)電壓時，兩極

間會有輝光放電現象。製程氣體則由上方極板

通入進入兩極板間的輝光放電區域，而製程所

產生之癈氣則由抽氣幫浦抽至癈氣處理系統。


• 反應氣體(Gas Source)： SiH4(Silane) 、H2

(n+a-Si反應時則加入PH3氣體)

SiH4(g) + H 2(g) a-Si:H

• a-Si 製程條件: (Balzers )

壓力 1 torr

溫度 200 °C

功率 5 W

PECVD應用：非晶矽膜(a-Si)

用途


PECVD應用：氮化矽(Silicon Nitride) SiNx

• 反應氣體(Gas Source)： SiH4(Silane) 、NH3、N2 、H2

SiH4(g) + H 2(g) a-Si:H

• SiNx 製程條件:(Balzers )

壓力 1 torr

溫度200 °C

功率10 W

用途


Photolithography設備簡介

接觸式光罩對準曝光機(Mask Aligner) • 對各元件之對準曝光


Photolithography設備簡介光阻塗佈機(Photo Resist Spinner) • 上光阻

• (兩段轉速、兩段時間控制)

加熱板(Hot plate)• 軟烤(曝光前烘烤)


Photolithography設備簡介

烤箱(Oven)• 矽晶片或其它半導體晶

片，塗光阻前處理，烘乾

光學顯微鏡(Optical Microscope)• 觀察顯影效果


Photolithography操作程序

清洗(丙酮、甲醇、去離子水)

去水烘烤

光阻覆蓋

軟烤

曝光

硬烤

顯影


I-V Measurement設備應用

金屬與半導體界面(Metal-Semiconductor Contacts)

蕭特基元件(Schottky diode)

歐姆接觸(Ohmic contact)

電晶體元件(MOSFET, TFT…)

光電元件-太陽能電池元件(Solar cell)


應用：電晶體元件(MOSFET, TFT…)


操作程序

試片固定

1.將樣品置放在substrate holder上

2.接上抽氣管,打開馬達開關,讓試片

可以被吸住固定.


操作程序

探針固定

1.將探針的訊號線接到黑箱璧上的接頭

2.將探針移到試片元件上方

3.旋轉probe station上方選鈕,使得探針緩緩下降到試片上方的金屬面上,仔細確認探針和金屬面有所接觸完成.


操作程序電性量測1.將電腦與KEITHELY量測儀接線接上

2.將KEITHELY量測儀接線接到黑箱璧上

3.開啟電腦ICS軟體及KEITHELY量測儀電源

4.選取instrument中的select instrument

5.點選k12361,再按connect,再按config,在新開發中按下Poll及確定,等待數秒後再按ok,回到原視窗案ok.


操作程序

ICS軟體設定

1.選取measure中的Edit setup,按下NEW,輸入名稱按ok.

2.再按Device,選取要量測元件之種類,按ok

3.再按下Source Unit,再新視窗點選各儀器代號再點要連接

元件之端點,則元件端點會小icon,按此icon可進入設定參

數,設定好後按Done.


Masks

Layer 1 Gate (Al)

Layer 2 a-Si (PECVD)

Layer 3 S/D (Al)

Layer 4 Contact hole (Wet Etch)

Layer 5 Etch Stop (SiNx)


Layer 1 Gate (Al)


W L5 5


Alignment Mark






Layer 3 S/D (Al)



Layer 4 Contact hole (Wet Etch)



All Masks




90°


Vernier

Mask 10-5 +5

每個bar皆10um寬每個bar間距10um寬

20um 30um

Mask 20-5 +5

每個bar皆10um寬

20um 30um

每個bar間距10.5um寬

-10

-10

+10

+10

Mask 1

Mask 2

以上畫好,再複製整套並旋轉90度,兩套分別標明X , Y(用layer 1標明)


MemoMemo

Documents

Lab in Semiconductor Devices - 中興大學教職員工網頁web.nchu.edu.tw/pweb/users/fansen_wang/lesson/2970.pdf · 2007/9/13 Lab in Semiconductor Devices / NCHE EE / Prof. F