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2006 Microchip Technology Incorporated. All Rights Reserved. Slide 1201ASP

201ASPMid-Range Family PIC16F887Peripheral Configuration and

Assembly Programming


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Objectives

At the end of this class you will:

Understand the basic PICmicro peripherals and

their associated registers

Have HANDS ON experience initializing Mid-

Range peripherals Be able to implement peripherals not covered

here

Understand interrupts and polling

Write your own application code from scratch


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To get the most from this Class

Ideallyyou should be familiar with the

following:

Assembler programming

Basic Mid-Range family Instruction set

Data and Program memory organization

MPLAB Integrated Development Environment

Microchip ICD2 debugger


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201ASP Agenda

Briefreview of Mid-Range Architecture, Instruction

Set and MCHP Tools Interrupts on the Mid-Range PICmicro

Basic Interrupts Lab

Peripheral discussion:

Input/Output Ports Timers

Timer0

Timer1

Timer1 Lab Timer2

Timer2 Lab


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201ASP Agenda

Enhanced Capture / Compare/ PWM Module

(ECCP)

PWM and Output Compare Labs

Analog Comparator

Analog to Digital Converters (ADC)ADC Lab

Enhanced Universal Asynchronous/Synchronous

Receiver/Transmitter (EUSART) I2C and SPI (Master Synchronous Serial Port)

Multiple Interrupt Lab

Wrap-Up and additional questions


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7/1752006 Microchip Technology Incorporated. All Rights Reserved. Slide 7201ASP

Mid-Range PIC Block Diagram

ADC

TIMER0

MUX

ALU

EUSART

MSSP

PERIPHERALS

WORKINGREGISTER

STATUS REGISTERPages ofProgramMemory

Banks of Data Memory

INSTRUCTION REGISTER

8-bit value from instruction

14-bits

PROGRAM COUNTER



Program Memory

Maximum 8K words:

(8K x 14-bits/word)/1 byte= 14Kbytes of memory

Reset Vector at 0000h

PC will go to this addressupon any reset

Interrupt Vector at 0004h PC will go to this address

upon any Interrupt

Reset Vector

Interrupt Vector

Page 0

Page 1

Page 2

Page 3

0000h

0004h

0005h07FFh

0800h0FFFh

1000h17FFh

1800h1FFFh



Program Counter (PC) and Stack

13-bit PC

PCL ALU result (8-bits) orOPCODE(11-bits)

PCH Paging bits Updated from PCLATH

Specifies page in programmemory

8 Level Deep Stack Stores the contents of the

PC PUSHES

CALL/Interrupt

POPS RETURN, RETFIE,RETLW

PCLATH

PCH PCL

Stack Level 1

Stack Level 8

Program Memory

PC

CALL, RETURN,RETFIE, RETLW



Data Memory Map

128Bytes

Shared Shared Shared

Bank 0 Bank1 Bank2 Bank3

000h

01Fh

020h

07Fh

080h

09Fh

0A0h

0FFh

100h

110h

17Fh

180h

190h

1FFh

0EFh 16Fh 1EFh

10Fh 18FhSpecial

Function

Registers

SFR SFR

General

Purpose

Registers

General

Purpose

Registers

Special

Function

Registers

General

Purpose

Registers

General

Purpose

Registers



Special Function Registers (SFRs )

06hPORTB

PORTC 07h

PORTD 08h

PORTE 09h

PCLATH 0Ah

INTCON 0Bh

PIR1 0Ch

PIR2 0Dh

86hTRISB

TRISC 87h

TRISD 88h

TRISE 89h

PCLATH 8Ah

INTCON 8Bh

PIE1 8Ch

PIE2 8Dh

Bank0 Bank1

Register File Concept

Accessed like anyother register

Some registers carryacross all banks(PCLATH, INTCON, etc.)


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Instruction Set Overview

35 single word instructions

All are single cycle except for program branches

Three categories of operations:

BYTE-ORIENTED BIT-ORIENTED

LITERAL and CONTROL ORIENTED

All on one slide!!!



PICmicro DevelopmentTools


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ICD-2 (In Circuit Debugger)

MPLAB ICD 2 is a low cost, real-time

debugger and programmer. It offers thefollowing features.

Real time background debugging

Reading/Writing memory space and EEDATAareas of target microcontroller

Programs configuration bits

Erase of program memoryspace with verification



APP001 Board

PIC16F887

PORTD LED 2 X 16 LCD Module

RS-232

LCD

Bright

A/D VRMAX232.

DC 9V

Input

Button

16MHz

Crystal

Reset

Button

ICD2

Connecter

J6

(RS-232)

J2

(32768Hz)

J9(LED)

I2C EEPROM

24LCxx

SPI EEPROM

25LCxxx

CAN & RS-485



Interrupts



Often we would like the processor to

perform a task if a specific event occurs

Two methods to check if this event hasoccurred:

Polling: Continuously check for event at various points in the code

Interrupts: INTERRUPTS normal code execution only when event

occurs

Polling and Interrupts



Polling

bsf PORTA,1 ;Set bit 1 of

;PORTA

btfss INTCON, T0IF ;Check Timer0;interrupt flag in;INTCON and

;skip the next;instruction if it;is set

goto $-1 ;Go back to

;previous;instruction

bcf PORTA,1 ;Clear bit 0 of;PORTA

RA = 1

T0IF = 1??

RA = 0

YES

NO



Reset code 000hgoto Start

;=========================int_vector code 004h

retfie ;return from;interrupt

;=========================

main_prog code

Start ;start label for main code

end

Interrupts

Mainprogram

execution

no interrupt

Execute ISR at

address 004h

interrupt flagset

retfie

instruction

Interrupt ServiceRoutine (ISR)

Main programcode



Enabling Interrupts

Processor must be told that interrupts will

be used in the code A number of registers with enable bits are

used:

Interrupt Control Register (INTCON) Peripheral Interrupt Enable Register 1 (PIE1)

Peripheral Interrupt Enable Register 2 (PIE2)


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Enabling a Core Interrupt

PROGRAM COUNTER

INTCON

GIE

INT Interrupt!!

0

goto $ address

goto $ address STACK

0 0 0 0 0 0 011INTE INTF

1

Int_vect CODE 004h

;clear INTF to enable;further interruptsbcf INTCON, INTF

retfie

Main CODEStart

; initialize INTCONclrf INTCON

;enable an external;interrupt on the INT pinbsf INTCON, INTE

;enable global interruptsbsf INTCON, GIE

goto $ ; sit here and loop forever


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Peripheral Interrupts

Two registers to enable interrupts on specific

peripherals: Peripheral Interrupt Enable Register 1 (PIE1)

Peripheral Interrupt Enable Register 2 (PIE2)

Two registers containing the specific peripheralinterrupt flag:

Peripheral Interrupt Request Register 1 (PIR1)

Flags for peripheral interrupts enabled in PIE1

Peripheral Interrupt Request Register 2 (PIR2) Flags for peripheral interrupts enabled in PIE2

*Flags will set even ifinterrupts are not enabled


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PIE1 and PIR1 Registers*

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

PIE1 Register (Interrupt Enables)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

PIR1 Register (Interrupt Flags)

ADIE ADIF ADC conversion complete

RCIE RCIF EUSART receive buffer is full

TXIE TXIF EUSART transmit buffer is full

SSPIE SSPIF I2

C or SPI InterruptCCP1IE CCP1IF Timer1 register capture or compare match

TMR2IE TMR2IF Timer2 value and PR2 period value match

TMR1IE TMR1IF Timer1 register has overflowed

Enable Flag Condition

*Check individual datasheets


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Enabling a Peripheral Interrupt

PROGRAM COUNTER

1 1

INTCON

GIE PEIE

PIE1

PIR1TMR1IE

TMR1IF

1

0

Timer1 Overflow!

1

0

goto $ address

goto $ address

Int_vect CODE 004h

banksel PIR1bcf PIR1, TMR1IF

retfie

STACK

Main CODEStart

banksel PIR1bcf PIR1, TMR1IFbanksel PIE1bsf PIE, TMR1E

bsf INTCON, PEIEbsf INTCON, GIE

goto $ ; sit here and loop forever


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Interrupt Logic

TMR0IETMR0IF

RBIERBIF

TMR2IETMR2IF

ADIEADIF

PEIE

GIE

Interrupt

Other peripherals


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Context Saving

During an interrupt:

Only the PC value is saved (on the stack)

Registers augmented in the ISR arepermanently changed

Key registers the user may want saved: Working register

Status

PCLath User defined registers


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Interrupt Priority

Mid-Range PIC microcontrollers treat all

Interrupts with the same priority

The user must do the following:

Determine source of interrupt

Determine the order in which the interruptsare serviced.


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Interrupt Priority Example

INT_VECTOR CODE 0x004 ; interrupt vector location

movwf temp_w ; save WREGmovf STATUS,wmovwf temp_status ; save STATUS register

btfsc INTCON,RBIF ; PORTB change?

call PORTB_ISRbtfsc PIR1,TMR2IF ; Timer 2 interrupt ?call Timer2_ISRbtfsc PIR2,TMR1IF ; Timer 1 interrupt ?call Timer2 ISR

Restore_context:movf temp_status,wmovwf STATUS ; restore STATUS reg.movf temp_w,w ; restore WREGretfie ; return from interrupt


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Basic InterruptHands on Lab

B i I


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Basic Interrupts

The objective of this is to:

Learn how to set up the System Oscillator

Learn how to set up and enable an internalinterrupt on the Mid-Range PIC

Become more familiar with the MPLAB IDE, theAPP001Board and the ICD2 Building a Project

Using the ICD to set a break point


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PIC16F887 Oscillator Diagram

Oscillator requests 4Mhz with Internal RC

O


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Basic Interrupt Lab Overview

Enable Interrupts

Initial PORTBfor S3 input

Clear Variables

No OperationNOP

Calldebounce

delay function

IncrementCount variable

Clear IF

retfie

Interrupt Vector Main Program

L b S ifi ( t )


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Lab Specifics (cont.)

Code is located in C:\RTC\201_ASP\Lab1-INT

Use MPLAB and the ICD to program the PIC16F887then run the program to view the LEDs increment.

Wh t d t k


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What you need to know

The function of the INTCON register bits

A subroutine called debounce is given that

delays processing and prevents the

mechanical bouncing of SW2 to generate

multiple interrupts ( more on this in later labs)

How to setup break points and a Watch

Window in MPLAB

B i I t t L b S l ti


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Basic Interrupt Lab Solution

bcf INTCON,INTF

bsf INTCON,INTE ; ### Enable INT0 Interrupt bsf INTCON,GIE ; ### Enable Global Interrupt

;

Loop

nop

goto Loop

:

:

Int_Service_Routine

call Debounce ; Delay until switch stops bouncing incf PORTD,F ; increments number of time button has

;been pushed

bcf INTCON,INTF ; ### clears the INT0 Interrupt Flag

retfie


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Peripherals


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Di it l I/O O i


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Digital I/O Overview

Up to 35 bi-directional I/O pins, some

multiplexed with peripheral functions

High drive capability

Direct, single cycle bit manipulation

Most I/Os have ESD

Multiplexed I/O pins default to ANALOGinputs on startup (high impedance state)

PORT d TRIS R i t


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PORTx and TRISx Registers

Every PORT (A, B, C, D, E) will have a

corresponding direction register TRISx

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

PORTB Register

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

PORTB Tri-State Register TRISB

1 = corresponding PORTB pin is input0 = corresponding PORTB pin is output

DataConfigures Data

Direction

ANSEL and ANSELH Registers


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ANSEL and ANSELH Registers

Two registers used to configure I/O to digital

I/Os multiplexed with analog peripherals default toanalog on start-up

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

ANS13 ANS12 ANS11 ANS10 ANS9 ANS8

Analog Select Register (ANSEL)

Analog Select High Register(ANSELH)

1 = Pin assigned as analog input

0 = Digital I/O

Initializing Digital I/O


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Initializing Digital I/O

Example:

Initializing PORTB for RB as inputs andRB as outputs

;------------configure PORTB for digital ----------------------------------------banksel PORTB ;Go to bank containing PORTB

;registerclrf PORTB ;Clear PORTBbanksel ANSELH ;Go to bank containing ANSELH

;registerclrf ANSELH ;Set as all digitalclrf ANSEL

;-----------Set up direction of each PORTB pin-------------------------------banksel TRISB ;Go to bank containing TRISB

;registermovlw b11110000 ;Value to set TRISB high

;and TRISB low move into;W register

movwf TRISB ;Move value in W into TRISB

PORTB Interrupt On Change


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PORTB Interrupt-On-Change

On PIC16F887 all PORTB pins have Interrupt-on-

Change and Weak Pull-Up options

RB3

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

Weak Pull-Up PORTB Register (WPUB)

1 = Pull-up enabled0 = Pull-up disabled

1IOCB7 IOCB6 IOCB5 IOCB4 ICOB3 IOCB2 IOCB1 IOCB0

RB4

Interrupt-On-Change PORTB Register (IOCB)

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

GIE PEIE TOIE INTE RBIE TOIF INTF RBIF

Interrupt Control Register (INTCON)

RBIF

1

HIGH

LOW

*PORTB must first be read/written and then RBIF can be cleared

in software


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Timers

Timers


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Timers are used for many functions:

timing reference to generate an event

count the number of events

waveform generation etc...

PIC16F887 has 3 timers

Timer0

Timer1

Timer2

Timers

PIC16F887 Timer Comparison


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PIC16F887 Timer Comparison

TIMER0 TIMER1 TIMER2SIZE OF

REGISTER8-bits (TMR0) 16-bits

(TMR1H:TMR1L)8-bits (TMR2)

CLOCK SOURCE

(Internal)

Fosc/4 Fosc/4 Fosc/4

CLOCK SOURCE

(External )

T0CKI pin T1CKI pin orTimer 1 oscillator

(T1OSC)

None

CLOCK SCALINGAVAILABLE

(Resolution)

Prescaler 8-bits(1:21:256)

Prescaler 3-bits(1,2,4,8)

Prescaler(1:1,1:4,1:8)

Postscaler(1:11:16)

INTERRUPTEVENT and FLAG

LOCATION

On overflowFFh00h

(T0IF in INTCON)

On overflowFFFFh0000h

(TMR1F in PIR1)

TMR2 matches PR2

(TMR2F in PIR2)

CAN WAKE PICFROM SLEEP?

NO YES NO

Timer 0 Block Diagram


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scaled clock TMR0T0CKIpin

Fosc/4

prescalerWatchdog Timer

synchronize

WDT out

OPTION register

RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0

TMR0 Clock Source Select

1 = TOCK1, 0 = Fosc/4

Source Edge Select1 = increment TMR0 on high-to-low transition

0 = increment TMR0 on low-to-high transition

Prescaler Assignment1= prescaler assigned to WDT0= prescaler assigned to Timer 0

Prescaler Rate Select Bits

PS2 PS1 PS0

TMR0

RATE

0 0 0 1:2

0 0 1 1:4

0 1 0 1:8

0 1 1 1:16

1 0 0 1:32

1 0 1 1:64

1 1 0 1:128

1 1 1 1:256

8

DATA BUS



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TOIF


scaled clock TMR0T0CKIpin

Fosc/4

prescalerWatchdog Timer

synchronize

WDT out

8

DATA BUS

Timer 0 is readable or writeable from the data bus

Writes will inhibit increment for 2 x TCY

TOIF in INTCON register is set with Timer 0 roll-overFFh 00h

INTCON register

If TOCK1 is used as the clock source, prescaler is first

sampled and then synchronized with the internal clock

Timer0 Initialization (Internal Clock Source)


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TMR0

0 0 0 0 0 0 0 0

INTCON

0 0 0 0 0 0 0 0

OPTION_REG

0 0 0 0 0 0 1 1

T0IF

This interrupt flag will set on Timer0overflow even if all interrupts are

disabled

PSAPS

TOCS

SELECTSINTERNAL

CLOCK

ASSIGNSPRESCALER TO

TIMER0

SELECTS1:16

TIMER0 RATE

T0IF = 0?

NO

YES

CONTINUE

1

;Make sure the TMR0 register is clearbanksel TMR0clrf TMR0

; Clear T0IFbcf INTCON,T0IF

;Setup the following in the OPTION_REG;Timer0 increment from internal clock;with a prescaler of 1:16

banksel OPTION_REGmovlw b00000011movwf OPTION_REG

;The TMR0 interrupt is disabled, do polling;on the T0IF overflow bit

btfss INTCON, T0IFgoto $-1

Timer1 Block Diagram


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T1CKIpin

T1OSCT1OS0

T1OSI

prescalersynchronize

Timer1 Control Register (T1CON)

Clock Source Select1 = External (T1CKI on rising edge)0 = Internal FOSC/4

LP Oscillator Enable1 = T1OSC selected0 = T1CKI can be used

Fosc/4

T1CKPS1 T1CKPS0 scale

1 1 1:8

1 0 1:4

0 1 1:2

0 0 1:1

Timer1 On1 = Enables Timer1

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

TMR1H TMR1L

Enable

TMR1ON



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TMR1GE

Timer1 External Clock Input Synchronization1 = do not synchronize external clock input0 = synchronize external clock input


T1CKIpin

T1OSCT1OS0

T1OSI

prescalersynchronize

T1G


Fosc/4

TMR1H TMR1L

Timer1 Gate invert1 =Timer1 counts when gate is HIGH0 = Timer1 counts when gate is LOW

Timer1 Gate Enable1 = Timer1 is on if gate is not active0 = Timer1 is on

COMPARATOR 2output

If TMR1ON is 0, ignore TMR1GEbit

Enable

TMR1ON

T1GINV

Determined byT1GSS in CM2CON1

(comparator 2 controlregister 1)

Will Timer1 time Highor Low transitions

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Timer1 Interrupt


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Main Code

Start

;Start by clearing the Timer1 interrupt flag

banksel PIR1

bcf PIR1, TMR1IF

;Enable Timer1 interrupt

banksel PIE1

bsf PIE1, TMR1IE

;Enable Global and Peripheral Interrupts

bsf INTCON, GIE

bsf INTCON, PEIE

;

Timer1 Interrupt

INTCON

PIE1

1

GIE PEIE

TMR1IE

1

1

PIR1

TMR1IF

0

TMR1H TMR1L

1 1 1 1 1 1 0 11 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1

OVERFLOW



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Timer1 Initialization (Internal Clock Source)TMR1H

0 0 0 0 0 0 0 0

INTCON

T1CON

T1CKPS

TMR1L

0 0 0 0 0 0 0 0

PIR1

TMR1IFPIE1

TMR1IE

0 00 00000

0000000

000

0

00000

000000 11

T1SYNC

Scale input

clock to 1:8

Selectinternal

clock (Fosc/4)

TMR1CS

Synchronizeexternal clock

output

TMR1ON

1

TMR1H:TMR1L INCREMENTING

1

OVERFLOW!!

;Make sure the TMR1 registers are clearbanksel TMR1Hclrf TMR1Hclrf TMR1L

;Make sure the TMR1IF flag in PIR1; is clearedbanksel PIR1bcf PIR1,TMRIF

;Setup T1CON register for internal clock with;1:8 prescaler, Timer1 is stopped and T1 osc;is disabledmovlw b00110000movwf T1CON

;Start Timer1 incrementingbsf T1CON, TMR1ON

;The TMR1 interrupt is disabled, do polling;on the TMR1IF overflow bitbtfss PIR1, TMR1IFgoto $-1


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Timer 1 Lab(Lab2)

Lab2 Timer 1


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Lab2 Timer 1

Objective of this lab is to become familiar withthe operation of Timer1

AND

To gain experience enabling Peripheral

Interrupts

Lab2 Overview


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Lab2 Overview

Initialize PORTB

Initialize Timer1 clocksource and pre-scaler:

Timer1 interruptsevery 100,000 Instruction cycles

Enable Timer1, Globaland Peripheral Interrupts

NOP Main Loop

MAIN ProgramInterrupt Vector

Save Context

Clear IF

Reload Timer1

Toggle LED 0

Toggle LED 3

Restore Context

Retfie

5th Int. ?NO

YES

Lab2 Specifics


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Lab2 Specifics

The code for the lab is in

C:\RTC\201_ASP\Lab2-TMR1

Within lab2.asm complete the following

Set Timer 1 clock source to Fosc/4

Set Timer 1 pre-scaler to 2

Load Timer 1 with 0x3CB0 (65,356 50,000)

Start Timer 1

Enable Timer 1, Global and Peripheral Interrupts



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Register Operations of INTCON, T1CON,TMR1H, TMR1L and PIE1

With a value of 0x3CB0 and a pre-scaler of 2,Timer1 will overflow every 100,000 cycles

The interrupt vector code to toggle the LEDshas been provided

b2 S l i


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Lab2 Solution;; **********************************************************************************; Set code to Select clock source, Set pre-scaler to 2, load hex 3CB0 into Timer1; and turn on Timer1; **********************************************************************************

movlw (.65536-.50000) / .256 ; initialize TMR1L and TMR1Hmovwf TMR1Hmovlw (.65536-.50000) % .256movwf TMR1L

bsf T1CON,T1CKPS0 ; set pre-scaler to 2bcf T1CON,TMR1CS ; set Clock source to Fosc/4bsf T1CON,TMR1ON ; turn Timer1 on

;;************************************************************************************; Enable Timer1 interrupts, Peripheral Interrupts and Global Interrupts;************************************************************************************

;bsf STATUS,RP0 ; go to bank1bsf PIE1,TMR1IEbsf INTCON,GIEbsf INTCON,PEIEbcf STATUS,RP0 ; return to bank0

Lab2 Questions


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Lab2 Questions

Question: Was Timer 1 still running during the time it

took to service the Interrupt?Answer: Yes

Question: What effect did this have on the value to beplaced to reload TMR1L and TMR1H?

Answer: Everything to be precise the latency of

reloading Timer1 should be considered



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Prescaler1:1, 1:4, 1:16

COMPARATOR

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Postscaler

1:1

1:16

Fosc/4

Timer2 ON1 = Timer2 enabled

T2CKPS1 T2CKPS2 Scale

0 0 1:1

0 1 1:4

1 X 1:16

TMR2

TMR2

OUTPUT

PR2

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 SCALE

0 0 0 0 1:1

0 0 0 1 1:2

0 0 1 0 1:3

0 0 1 1 1:4

0 1 0 0 1:5

0 1 0 1 1:6

0 1 1 0 1:7

0 1 1 1 1:8

1 0 0 0 1:9

1 0 0 1 1:10

1 0 1 0 1:11

1 0 1 1 1:12

1 1 0 0 1:13

1 1 0 1 1:14

1 1 1 0 1:15

1 1 1 1 1:16




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Prescaler1:1, 1:4, 1:16

COMPARATOR

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Postscaler

1:1

1:16

1 1 1 1 1 0 0 0

Fosc/4

TMR2

OUTPUT

1 1 1 1 0 1 1 01 1 1 1 1 0 0 01 1 1 1 0 1 1 11 1 1 1 0 1 0 1

1

PIR1

TMR2IFTimer2 Control Register (T2CON)

TMR2

PR2

Timer2 Initialization


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TMR2

0 0 0 0 0 0 0 0

T2CON

PIR1

TMR2IF

PIE1

TMR2IE

0

0

100 00 111

;Disable TMR1 interrupts in the PIE1;register that holds the TMR2IE bit.;Make sure the TMR2IF flag in PIR1 is clearedbanksel PIE1

bcf PIE1, TMR2IEbanksel PIR1bcf PIR1, TMR2IF;Setup T2CON register for:; Postscaler = 1:15; Prescaler = 1:16;Timer2 is offmovlw b01110010

movwf T2CON;Make sure the TMR2 register is clearbanksel TMR2clrf TMR2;Load the PR2 register with a predetermined;valuebanksel PR2

movlw b10000000movwf PR2;Start Timer2 incrementingbanksel T2CONbsf T2CON, TMR2ON;The TMR2 interrupt is disabled, do polling;on the TMR2IF flagbtfss PIR1, TMR2IF

goto $-1

1

TOUTPS

TMR2ON

T2CKPS

Postscalerset to 1:15 Prescalerset to 1:16

Timer2is OFF

1

TMR2 INCREMENTINGTMR2 = PR2

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 SCALE

0 0 0 0 1:1

0 0 0 1 1:2

0 0 1 0 1:3

0 0 1 1 1:4

0 1 0 0 1:5

0 1 0 1 1:6

0 1 1 0 1:7

0 1 1 1 1:8

1 0 0 0 1:9

1 0 0 1 1:10

1 0 1 0 1:11

1 0 1 1 1:12

1 1 0 0 1:13

1 1 0 1 1:14

1 1 1 0 1:15

1 1 1 1 1:16

PR2

0 0 0 0 0 0 01


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Timer 2 Lab(Lab3)

Timer 2 Lab


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The Goal of Lab3 is to become familiar with the

following : Timer2 Clock Source

Pre scaler value

Post scaler value

Turning on Timer2

Setting all the enable bits needed for Timer2 to

successfully generate an interrupt

Lab3 Overview


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Main Program

Initialize PORT B

Set up Timer2PR2, Pre scaler,

Post Scaler,clock sourcefor 10mS

Enable interrupts

NOP

Interrupt Vector

Save Context

Increment counter thenumber of times

Timer2 has interrupted

Increase the LED count

Restore context

retfie

Lab3 Specifics


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p

Code for this lab is in

C:\RTC\201_ASP\Lab3-TMR2

Complete the following sections of code

Set Timer 2 pre-scaler to a value of 4 Set Timer 2 post-scaler to a value of 10

Turn Timer 2 on

Configure the GIE, PEIE and Timer 2 Interrupt

Enable bit



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y

Special Function Registers (SFRs) needed forthe lab3 are INTCON , PIE1, PR2 , and

T2CON

With PR2 set to 250, the pre-scaler at 4, and

the post-scaler at 10, Timer 2 will interrupt at

an every 10 ms (about 1/100 second) with a4Mhz oscillator ( Fosc/4 = 1Mhz)

Timer 2 Lab Solution


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;;*************************************************************************; configure Timer2 Prescaler of 4, PR2 of 250 and a postscaler of 13; and turn timer2 on.;*************************************************************************;

banksel 0 ; set bank to 0movlw b01001000 ; set 10 as postscalermovwf T2CON

bsf T2CON,T2CKPS0 ; set prescaler to 4bsf T2CON,TMR2ON ; turn on Timer2

;************************************************************************; Enable Timer2 interrupts, Peripheral Interrupts and Global Interrupts;************************************************************************

;bsf STATUS,RP0 ; go to bank1bsf PIE1,TMR2IEbsf INTCON,GIEbsf INTCON,PEIEbcf STATUS,RP0 ; return to bank0

Lab3 Questions


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Question: Like Timer1 does Timer2 keep runningduring Interrupt latency?

Answer: Yes it does !

Question: Does the user have to account for the freerunning Timer2 in order to ensure a precise interruptperiod?

Answer: No, Interrupt occurs on match notoverflow


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EnhancedCapture/Compare/PWM

Module

ECCP Overview


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Capture Capabilities

Times the duration of an event Compare

Triggers a specific event when a determined amountof time has passed

Pulse Width Modulation (PWM)

creates reconfigurable, steady duty-cycle, squarewave output at defined frequency

Provides enhanced features for various bridgeconnectivity

* Module interfaces with Timers 1 and 2

ECCP MODE Timer Resource

Capture Timer 1

Compare Timer 1PWM Timer 2

ECCP Control Registers


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P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

P1MOutput Configuration Bits

(ii)

Capture/Compare Modes = not used 00

Enhanced PWM = Provides Half-Bridge or Full-Bridge outputSteering Control

DC1BPWM duty cycle 2 LSBs (8 MSBs located in CCPR1L)

*Not used in Capture or Compare modes

CCP1M

ECCP Mode Select Bits (i)

Configure the module for variety of modes including TriggerSpecial Event and edge detection

BIT FUNCTION

CCP2CON is similar to CCP1CON without:i. Compare mode toggle on output pin in the Mode Select Bitsii. Enhanced PWM configuration capabilities (Output Configuration bits)

Enhanced CCP1 Control Register (CCP1CON)

These bits determine the mode of the modulei.e. Use Capture, Compare or PWM mode

CCPxM3 CCPxM2 CCPxM1 CCPxM0 EECP Mode Selected

0 0 0 0 Capture/Compare/PWM off (resets ECCP module)

0 0 0 1 Unused (reserved)

0 0 1 0 Compare mode, toggle output on match

0 0 1 1 Unused (reserved)

0 1 0 0 Capture mode, every falling edge

0 1 0 1 Capture mode, every rising edge

0 1 1 0 Capture mode, every 4th rising edge0 1 1 1 Capture mode, every 16th rising edge

1 0 0 0 Compare mode, set output on match

1 0 0 1 Compare mode, clear output on match

1 0 1 0 Compare mode, generate software interrupt on match

1 0 1 1 Compare mode, trigger special event

1 1 0 0 PWM mode; P1A, P1C active-high; P1B, P1D active-high

1 1 0 1 PWM mode; P1A, P1C active-high; P1B, P1D active-low

1 1 1 0 PWM mode; P1A, P1C active-low; P1B, P1D active-high

1 1 1 1 PWM mode; P1A, P1C active-low; P1B, P1D active-low

Capture Mode


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CCPx

TMR1H TMR1L

CCPRxH CCPRxL

Prescaler

1, 4, 16

Edge Detectand

System Clock (Fosc)


CCPxCON

CCPxIF in PIRx

Single Buffered

CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE

0 1 0 0 Capture every falling edge

0 1 0 1 Capture every rising edge

0 1 1 0 Capture every 4th rising edge

0 1 1 1 Capture every 16th rising edge

TMR1H TMR1L

Capture Initialization


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TMR1H

TMR1ON

CCP1IF

TMR1L0000000 0

0000000 0

PIR1

0

CCP1CON

T1CON

00000 0

1

TIMER1 INCREMENTING!!

00

0

CCPR1H

CCPR1L

11

1

4th Rising EdgeDetected!!

Current Timer1 Value

Current Timer1 Value

;Turn off CCP modulebanksel CCP1CONclrf CCP1CON;Make sure Timer1 is offbcf T1CON, TMR1ON;Clear Timer1 result registersclrf TMR1Hclrf TMR1L;Disable all interrupts for CCPbcf PIR1, CCP1IF

banksel PIE1bcf PIE1, CCP1IE;Set CCP1 pin for inputbsf TRISC, 2;Initialize Capture for every 4th rising edgebanksel CCP1CONmovlw b00000110

movwf CCP1CON;Start Timer1 incrementingbsf T1CON, TMR1ON;Test the CCP1IF flag for capturebtfss PIR1, CCP1IFgoto $-1

Compare Mode


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YESYES CCPx

Special Event Trigger

CCPxIF in PIRx

OUTPUT

LOGIC


TMR1H TMR1L

COMPARATORDoes

TMR1H:TMR1L =

CCPRxH:CCPRxL??

NO

CCPRxH CCPRxL

CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE1 0 0 0 Set output on match (CCPxIF is set)

1 0 0 1 Clear output on match (CCPxIF is set)

1 0 1 0Generate software interrupt on match(CCPxIF is set CCP1 pin unaffected)

1 0 1 1

Trigger special event

(CCPxIF is set, CCP1 resets TMR1 orTMR2 and starts an A/D conversion if

enabled)

Compare Initialization


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TMR1H

TMR1ON

CCP1IF

TMR1L

0000000 0

0000000 0

PIR1

0

CCP1CON

T1CON

00000 0 0

TIMER1 INCREMENTING!!

CCPR1H

CCPR1L

0000000 0

000000 0

0

0

1

1

1

TMR1H:TMR1L = 1000 0000 0000 0000(CCPR1H:CCPR1L Value)

1

;Turn off the CCP modulebanksel CCP1CONclrf CCP1CON;Turn off Timer1bcf T1CON, TMR1ON

;Clear Timer1 result registersclrf TMR1Hclrf TMR1L;Disable CCP1 interrupt and make sure;its flag is clearbanksel PIE1bcf PIE1, CCP1IEbanksel PIR1bcf PIR1, CCP1IF;Make CCP1 pin outputbanksel TRISCbcf TRISC, 2;Initialize Compare to set output on matchbanksel CCP1CONmovlw b00001000movwf CCP1CON;Load half of Timer1 full scale value into

;CCPR1H:CCPR1Lbanksel CCPR1Hmovlw b10000000movwf CCPR1Hclrf CCPR1L;Start Timer1 incrementingbsf T1CON, TMR1ON;Test CCP1IF for Timer1 match with CCPRxbtfss PIR1, CCP1IF

goto $-1

PWM Mode


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Generates a Pulse-Width Modulated (PWM)

signal on the CCPx pin Duty cycle, period and resolution

determined by the following registers

PR2 T2CON

CCPRxL

CCPxCON

PWM Block Diagram


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CCPRxL DCxB

CCPxpin

CCPRxH LATCH

TMR2 incrementing

PR2

Latch

CCPxOUTPUT

COMPARATOR

COMPARATORTMR2 = PR2

DUTY CYCLE VALUE

TMR2 = CCPRxH

DOUBLE

BUFFER

R

S

8

8

(1)

Note 1: TMR2 is concatenated with the2-bit FOSC, or 2-bits fromPrescaler to create 10-bit timebase

10

10

10

Setup for PWM Operation


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PR2

10 1 1 1 1 1 1

CCP1CON

0 0 0 0 0PWM Mode

CCP1M duty cycle

LSBsDC1B

CCPR1L

10 0 0 1 1 1 1

TMR2

000 0 0000

111

T2CON

1

TMR2ON

0 0 0 0 0 0 0

Prescaler bitsTOUTPS

Prescaler bitsT2CKPS

;Turn off CCPx pin by setting TRISC bit HIGHbanksel TRISCbsf TRISC, 2

;Clear Timer2

banksel TMR2clrf TMR2

;Set up Period and Duty Cycle using an 8MHz oscillatormovlw b01111111 ;movwf PR2 ;Load a 64uS Period Valuemovlw b00011111 ;movwf CCPR1L ;Load Duty Cycle Value

; (25%) of PWM period

;Configure ECCP module for single PWM; with P1A active HIGH and;LSBs of Duty Cycle are 10movlw b00101100 ;movwf CCP1CON ;ECCP module is configured

;for PWM and Duty Cycle;LSBs loaded

;Turn CCPx pin back onbanksel TRISCbcf TRISC, 2 ;Make CCP1 output

;Timer2 starts when TMR2ON is set beginning PWMmovlw b00000100 ;incrementingmovwf T2CON ;Prescaler and Postscaler

;are both 1:1


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Pulse Width Modulation(PWM) Lab4


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PWM Lab4 Overview


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Load PR2 value

Set up RC2 as output pin

Load CCPR1L for 50% duty cycle

Configure CCP as 8-bit PWM

NOP

Turn on Timer2 w/ 1:1 pre scaler

Main Code

Lab4 Specifics


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Code for the lab is in

C:\RTC\201_ASP\Lab4-PWM

Complete the following sections

Configure PORTC pin 2 ( CCP1) as an output Set CCP in PWM mode

Clear DCB1 and DCB0 (8-bit PWM)

Configure Timer2 with 1:1 pre-scaler


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Lab4 Solution


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;*****************************************************************; Set CCPx as an output;*****************************************************************

bcf TRISC,2 ; set CCP1 pin as output pin;; set duty cycle for 50%;

bcf STATUS,RP0 ; go to bank 0movlw 0x80

movwf CCPR1L ; set duty cycle;*****************************************************************; Put CCP1 module in PWM mode.; Configure CCP to clear DCB1 and DCB0 ( 8-bit PWM);*****************************************************************

movlw 0x0Cmovwf CCP1CON

;*****************************************************************; Configure Timer2 Pre and post scale of 1:1; and turn Timer2 on;*****************************************************************

bsf T2CON,TMR2ON ; turn on Timer2

Lab4 Questions


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Question: Why didnt we have to enable the interrupts

for the PWM to work?

Answer: PWM will run concurrently with the PICmicro

MCU without slowing the processor down


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Output Compare Lab

(Lab5)

Output Compare Lab5


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Goals of the lab are to gain experience with the

following: Setting up the ECCP for Output Compare

Configure the Special Event Flag to reset Timer1

Configure the ECCP to generate an Interrupt on Timer1

overflow Using an Interrupt Vector to modify the interval between

Interrupts

Lab5 Overview


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Save Context

Toggle CCPOutput Pin

Clear IF

Decrement

CCPR1L

Configure CCP asOutput Compare

Initialize PORT C

Initialize Timer1

Turn on timer1

NOP

RETFIE

Interrupt Vector Main Program


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The registers needed to complete this lab are

INTCON, T1CON, CCP1CON.

The Interrupt Vector has been provided

The Value of CCPR1L will rollover from 0 to

0xFF and continue to decrement

CCP Lab5 Solution


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;; Set CCP1COM to Output Compare mode with Special Event Trigger; to clear the Timer 1 register pair on a match

;********************************************************************movlw 0x0Bmovwf CCP1CON ; set value in CCP1CON

;; Configure Timer 1 for Fosc/4 operation. 8:1 Pre-scaler;;*******************************************************************

movlw 0x30

movwf T1CON;

;

; Enable Timer 1 interrupts, Peripheral Interrupts and Global Interrupts;;********************************************************************

bsf PIE1,CCP1IEbsf INTCON,GIEbsf INTCON,PEIE

Lab5 Question


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Question: The PWM did not require an interrupt in

order to work. Do we need an interrupt to operate inoutput compare mode?

Answer:Not necessarily

We did require an interrupt in this Lab because our

task on an Output Compare was not one of the

options


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Comparators

Comparator Overview


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Comparator Module:

Compares analog input voltage to a referenceand outputs a digital result

PIC16F887 has 2 Comparators (C1 and C2)

Vin

Vout

Vref

Comp

Analog Input

(Vin)

Reference Voltage(Vref)

Output

(Vout)


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Simplified Comparator Block Diagram


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C12IN0

C12IN1

C12IN2

C12IN3

CxIN+

CxVref

CxR

CxON

CxOUTpin

CxON CxOUT CxOE CxPOL --- CxR CxCH1 CxCH2

CxOE

CxPOL

comparator

_

+

1 = OUTPUT INVERTED

CxR = 0

CxR = 1

CxCH1 CxCH0 CHANNEL

0 0 C12IN0-

0 1 C12IN1-

1 0 C12IN2-

1 1 C12IN3-

CxOUT

Comparator Module Register CM2CON1


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MC1OUT MC2OUT C1RSEL C2RSEL --- --- T1GSS C2SYNC

MC1OUT Mirror copy of C1OUT bit

C2RSEL1 = CVREF routed to C2VREF input of comparator C2

0 = 0.6V absolute voltage reference is routed to C2VREF

MC2OUT Mirror copy of C2OUT bit

C1RSEL1 = CVREF routed to C1VREF input of comparator C1

0 = 0.6V absolute voltage reference is routed to C1VREF

T1GSS0 = Timer1 will increment on comparator output, 1 = Timer gate will

increment with source on external pin

C2SYNC1 = comparator 2 output is synchronized to falling edge of Timer1

clock

0 = comparator output is asynchronous

BIT FUNCTION

simultaneous readof both comparators


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Comparators and Sleep Mode


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Comparators remain active in Sleep if enabled

prior to Sleep instruction Change on comparator output will wake-up

PICmicro

C1IE/C2IE (PIE2) and PEIE (INTCON) must beenabled

Next instruction following SLEEP instruction isexecuted on wake-up or the ISR (Interrupts enabled)

Enable GIE (INTCON) to perform an ISR instead

Any reset turns comparators off returning allregisters to default

Comparator Voltage Reference


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Voltage Reference Module:

Independent from Comparator operation Provides two 16-level voltage ranges

Output clamped to Vss

Provides a ratio of Vdd Fixed reference (0.6V)

VREF+

VDD

VREN

VREF-

8R R R R R

8R

CVREF

VROE

CVREFTo Comparatorsand ADC Module

4 VR

15

0

VRSS = 1

VRSS = 0

VRSS = 1

VRSS = 0

VRR

EN

Fixed VoltageReference

FVREN

HFINTOSCenable

Sleep

0.6VFixedRef

To Comparatorsand ADC Module

Voltage Reference Control Register(VRCON)


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VREN VROE VRR VRSS VR3 VR2 VR1 VR0

( )

VREN Comparator1 Vref enable, 1 = enabled

VRR

CVref Range Selection

1 = Low Range

0 = High Range

VROE

Comparator2 Vref enable

1 = CVref voltage level is also output on the RA2/AN2/VREF/C2IN+pin

0 = CVref voltage is disconnected from the RA2/AN2/VREF/C2IN+ pin

VRSSRange Select Bit

1 = Comparator reference source, CVrsrc = (Vref+) (Vref-)

0 = Comparator reference source, CVrsrc = Vdd - Vss

VR CVref Value Selection bits

BIT FUNCTION

IfVRR = 1 or Low Range is selected:CVref= (VR/24) x Vdd

or

IfVRR = 0 or High Range is selectedCVref= Vdd/4 + (VR/32) x Vdd


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ADC Registers


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ADCS1 ADCS2 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

The ADC implements two control registers

ADCON0 and ADCON1

ADCON0

ADCSxbits

A/D Conversion Clock Select bits

00 = Fosc/2, 01 = Fosc/8, 10 = Fosc/32,

11 = FRC (Internal Oscillator)

CHSx bits Analog Channel Select bits

GO/DONE 1 = A/D Conversion in progress

0 = A/D Conversion is completed

ADON Enables the ADC module

BIT FUNCTION

ADC Registers


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ADFM --- VCFG1 VCFG0 --- --- --- ---

ADCON1

ADFM Result registers justification bit

1 = Right Justified, 0 = Left Justified

VCFG1 Negative voltage reference

1 = external source on Vref- pin, 0 = Vss

VCFG0 Positive voltage reference

1 = external source on Vref+ pin, 0 = Vdd

BIT FUNCTION

ADC Registers


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Following conversion, ADC result in is placed

into two result registers ADRESH and ADRESL 10-bit ADC result can either be Left or Right

Justified

MSB LSB

MSB LSB

Right Justified

Left Justified

10-bit Result

10-bit Result

A/D Module DiagramVref+

i

CHS3 CHS2 CHS1 CHS0 CHANNEL

0 0 0 0 AN0

ADCS1 ADCS2 Conversion


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ADC

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13Holding Capacitor

Conversionclock scalerFosc

Vref+

Vref-

pin

Vref-

pin

Vdd

Vss

ADRESH ADRESL

ADCON0

0 0 0 0 AN0

0 0 0 1 AN1

0 0 1 0 AN2

0 0 1 1 AN3

0 1 0 0 AN4

0 1 0 1 AN5

0 1 1 0 AN6

0 1 1 1 AN7

1 0 0 0 AN8

1 0 0 1 AN9

1 0 1 0 AN10

1 0 1 1 AN11

1 1 0 0 AN12

1 1 0 1 AN13

Clock

0 0 Fosc/2

0 1 Fosc/8

1 0 Fosc/32

1 1 FRC(dedicated

InternalOscillator)

ADCS1 ADCS2 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

A/D Module DiagramVref+

i

VCFG0 = 1VCFG0 = 0


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ADC

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13Holding Capacitor

Conversionclock scalerFosc

Vref+

pin

Vref-

pin

Vdd

Vss

ADRESH ADRESL

ADFM VCFG1 VCFG0ADCON1

10

VCFG1 = 1VCFG1 = 0

VCFG0 = 1VCFG0 = 0

Timing Considerations for ADC


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When an A-to-D channel is selected time

must be taken for the holding capacitor tocharge

All 10 bit conversion take 11 cycles tocomplete

User must select the appropriate ADCclocking based on the system clockfrequency


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Analog-to-DigitalConversion LAB(Lab6)

Analog-to-Digital Converter lab6


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This Lab will familiarize you with the following:

Setting up the ADC module

Operating a Peripheral from the main program

and not an interrupt vector

Using the value read from one peripheral (ADC)

and using it to drive another Peripheral (ECCP in

PWM mode)

ADC lab6 Overview


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Configure Timer 2

Configure andTurn on ADC

Configure CCP for

PWM

Configure PORT C

Disable interrupts

Main Program

Continued onnext page

Lab6 Overview ( cont.)Continued from


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Output ADC value toLEDs

Start ADC

Put ADC value inPR2 & CCPR1L

ADC done?

Main Loop

NOYES

Previous Page

Lab6 Specifics


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Complete the following sections of code in the

project C:\RTC\201_ASP\Lab6-ADC Configure the ADC to return a left Justified value

into ADRESH

Set Tad to Tosc*8 Turn on ADC unit

Complete the code to start an ADC and wait for

the conversion to finish in the main control loop



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This lab does not do the ADC conversion inan interrupt routine. This lab uses a pollingmethod.

Writing the value of the ADC conversion intoCCPR1L will change the duty cycle of thebuzzer

ADCON1 and ADCON0 special functionregisters are used to complete this lab

ADC Lab6 Solution

********************************************************************************


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;********************************************************************************; Configure ADC , Channel 0, left justified, Tad=8 * Tosc, turn on ADC;********************************************************************************

clrf ADCON0 ; esnure default Channel is set to channel 0bsf ADCON0,ADCS0 ; set Tad = 8 Toscbsf ADCON0,ADON ; turn on ADC unitbsf STATUS,RP0 ; go to bank1movlw 0x0E ; Left Justify and set configurationmovwf ADCON1

;

; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts;

bcf INTCON,PEIEbcf STATUS,RP0 ; return to bank 0

loop;;*********************************************************************************; add three lines of code to start the ADC conversion and wait for the conversion

; to complete;********************************************************************************

bsf ADCON0,GO ; start A-to-D conversion on channel 0btfsc ADCON0,GO ; Is the conversion done?goto $-1 ; No: Check again

ADC Lab6 Question


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Question: Instead of waiting for AD Done bit to be set

in the main program, could we start the ADC fromwithin an interrupt routing?

Answer: YES


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ENHANCED UniversalSynchronous Asynchronous

Receiver Transmitter (EUSART)

EUSART Overview


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Serial I/O communications peripheral Sometimes called Serial Communications Interface or

SCI

Main Functions: Can be synchronous or asynchronous

Can receive and transmit Full-duplex asynchronous transmit and receive

Half-duplex synchronous master and slave

Most common use RS-232 communications to a PC serial port

Needs driver for RS-232 level shifter

Enhanced features allow interface with a LocalInterconnect Network (LIN) bus system

EUSART Registers


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There are several registers used with the

EUSART Baud rate generator registers:

SPBRG and SPBRGH

Transmit status and control (TXSTA) Receive status and control (RCSTA)

Receive and transmit data registers

Transmit data register (TXREG)

Receive data register (RCREG)

TXSTA Register


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Bit Function

CSRC Clock Source Select

1 = Master Mode (clock generated internally from BRG)

0 = Slave Mode (clock from external source)

CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D

TX9 Ninth bit transmission enable

TXEN 1 = Transmit enabled

SYNC EUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode

SENB 1 = Send sync break character bit

0 = Sync break transmission is completedBRGH Baud Rate Select, 1 = High Speed, 0 = Low Speed

TRMT 1 = Transmit Shift Register (TSR) is empty, 0 = TSR is full

Indicates when last bit is shifted out

TX9D Ninth bit of transmit data

RCSTA Register


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Bit Function

SPEN Serial Port Enable

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

RX9 1 = Enable 9-bit data reception, 0 = 8-bit data

SREN Synchronous mode Master, 1 = enable, 0 = disable single receive

CREN Continuous Receive Enable

ADDEN 1 = enables address bit detection (enable interrupt and load the receivebuffer when RSR is set

FERR 1 = framing error occurred (Stop bit not detected)

OERR 1 = Overrun error occurred (FIFO was still full when other data wasloaded)

RX9D Ninth bit of received data

Baud Rate Control Register (BAUDCTL)


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Bit Function

ABDOVF Auto-Baud Detect Overflow bit (Asynchronous mode only)

1 = Auto-baud timer has overflowed

RCIDL Receiver Idle Flag, 1 = Receiver is idle, 0 = Start bit has been received

and the receiver is receiving

SCKP Synchronous Clock Polarity bit

Asynchronous mode: 1 = transmit inverted data to the RB7/TX/CK pin

Synchronous mode: 1 = data is clocked on rising edge of the clock

0 = data is clocked on falling edge of the clock

BRG16 16-bit Baud Rate Generator bit1 = selects 16-bit BRG, 0 = selects 8-bit BRG

WUE Wake-Up Enable bit (Asynchronous Mode only)

ABDEN Auto-Baud Rate Detect Enable bit, 1 = enabled

In SLEEP, detects when 9th bit is set

ABDOVF RCIDL ---- SCKP BRG16 ---- WUE ABDEN

Baud Rate Formulas


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Configuration bitsBRG/EUSART

ModeBaud RateFormula

SYNC(TXSTA)

BRG16(BAUDCTL)

BRGH(TXSTA)

0 0 0 8-bit/Asynchronous Fosc/[64 (n+1)]

0 0 1 8-bit/Asynchronous Fosc/[16 (n+1)]

0 1 0 16-bit/Asynchronous

0 1 1 16-bit/Synchronous Fosc/[4 (n+1)]

1 0 X 8-bit/Synchronous

1 1 X 16-bit/Synchronous

*n = value of SPBRGH:SPBRG register pair

Transmit Block Diagram


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TX9D

SPEN

Baud RateGenerator

TXENMSB LSB

TXREG

Transmit ShiftRegister (TSR)

TX9

DATA BUS

TXIF

InterruptTXIE

Pin Buffer

and Control

TRMT

Set TXIFClear TXIF

Enables SerialPort

Set TRMT bitIndicates shift register is emptyClear TMRT bitTSR has data in itNinth data bit

TX/DTpin

Receive Block Diagram

Enable Serial Port


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Pin Bufferand Control

SPEN

DataRecovery

Baud RateGenerator

STOP START

RX9

Data Bus

RX9DRCIE

Interrupt

RCREG

Receive Shift Register (RSR)

RX/DTpin

FIFO

STOP START

Set RCIF flagClear RCIF flag

RCIF


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EUSART Receive &Transmit LAB(Lab7)

EUSART lab7

Thi L b ill f ili i ith th f ll i


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Setting up the EUSART module with 9600,N,8,1

Operating receiver of EUSART in the interruptservice routine from the RS-232

Main program is waiting the receiving flag forsend out the data through EUSART

USART lab7 Overview

Main Program


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Configure EUSART

Enable RxDinterrupts

Configure LEDs

Configure PORT C

Main Program

RxD_FG=1

NO

RxD_FG=0

Send Data Out


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Lab7 Specifics

C l t th f ll i ti f d i th


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project C:\RTC\201_ASP\Lab7-EUSART Configure the USART for the Asynchronous Mode

9600 bps, None Parity Check, 8-bit Data, 1 Stop bit

4MHz/16/(25+1) =9615 bps , SPBRG = 25

Set PORTC for TxD & RxD

Set PORTD for LEDs output

Turn on USART module

Received a data through RS-232 in interrupt

routine then send out the data through main

program



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Receiver use the interrupt method for the real-time receiving instead of the polling method.

Use a real-time flag to inform main program

Setting the RS-232 communication protocol

Using the Hyper-Terminal on COMx of PC

USART Lab7 Solution;***********************************************************************;**** Initial USART as 9600 N 8 1


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; Initial USART as 9600,N,8,1;***********************************************************************Init_USART

banksel BAUDCTL ; Bank 3

movlw b'00000000' ; disable Auto-Baud Detect, TxD is RC6, BRG = 8-bitmovwf BAUDCTL

banksel TXSTA ; ### Bank 1movlw b'00100100' ; ### 8-bit data mode , ASYNCmovwf TXSTA ; ### High Speed mode, Enable TxD

;movlw .25 ; ### Set baud rate at 9600 with High Speed modemovwf SPBRG ; ### System Clock are 4MHz using internal RC

bcf PIE1,TXIE ; ### Disable TxD interruptbsf PIE1,RCIE ; ### Enable RxD interrupt

bsf TRISC,7 ; ### set input for RC7, RxD receiving pinbcf TRISC,6 ; ### set output for RC6, TxD pin

banksel 0

movlw b'10010000' ; ### Enable Serial Port, 8-bit receivemovwf RCSTA ; ### Continuous Receive, Disable Address Detection;

bcf PIR1,TXIF ; Clear TxD interrupt flag;bcf PIR1,RCIF ; Clear RxD interrupt flag

;bsf INTCON,PEIEbsf INTCON,GIE

USART Lab7 Question

Question: Send the transmitter data in the main


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Question: Send the transmitter data in the main

program, could we send the data through an interrupt

routing?

Answer: YES


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MASTER SYNCHRONOUSSERIAL PORT (MSSP)

MODULE

Overview

The MSSP module can operate in one of two


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The MSSP module can operate in one of twomodes: Serial Peripheral Interface (SPI)

Inter-Integrated Circuit(I2CTM) Full Master mode

Slave mode (with general address call).

The I2C interface supports the followingmodes in hardware: Master mode

Multi-Master mode Slave mode.

Conditions :

I2C Conditions


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Conditions :

START (S)

STOP (P)

ACKNOWLEDGE (A)

RESTART (R)

NEGATIVE or NOT-ACKNOWLEDGE (N)

SDA

SCL

SDA pulled LOWwhile SCL isstill HIGH

SDA releasedwhile SCL isstill HIGH

SDA goes LOW during9th clock pulse of SCL

Stop condition quickly followedby a Start conditionRecipient does not drive SDALOW

External IC EEPROM Read

+5V


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EEPROM

PIC

SCL

SDA

LISTEN LISTEN LISTEN

READMODEGOTO

ADDRESSSTOPDATA

MASTER

SLAVESSTART DATASLAVEADDRESS

BUSY BUSY

WRITEMODE

ACKEEPROMMEMORYADDRESS

RESTARTNACKSTOPACK

MSSP Control Registers

There are 3 associated control registers


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There are 3 associated control registers

1. MSSP Status Register (SSPSTAT)

SMP Slew Rate Control bit

CKE Not used in I2C mode

D/A Last byte Rx/Tx was data or address

SMP CKE D/A P S R/W UA BF

CONTROL BITS DETECTION BITS (FLAGS)

P Stop Condition Detected

S Start Condition DetectedR/W Slave :READ/WRITE or Master = transmit in progress

UA Address needs to be updated

BF The SSPBUF register is full

BIT FUNCTION


2 MSSP Control

SSPM3 SSPM2 SSPM1 SSPM0 Mode

0 0 0 0 SPI Master mode clock = FOSC/4


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2. MSSP ControlRegister 1 (SSPCON)

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

CONTROL BITS ERROR DETECTION BITS (FLAGS)

WCOL Write Collision Detected

CKP Enables clock

SSPOV A write to the SSPBUF before previous value processed

SSPEN Enables MSSP module

SSPM3 Mode Select Bit

SSPM2

SSPM1

SSPM0

BIT FUNCTION

Mode Select bits

0 0 0 0 SPI Master mode, clock = FOSC/4

0 0 0 1 SPI Master mode, clock = FOSC/16

0 0 1 0 SPI Master mode, clock = FOSC/640 0 1 1 SPI Master mode, clock = TMR2 output/2

0 1 0 0 SPI Slave mode, clock = SCK pin, SS pin control enabled

0 1 0 1 SPI Slave mode, clock = SCK pin, SS pin control disabled,SS can be used as I/O pin

0 1 1 0 I2C Slave mode, 7-bit address

0 1 1 1 I2C Slave mode, 10-bit address

1 0 0 0 I2C Master mode, clock = FOSC / (4 * (SSPADD+1))

1 0 0 1 Reserved

1 0 1 0 Reserved

1 0 1 1 I2C firmware controlled Master mode (Slave idle)

1 1 0 0 Reserved

1 1 0 1 Reserved

1 1 1 0 I2C Slave mode, 7-bit address with Start and Stop bitinterrupts enabled

1 1 1 1 I2C Slave mode, 10-bit address with Start and Stop bitinterrupts enabled


3 MSSP Control Register 2 (SSPCON2)


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3. MSSP Control Register 2 (SSPCON2)

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

CONTROL BITS DETECTION BITS (FLAGS)

GCEN Generates an interrupt when a call is received (slave mode)

ACKEN Initiate ACK/NACK condition (Transmits ACKDT bit)

ACKSTAT 0 = Acknowledge received from slave (transmit mode)

ACKDT 0 = ACK 1 = NACK (receive mode)

RCEN Enables receive mode

PEN Initiates a STOP condition

RSEN Initiates a RESTART condition

SEN Initates a START conditionSEN Initiates a START condition

BIT FUNCTION

Registers Associated with I2C

4 MSSP Receive/Transmit Buffer (SSPBUF)


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4. MSSP Receive/Transmit Buffer (SSPBUF)

Holds the data to be transmitted or the data thathas been received by the MSSP module

When full, the BF (Buffer Full) bit in the SSPSTATregister is set

Any write to the SSPBUF register duringtransmission/reception of data will be ignored,and the write collision detect bit WCOL of theSSPCON register will be set

Registers Associated with I2C

5 Serial Port Address (SSPADD):


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5. Serial Port Address (SSPADD):

Slave mode:

contains the slave address of the PIC

Compared against the received value

Master mode:

Used to calculate the clock speed (BAUD rate) of the I2C

system.

)1(4 SPADD

FoscBAUD RATE =

*NOTE: FOSC is the frequency of the oscillator not theInstruction Clock TCY

MSSP Interrupts

The SSPIF interrupt flag is set in the PIR1


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The SSPIF interrupt flag is set in the PIR1

register with the following events START condition

STOP condition

Data transfer byte transmitted/received

Acknowledge transmit RESTART condition

SSP interrupts will only occur if the SSPIE inthe PIE1 register is enabled as well as the GIEand PEIE in the INTCON.


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MSSP ModuleI2C Lab(Lab8)

EUSART Lab 8



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Setting the MSSP module as 7-bit I2C Master

mode with 100KHz bus rate

Know the I2C command and step by step

Read the I2C temperature sensor TC74 then

show on LEDs

TC74 Command

Read Temperature I2C command for the TC74-A7


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s TC74

Addr

Wr Ack Read Temp.

Command

Ack S TC74

Addr

Rd Ack Temp.

Data

NAck P

1001111 1 0 00000000 0 1001111 0 0 00010011 1

Read Temperature I2C command for the TC74 A7

TC74 Package

Lab8 Specifics



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project C:\RTC\201_ASP\Lab8-I2C Configure the MSSP for the 7-bit I2C Master

Mode

Set both SCL & SDA pin are input mode

Send a Read Temperature command to read

current temperature from TC74-A7

Show the temperature result on the LEDs



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The read temperature command is similar theRandom Read a byte data from I2C EEPROM

Check the SSPIF for each step machine

Who will return the Ack/NAck signal

Bus Collision interrupt bit (BCLIF) handling

USART Lab8 Solution

Init I2C Master


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Init_I2C_MasterBANKSEL TRISC ; Initial PortC,bit 3 & 4 as Inputbsf SCL ; RC3 = SCL , RC4 = SDAnopbsf SDA

;BANKSEL 0movlw b'00101000' ; ### I2C Master Mode, Clock Rate: FOSC/(4*SSPADD+1)movwf SSPCON ; ###

;banksel SSPADDmovlw .9 ; ### This gives 100KHz I2C clock @ 4MHzmovwf SSPADD ; ### (4MHz/4) / (9+1)= 100KHz

;movlw b'10000000' ; ### Disable slew rate control,movwf SSPSTAT ; ### and clear status bits

;

movlw b'00000000' ; Set SCL,SDA into Ready statusmovwf SSPCON2

;return


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Appendix A.Multiple InterruptLab 9

Lab 9 on Multiple Interrupts

This Lab involves:


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This Lab involves:

Dealing with 2 ( or more) concurrent interrupts

Determining the source of an interrupt

Deciding which interrupt request will be serviced

first

Lab 9 Overview

M i P


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Setup PORTB and enableINT0 interrupts onSw2as in Lab 1

Enable Timer1 andPORTC as In Lab 5

Set up CCP as OutputCompare just as in Lab 5

Main Program

Continued on next slide

NOP

Lab 9 Overview

INT0_ISR CCP_ISR


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Toggle variableCalled

push_flag

Clear IF

Clear IF

Call debounce

Delay routinePut -2 in WREG

Put 0 in WREG

Add WREG toCCPR1L

push_flag

Set ?

retfie

retfie

yes


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Lab 9 Specifics

Lab is found in:


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C:\RTC\201_ASP\Lab9-MXINT

The two interrupt Service routine are provided

(INT0_ISR and CCP_ISR)

Complete the following sections of code

When an interrupt occurs, determine the cause

and transfer control to the appropriate ISR Set the SFRs to enable INT0 and CCP1 Interrupt

to occur

What you need to know for Lab

INTCON, and PIR Special Function Registers are


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, p g

used in this lab

Lab 9 Solution

Vector Parsing Section


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NT_VECTOR CODE 0x004 ; interrupt vector location

;

; Save Wreg, STATUS, and PCLATH during Interrupt Service

;

call save_regs;

btfsc INTCON,INTF ; ### test for INT0 interrupt

goto INT0_ISR

btfsc PIR1,CCP1IF ; ### test for CCP Interrupt request

goto CCP_ISR

;

Lab 9 Questions

Question: Why is there a noticeable silence shortly


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y y

when SW2 is released?

Answer: Since debounce is called during an interrupt

and the GIE bit is cleared, the CCP1 interrupt that

toggles the buzzer is not allowed to operate. Therefore,

the buzzer goes quiet

Lab 9 Questions (cont.)

Question: How can this silence be eliminated


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Question: How can this silence be eliminated

and the buzzer continue to run ?

Answers:

1. Capture SW2 in the main and call debouncewhile GIE is set

2. User a timer to accomplish the delay

3. Re-enable interrupts during the INT0interrupt service

Lab 9 Questions (cont.)

Question: Which of these three methods is better?


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Answer: It depends !!

Each has their own advantages and disadvantages

Appendix B. Lab10Access Internal EEPROM


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Project Name : Lab10-EEPROM.mcp

Content in the Lab10

Defined the EEPROM data in the program

Write a byte data to the EEPROM

Read a byte data feom EEPROM

Request to use the MPLAB SIM for this

project

Open EEPROM window in the view manual

Appendix C. Lab11LCD Display Module


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Provided the LCD routine for the LCDModule of APP001

Use the global & extern directiveinstruction for LCD routine access


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201ASP Wrap-Up

201ASP Wrap-up

Today we covered the following


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y g

peripherals on the Mid-Range family I/O ports

Interrupt structure and processing

Timers (timer0, timer1, timer2)

ECCP ( Output Compare, Input Capture, PWM)

Comparators and Analog-to-Digital Converters

Voltage Reference

EUSART Serial Port

I2C using the MSSP module

Final Word

This discussion has followed standard


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MCHP datasheet flow:Overview of peripheral

Register Descriptionand Configuration

Enhanced orSpecial Features

*Packaging and Electrical Specifications are at the endof the datasheet

Use these sections to: Develop logic flow charts or

pseudo-code (Avoid Spaghetti

Programming!!)

Other Tips: Comment your code thoroughly Choose descriptive names

for user defined registers


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Thank You!!

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