Logic Synthesis 07

VLSI TEST LAB. NCKU-EE KJLEE

Advisor: Kuen-Jong LeePresenter: Wei-Cheng Lien

E-mail: [email protected]

Logic Synthesis with Synopsys Design Vision

Reference:1. Synopsys Manual (Version X-2005.09, September 2005)2. CIC Training Manual Jan.-20073. Synopsys Online Support4. CIC News

VLSI System Design NCKUEE-W.C. LianLogic Synthesis with Synopsys .2

Cell-Based Design FlowMatlab/C/C++/

System C/System Verilog/ADS/ConvergenSC

NC-Verilog/Verilog XL/ModelSim/VCS

Design/Power Compiler

SOC Encounter/Astro

NC-Verilog/Verilog XL/ModelSim/VCS

DFT Compiler/TetraMAX

Verilog/VHDL

DRC/LVS (Calibre)

Calibre Xrc/NaroSim/TimeMill & PowerMill/

Star RCXT

Memory Compiler

SynTest

Physical Compiler/Mgama Blast

Tap out

Logic Synthesis &formal verification

Conformal LEC/Assertain ABV

/Formality

Gate-level post-layoutsimulation

transition-level post-layoutsimulation

RTL-levelDesign

Hard IP

Soft IP

Post-layout Verification

Layout-levelDesign

Gate-levelSimulation

Design forTesting

System-levelDesign


How to Set CAD Tool Environment Unix% cp /home4/classuser/sys0701/sys0701ta1/.cshrc . Unix% cp /home4/classuser/sys0701/sys0701ta1/.synopsys_dc.setup . Unix% cp /home4/classuser/sys0701/sys0701ta1/setup.csh . (Source CAD Tool license)


Outline

Basic concepts of logic synthesis [6] Synthesis with Synopsys design vision [52] Synthesizable/good coding styles [7] Conclusions [2]


Chapter 1Basic concepts of logic synthesis


Logic Synthesis

Synthesis=translation+optimization+mapping

(HDL Compiler)

No timing info.

Timing info.

(Design Compiler)

RTL


Logic Synthesis Flow Overview


Module Structure1.Module name & Port list2. Definitions (I/O, wire, reg,

function, parameter, integer)3.Module instantiations4. Module statements & constructs

HDL Compiler (1/2) HDL Compiler translates verilog HDL descriptions

into a netlist with GTECH library (the synopsys default)

HDLCompiler

Symbol View


HDL Compiler (2/2) In schematic view, we can see the verilog file is translated

with a GTECH library

Schematic View


Design Compiler

+TechnologyLibrary

=

TSMC13.v, UMC18.vetcfast.db, slow.dbetc


Chapter 2Synthesis with Synopsys design vision


Synthesis Step1. Edit Your Code for

Synthesis [0]

2. Read in & Set library [2]

3. Design View [2]

5. Apply Design Constraints [7]

4. Set Design Environment [8]

6. Compile Design [6]

7. Report & Analysis [7]

8. Simulation & Wave View [4] Layout


Start to Use Design Vision (1/2) Unix% cp -r /home4/classuser/sys0701/sys0701ta1/student .

(Example) Unix% more .synopsys_dc.setup :

zMenu File Setup


Start to Use Design Vision (2/2)

Invoke Design Vision

(1) XG Mode (After 2005/9)Unix% dv (&)

(2) DB Mode (Before 2004/12)Unix%design_vision db_mode

(3) dcsh Mode (Before 1999)Unix% design_vision dcsh_mode

You can use -no_gui option to stop GUIUnix% Exit (or quit) for leave

XG Mode Supports 1. enhanced DB format (.ddc) format & db2. Tool Command Language (Tcl)


Tcl (Tool Command Language) Tcl changes your life. Tcl Script = A sequence Tcl Commands

design_vision-xg-t> Tcl commands


Step 2: Read File (1/3)

design_vision-xg-t>read_file -format verilog "../add4.v"current_design [module_name]link

2

1

zMenu File Setup


Step 2: Read File (2/3)

z Check if any errors or warnings appearz Modify your designs according to the error or

warning messages


Step 2: Read File (3/3) Read Files with different Methods.

z (1) Menu File Read

z (2) Menu File Analyze

z (2) Menu File Elaborate

design_vision-xg-t> analyze -library WORK -format verilog {top.v timer.v }elaborate top -architecture verilog -library WORK


Step 3: Symbol View

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1

2

design_vision-xg-t> current_design top

You can see the I/O pinsand number of bits they occupied


Step 3: Schematic View

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2

Cell Name

Instance Name


Real World Environment (1/2)

The defaults are not realistic conditions

Input drive is not infinite

Capacitive loading is usually not zero

Process, Voltage, and Temperature (PVT) variation

The operating environment affects

Characteristics of components selected from target library

Timing through your design The operating environment you specify

describes the conditions that the circuit will operate in field.


Real World Environment (2/2)

Target DesignAnother Design

Another Design

Input Drive Strength Input Delay

Output Loading Output Delay

z Specify these parameters and use the synthesis tool to make your design meet the real condition and constrains


Step 4: Setting Design Environment

(1) Setting Operating Condition [1] (2) Setting Input Driving Strength [2] (3) Setting Output Loading [1] (4) Setting Input/Output Delay [2] (5) Setting Wire Load Model [1]


(1) Set Operating Environmentz Attributes Operating Environment Operation Conditions

design_vision-xg-t>set_operating_conditions -min_library fast -min fast -max_library slow -max slow

For Setup Time Check For Hold Time Check


(2) Set Input Drive Impedance (1/2)z Switch to symbol viewz Choose the targeted input portsz Attributes Operating Environment Drive Strength


(2) Set Input Drive Impedance (2/2)

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design_vision-xg-t> set_driving_cell -library slow -lib_cell BUFX4 -pin {Y} [get_ports clk]set_driving_cell -library slow -lib_cell DFFX1 -pin {Q} [remove_from_collection [all_inputs] [get_ports clk]]

not want to scale the port drive capability

Derive design rule attributes from the driving cell and apply them to the ports the cell drives

1. SoC Design uses DFF for partition

2. Clock can model by ring buffer


(3) Set Output Loading z Choose the targeted output portsz Attributes Operating Environment Load

1. How to find the cell load ?

Choose the cell in library

2. Apply to output loading

design_vision-xg-t>set_load [load_of "slow/DFFX1/D"] [all_outputs]


(4) Setting Input/Output Delay (1/2)z 1. Choose input pins except clock.z 2. Attributes Operating Environment Input Delay

design_vision-xg-t> set_input_delay -max 1 -clock clk [all_inputs]set_input_delay -min 0.2 -clock clk [all_inputs]

Attention!The step should executeafter clock specify (Step 5) !


(4) Setting Input/Output Delay (2/2)z 1. Choose output pins z 2. Attributes Operating Environment Output Delay

design_vision-xg-t> set_output_delay -max 1 -clock clk [all_outputs]set_output_delay -min 0.1 -clock clk [all_outputs]

Attention!The step should executeafter clock specify (Step 5)clock specify (Step 5) !


(5) Setting Wire Load Modelz Attributes Operating Environment Wire Lode

design_vision-xg-t> set auto_wire_load_selection false (Turn Off WLM selection)set_wire_load_model -name tsmc13_wl10 -library slowset_wire_load_mode top

Wire Load Model (WLM):Estimate of a nets RC parasitics based on the nets fanout.But WLM isnt useful today.We use Topographical Mode to replace.


Step 5: Apply Design Constraints

Constraints are goals that the Design Compiler uses to optimize a design with target technology library.

During compile, Design Compiler attempts to meet all constraints.

(1) Set Design Constraint [2] (2) Maximum Delay Constraints [1] (3) Specify Clock [2]


(1) Set Design Constraint (1/2)z 1. Choose all top designz 2. Attributes Optimization Constraints Design Constrains

design_vision-xg-t> set_max_total_power 0.0 uwset_max_dynamic_power 0.0 uwset_max_leakage_power 0.0 uwset_max_area 6000set_max_fanout 2 [all_inputs]set_max_transition 0.3 [all_inputs]


How to know gate count of your design?

(1) Set Design Constraint (2/2)

First See the area your design after synthesis useMENU Design Report Area ordesign_vision-xg-t> report_area

Gate counts =Chip Report Area/NOR2 Area

Quick ViewNOR2(NAND2) Area = 5 for 0.13um library10 for 0.18um library

tsmc13g.pdf


(2) Maximum Delay Constraints z Choose start and end points of timing path

(push ctrl bottom to choose them)z Attributes Optimization Constraints Timing Constrains

For Combinational circuit primarily


(3) Specify Clock (1/2)z 1. Choose input port clockz 2. Attributes Specify ClocksBut some times the Tool will disappear when you check the option, we use command instead GUI.

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2


(3) Specify Clock (2/2)1

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6

Basic constraints for clockdesign_vision-xg-t> create_clock clock period 5 -waveform {2.5 5}set_fix_hold clockset_dont_touch_network clock

Other constraints for clockdesign_vision-xg-t> set_clock_uncertainty 0.1 [get_clocks clock]set_clock_latency -source 0 [get_clocks clock]set_clock_latency 1 [get_clocks clock] set_input_transition 0.3 [all_inputs]set_clock_transition 0.3 [all_clocks]

Not re-buffer the clock

Automatic solve hold time violation

VLSI System Design NCKUEE-W.C. Lian

Clock Network Effects

Logic Synthesis with Synopsys .37


Check Designz Menu Design Check Design

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3

2

4

5design_vision-xg-t> check_design


Some Warnings Solution Whats wrong after design check? (1) multiple design instance Sol: 1. Select the most top design of the hierarchy

2. Hierarchy/Uniquify/ Hierarchydesign_vision-xg-t> uniquify

(2) assignment problemdesign_vision-xg-t> set_fix_multiple_port_nets all buffer_constants

complie(3) does not drive any nets dont care!

For more detail


Save Script File for Constraintsz MENU File Save Info Design Setup

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design_vision-xg-t> write_script > //chip.dc

Attention! You should add uniquify to the dc fileand solve Multiple Instance


Execute Script File

z Setup Execute Script1

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4

design_vision-xg-t> source //chip.dc


Step 6: Compile Overview

Logic Level Optimization

Gate Level Optimization

Map

Flatten Structure

For Area/Speed

For Area(Default: ON)

Form SOP terms(Default: OFF, Only for timing goal and banishing dont care)

Replace GTECH cells from target library


Apply Structure & Flatternz Attributes Optimization Directives Design

Consider timing constrains

Use boolean algebra to reduce size

Computer resource

Output Sharing

Use Karnaugh map


Mapping (Compile Design) (1/3)

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2z Menu Design Compile Design

design_vision-xg-t> compile -map_effort medium -area_effort medium


Mapping (Compile Design) (2/3)Mapping current

Design with library

Set amount ofCPU time

Set area recovery phase

Reference: Design Manual

Use only local improvementno mapping

Remove all designs except dont_touch

optimizes across all hierarchical boundaries

sequential elements in optimized design must exactly match RTL

replaces all sequential elements with scan-equivalent cells

fix design rule violations without performing design optimization.


Mapping (Compile Design) (3/3)z Check if any errors or warnings exist!

2. DC-Ulrta

1. General Compile


High Performance Designs This command requires a DC-Ultra license and a

DesignWare (technology-indep soft macros) Foundation license.

4 addition options in new versions (DC 2005.09-SP3)z Menu Design Compile Ultra

design_vision-xg-t> compile_ultra scan -no_uniquify -no_autoungroup

compiler optimizes designs that have multiple instantiations

perform a test-ready compile

automatically removes levels of hierarchy


Step 7: Report & Analysis

(1) Timing Report(2) Area Report(3) Power Report


(1) Timing Report (1/2)z Menu Timing Report Timing

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3 design_vision-xg-t> report_timing -path full -delay \max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group


(1) Timing Report (2/2)Unit: ns

Slack (Setup, Max delay) = Data Required Time Data Arrival Time0Slack (Hold, Min delay) = Data Arrival Time Data Required Time0

Max for setup


(2) Area Report (1/2)

z Menu Design Report Area

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2 3

design_vision-xg-t> report_area -nosplit


(2) Area Report (2/2)zUnit: um*um (CIC Default)

Dont care net area.

Report for this.

Gate counts =Chip Report Area/NOR2 Area= 2480 / 5 = 496

Quick ViewNOR2(NAND2) Area = 5 for 0.13um library10 for 0.18um library


(3) Power Report (1/2)z Menu Design Report Power

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design_vision-xg-t> report_power


(3) Power Report (2/2)


Highlight Menu View Highlight Critical Path


Save Design (1/2)z Menu File Save Asz Remember to check the Save all designs in hierarchy bottom

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design_vision-xg-t> write -hierarchy -format verilog -output /../top_compile.v

5


Save Design(2/2)

The .ddc format saves only the logical design information. (not save physical information)

The .db format saves both information. Menu File Save As

design_vision-xg-t>write -format ddc -hierarchy

design_vision-xg-t>write -format db -xg_force_db -hierarchy

design_vision-xg-t>read_db [design_name].db

design_vision-xg-t> read_ddc [design_name].ddc


Supported Database Formats by Tool

Reference:XG Mode User Guide


Save Design - Timing FileSynopsys Design Constraints (SDC) is a format used to specify the design intent, including the timing and area constraints for a design.SDC is based on the tool command language (Tcl).

design_vision-xg-t> write_sdf version 1.0 context verilog chip.sdf

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Step 8: Verilog Simulation (1/2)

Add initial $sdf_annotate(chip.sdf", top);

Delay effect

z Modify the testfixture

z Unix% verilog testfixture.v top_compile.v /../tsmc13.v +neg_tchkz Or use `include directive then Unix% verilog testfixture.vz timescale should appear in both the design file and textfixture file


Step 8: Verilog Simulation (2/2)

*** SDF Annotator version 2.2.4*** SDF Interface version 5.2.1*** SDF file: add16_3.sdf*** Back-annotation scope:

test_adder.Add*** No configuration file specified -

using default options*** SDF Annotator log file: sdf.log*** No MTM selection parameter

specified

*** No SCALE FACTORS parameter specified

*** No SCALE TYPE parameter specified

Configuring for back-annotation...

Reading SDF file and back- annotating

timing data...

*** SDF back-annotation successfully completed


Chapter 3Synthesizable/good coding styles


Unsupported definitions and declarations- primitive user-definition- time declaration- event declaration- triand, trior, tri1- tri0, trireg net types- Ranges and arrays for integers

Unsupported statements- initial statement- repeat statement- delay control- event control- wait statement- fork statement- deassign statement- force statement- release statement

Unsupported Verilog Language Constructs

Reference: HDL Compiler (Presto Verilog) Reference Manual

Unsupported operators-Case equality &-inequality operators (=== and !==) Unsupported gate-level constructs- nmos, pmos, cmos, rnmos,- rpmos, rcmos- pullup, pulldown, tranif0,- tranif1, rtran, rtrainf0, - rtrainf1 gate types Unsupported miscellaneous constructs- hierarchical names within a module

If you use an unsupported construct,Presto Verilog issues a syntax error such as event is not supported


Unsynthesizable Coding Style Verilog code is not pure RTL code.

Cannot use # delay commandEx:always@(posedge clk) begin

#20 a=c;end

Cannot use initial block in your design.Ex: module count(clk,c);

initial beginc=0;

end Cannot use the same reg in different always blocks.

Ex: always@(posedge clk) begina=c;

endalways@(posedge clk or negedge reset) begin

a=d; end

# delay cannot be synthesis to gate

Initial block only can be used in testfixture

One value cannot be driven by 2 condition


Warning/Error Messages for Unsynthesizable Codes

The warning message like cant read verilog file will appear when opening a verilog code that cannot be synthesized by Synopsys Design Vision.

Carefully check the messages when warned during synthesis and then make corresponding modifications.


Good Coding Style for Synthesis

Try to use always block and wire and assign command.

When you write Verilog code, at first you must consider the actual hardware.always @ (posedge clk) Flip-Flop

always @ (posedge clk or posedge reset) Flip-Flop with Reset

if (reset)

always @ (a or b) Latch or Combinational

wire a=(c=1)?b:d; Mux

wire a=b*c; Combinational


Unknown Simulation Resultsz Testfixture doesnt have $sdf_annotate declaration

z Your testfixture file must have :initial $sdf_annotate(g-bist4b4hs2.sdf,bist_sd);

z Timing violationHow can it happen? (a FlipFlop)

Try to slow down the clock or re-design

clk

D

Q

How can it happen? ( a Latch)

En

in

out

Try to re-design


Blocking and Non-Blocking (1/2)

z Using blocking assignments within combinational alwaysblock

always @(a or b or x) beginx = a & b;y = x | b;x = a;

end

youexpect

always @(a or b or x) beginx


Blocking and Non-Blocking (2/2)

z Using nonblocking assignments within sequential alwaysblock

always @(posedge clock) beginx


Conclusions Logic synthesis transforms verilog codes to

gate-level netlists at a more realistic level. The EDA tool, Synopsys Design Vision, helps

users to synthesize their own designs according to default/user specified conditions/constraints.

Good coding styles lead to synthesizable designs that meet specifications.

Art of Writing TestBencheshttp://www.asic-world.com/verilog/art_testbench_writing.html


Synopsys Documentation On Line documentation in Synopsys Web Site:

http://www.synopsys.com/support/dotw.html

Off Line documentation (DIR: \usr\cad\synopsys\doc\online\dc\...) Use Tool Option Menu Help Design Vision Online Help

Logic Synthesis withSynopsys Design VisionCell-Based Design FlowHow to Set CAD Tool EnvironmentOutline 5Logic Synthesis 7HDL Compiler (1/2)HDL Compiler (2/2)Design Compiler 11Synthesis StepStart to Use Design Vision (1/2)Start to Use Design Vision (2/2)Tcl (Tool Command Language)Step 2: Read File (1/3)Step 2: Read File (2/3)Step 2: Read File (3/3)Step 3: Symbol ViewStep 3: Schematic ViewReal World Environment (1/2)Real World Environment (2/2)Step 4: Setting Design Environment(1) Set Operating Environment(2) Set Input Drive Impedance (1/2)(2) Set Input Drive Impedance (2/2)(3) Set Output Loading (4) Setting Input/Output Delay (1/2) 29(5) Setting Wire Load ModelStep 5: Apply Design Constraints(1) Set Design Constraint (1/2)(1) Set Design Constraint (2/2)(2) Maximum Delay Constraints (3) Specify Clock (1/2)(3) Specify Clock (2/2)Clock Network EffectsCheck DesignSome Warnings SolutionSave Script File for ConstraintsExecute Script FileStep 6: Compile OverviewApply Structure & FlatternMapping (Compile Design) (1/3)Mapping (Compile Design) (2/3)Mapping (Compile Design) (3/3)High Performance DesignsStep 7: Report & Analysis(1) Timing Report (1/2)(1) Timing Report (2/2)(2) Area Report (1/2)(2) Area Report (2/2)(3) Power Report (1/2)(3) Power Report (2/2)HighlightSave Design (1/2)Save Design(2/2)Supported Database Formats by ToolSave Design - Timing FileStep 8: Verilog Simulation (1/2)Step 8: Verilog Simulation (2/2) 62Unsupported Verilog Language ConstructsUnsynthesizable Coding StyleWarning/Error Messages for Unsynthesizable Codes Good Coding Style for SynthesisUnknown Simulation ResultsBlocking and Non-Blocking (1/2)Blocking and Non-Blocking (2/2)ConclusionsSynopsys Documentation

Documents

Logic Synthesis 07