NORA based TDC in 90nm CMOS

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NORA based TDC in 90 nm CMOS

N. Petra a,n, S. Russo b, D. De Caro a, E. Napoli a, G. Barbarino c, A.G.M. Strollo a

a Department of Electronics Engineering, University of Napoli “Federico II”, via Claudio 21, I-80125 Napoli, Italyb Laboratoire de Physique Nucléaire et des Hautes Énergies, Université Pierre et Marie Curie Paris 6, Université Paris Diderot, Paris 7, CNRS—IN2P3, 4 place Jussieu,75252 Paris Cedex 05, Francec Department of Physics, University of Napoli “Federico II”, Italy

a r t i c l e i n f o

Article history:Received 17 October 2012Received in revised form13 March 2013Accepted 20 March 2013

Keywords:TDCDynamic logicPrecharged logicNORA logic

92/$ - see front matter & 2013 Elsevier Ltd. Ax.doi.org/10.1016/j.mejo.2013.03.015

esponding author. Tel.: +39 081 768 3680.ail address: [email protected] (N. Petra).

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a b s t r a c t

This paper investigates the idea to construct Time-to-Digital Converter (TDC) circuits based on dynamicprecharged NORA delay elements. A self-charging technique is proposed in order to accommodate thedynamic delay elements in a ring-oscillator like structure. The employ of dynamic logic allows to reducethe TDC resolution with respect to previous TDCs based on standard CMOS logic. The ring-oscillator liketopology imparts a very large dynamic range to the proposed circuit. In the paper a TDC, based on aPseudo-differential topology, is presented, that is robust against PVT and mismatch variations. The TDC isfabricated in 90 nm CMOS technology, and presents a resolution of 25 ps. Experimental measurementsconfirm the effectiveness of the idea and show that the proposed TDCs exhibit low INL and a largedynamic-range when compared with state-of-the art circuits.

& 2013 Elsevier Ltd. All rights reserved.

1. Introduction

IME-TO-DIGITAL converter (TDC) is widely used in several appli-cations, such as scientific experiments [1], range-finding [2,3],all-digital frequency synthesis [4–8], GFSK transceivers [9], testequipment [10], on-chip testing structures [13]. A TDC measures atime and returns the digital encoded value of the measurement,similarly to an Analog-to-Digital converter where the time repre-sents the analog information. The measured time can be thedelay between two events or the delay between a signal and areference clock.

In order to have large dynamic range and high resolution TDCscan be designed combining a synchronous counter and an asyn-chronous fine interpolator. As an example Fig. 1 shows a simpleTDC measuring the delay between the Start and Stop signals.When Start goes high the NAND gate and the inverters act as a freerunning ring oscillator and produce the clock for the synchronouscounter. When Stop goes high the D-flip-flops latch the state of thedelay line. The value counted by the counter represents the coarsepart of the measure. The state of the delay line latched by flip-flopsrepresents the fine part of the measure.

The resolution of the TDC shown in Fig. 1 is equal to the delay ofan inverter. As the technology scales down the delay elementscan be design to exhibit very low delays [14–16]. TDCs with few

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al., NORA based TDC in 90

dozens picoseconds resolution can be easily designed with thescheme of Fig. 1 with nowadays technologies.

In order to further improve resolution several fine interpolatorshave been proposed in literature. A first class of fine interpolators[10–12] exploits the delay difference between two logic gates.As an example in Fig. 2 the TDC proposed in [10] is shown. The Dinputs of the flip-flops (Start) propagate through a chain of buffershaving delay τ1, whereas the clock (Stop) propagates through achain of buffers having delay τ2≠τ1. The buffers on the clock actas the Vernier scale used in calipers giving a resolution equal to|τ2-τ1|. Since |τ2-τ1| can be smaller than the τ1 and τ2 the resolutioncan be better than the resolution of the TDC in Fig. 1. Beside theresolution, a difference between the TDC in Fig. 1 and the TDC inFig. 2 is the measurement time. When the Stop signal is asserted,the TDC in Fig. 1 concludes the measure in the time needed bythe flip-flops to latch the D inputs. The TDC in Fig. 2 must wait forthe Stop signal to propagate through a large number of buffers.The lower |τ2-τ1| the higher the number of buffers Stop mustpropagate through. Hence a trade-off exists between resolution andmeasurement time.

In [13] the difference between the frequency of two oscillatorsis used in place of the difference in delay to implement a Vernierbased TDC. The Start and Stop signals are used to activate the twooscillators. After a number of periods the two oscillators will be in-phase. The number of periods needed for re-phasing gives themeasured value.

Pulse shrinking [17,18] is another Vernier based technique toimplement TDCs. Here the length of a pulse is the time to bemeasured. The pulse propagates through a chain of inverters. The

nm CMOS, Microelectron. J (2013), http://dx.doi.org/10.1016/j.

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Fig. 1. TDC based on a free running ring oscillator.

Fig. 2. Vernier based TDC.

Fig. 3. Chain of NORA inverters.

N. Petra et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎2

inverters are designed in order to have different rise-time and fall-time. Due to the difference between rise and fall time the pulseshrinks down till it disappears. The number of inverters needed toshrink the pulse is a measure of the pulse width.

Multistage interpolation [19] is another technique for highresolution TDCs. Successive approximation is used in these circuitsto compute the binary word representing the measured time. Asper Vernier based technique, a trade-off exists between measure-ment time and resolution.

Sub-gate-delay resolution is achieved with the multi-path ringoscillator proposed in [20]. Here a ring oscillator is used as thefine interpolator of the TDC. The resolution is improved using astructure where each inverter is driven by the output nodes ofseveral other inverters along the chain. The multi-path structureallows decreasing the delay per stage by a factor of 5–6 withrespect to the delay of a single inverter. However the designprocess requires extensive simulations to properly size the tran-sistors and choose the connections between the inverters. Further-more moving the design to a new technology requires to repeatthe design process starting from scratch.

Beside resolution, linearity is another important parameter ofa TDC. Integral non-linearity (INL) and differential non-linearity(DNL), like in ADCs, are used to measure the linearity of TDCs.Non-linearity can be due to differences in the delay elements ofthe TDC (for instance the delay of the NAND gate in the TDC ofFig. 1 is different by the delay of the inverters) or to mismatch inthe capacitive load of the delay elements. Another cause of non-linearity can be the mismatch between the low-to-high and thehigh-to-low delay of the inverters [16]. For instance, in Fig. 1, whenone inverter has a low-to-high transition, the next inverter willhave a high-to-low transition, and the two delays depend on thecurrent the p-channel MOSFET and the n-channel MOSFET cancarry. Although the inverter can be designed to have equal low-to-high and high-to-low delays, process variations can affectn-channel MOSFETs and p-channel MOSFETs in a different way.This non-linearity source does not appear in the TDC of Fig. 2where all the buffers have a low-to-high transition. In conclusionhigh linearity can be achieved designing TDCs having identicaldelay elements, making the same transitions and having a regularlayout.

In this paper a novel TDC is proposed. We focus on fast non-Vernier based TDCs. The proposed TDC is based on the schemeof Fig. 1. In order to achieve sub-gate resolution, the proposedTDC uses fast, pre-charged, dynamic logic [21] to implement theinverters. The resulting resolution is intrinsically smaller thanTDCs using standard CMOS inverters. In order to arrange thedynamic inverters in a ring topology a self-charging strategy isproposed. Linearity of the proposed TDC is improved by using

Please cite this article as: N. Petra, et al., NORA based TDC in 90mejo.2013.03.015i

pseudo-differential topology. The techniques proposed in [20] canbe applied to our TDC to further improve the resolution.

The paper is organized as follows. In Section 2 the use ofdynamic logic within a TDC is discussed. The architecture ofthe proposed TDC is shown in Section 3. Circuit implementationresults are shown in Section 4 while conclusions are carried out inSection 5.

2. TDC with dynamic delay elements

The resolution of a TDC based on the scheme of Fig. 1 dependson the delay of the inverters of the asynchronous fine interpolator.The inverters are usually implemented using CMOS logic. In orderto improve resolution we propose to use dynamic logic [21] toimplement the inverters.

Among dynamic logic families, no-race (NORA) [21] logic iswell known to provide reduced delay. A chain of NORA inverters isdepicted in Fig. 3. Each n-type NORA inverter feeds a p-type NORAinverter. Before the Start signal can propagate through the inver-ters chain all the n-type inverters must be precharged high(through the PreNi signals, i¼1,3,…) and all the p-type invertersmust be precharged low (through the PrePi signals, i¼2,4,…). Onceprecharged the cells can be enabled through the signals enNi

(i¼1,3,…) and EnP i (i¼2,4,…). At this point a low-to-high transi-tion on the signal Start propagates through the chain with a smalldelay due to the reduced load at the output of the inverters.

In order to estimate the advantage of NORA inverters withrespect to standard CMOS inverters we have simulated twoinverters chains in the UMC 90 nm CMOS technology. One chainuses 24 standard CMOS inverters and the other uses 24 NORAinverters. Both CMOS and NORA use the same transistor sizing.The size of p-channel MOSFETs is chosen in order to balance low-to-high and high-to-low delays. The results of the simulation areshown in Fig. 4 where the 2nd and the 22nd inverter's outputwaveform for both CMOS and NORA inverter chain is shown,together with the Start signal. As can be seen the propagationdelay (and hence the resolution) of the NORA inverters chain is29% smaller than the propagation delay of CMOS inverters chain.

The use of NORA inverters in a TDC based on the scheme ofFig. 1 is not straightforward due to the presence of the precharging(PreNi and PrePi) and enabling (enNi and EnP i) signals. In thestandard design of NORA logic circuits these signals are the twophases of the clock. However in order to allow the NORA invertersto be arranged within a free running ring oscillator topology theprecharging and enabling signals must be dynamically changedduring the oscillation of the ring.

To that purpose we propose a novel self-charging scheme inwhich the precharging and enabling signals of each NORA inverterare driven by the output of the other inverters of the ring. Thebasic idea behind proposed scheme is that a NORA inverter muststay enabled for the time needed to allow the subsequent invertersto switch. Once the inverter has propagated the Start signal, it canbe precharged and, afterwards, enabled. In the following sectionwe detail the TDC architecture and the proposed self-chargingscheme.






Fig. 4. Comparison between NORA and CMOS inverters chains.

Fig. 5. Proposed differential dynamic TDC.

Fig. 6. Control bus.

Fig. 7. Differential dynamic delay element.

Fig. 8. Timing diagram of the signals of the differential dynamic delay element.

N. Petra et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 3

3. TDC architecture

Fig. 5 shows the top-level architecture of the proposed TDC.The architecture uses a synchronous counter and a fine interpo-lator. The fine interpolator is obtained as a chain of L pseudo-differential dynamic delay elements controlled through the con-trol bus. The control bus, shown in Fig. 6, drives three globalsignals and their complements to all the delay elements. The“Global Precharge” signal is used as a reset signal to precharge allthe dynamic delay elements at the beginning of the measure. The“Global Enable” signal is driven low to stop the measure, disablingthe delay elements. This signal is the complement to the STOPsignal in Fig. 1 and is used to stop the measure. The “Global Static”is used to allow reading the state of the delay elements chain andits use will be detailed in the following.

As we will show the outputs of each delay element must beconnected to the pre-charge logic of another delay element. Suchconnection is ensured by the self-charging feedback bus.

The delay elements compute two differential outputs (OutNi

and outPi) and their logical complement (OutNi and OutPi ). Fig. 7shows the detail of the differential dynamic delay element. Thetwo NORA inverters in the dashed boxes are used to computethe two complementary outputs OutNi and OutPi from OutNi−1

and OutPi−1. The complemented outputs OutNi and OutPi arealso computed with the aid of two standard CMOS inverters.The enable and precharge signals of the two NORA inverters areobtained through the NAND and NOR gates depicted in the figure.The control bus provides the “Global” control signals to theinverters. When the “Global Precharge” signal goes high the twoNORA inverters are precharged through the signals PreNi andPrePi. When the “Global Enable” signal goes low the delay


elements are disabled through the signals EnNi and EnPi freezingthe chain and stopping the measure.

The NORA inverters can also be disabled and precharged by theoutputs OutN iþk and OutP iþk of another delay element (k positionsahead in the inverters chain of Fig. 5). When the i+k-th delay cellswitches (OutN iþk-1 and OutPiþk-0) the i-th cell is disabled andprecharged. When the i+k-th delay cell is precharged (OutN iþk-0and OutP iþk-1) the i-th cell is enabled. The signals OutN iþk andOutPiþk are provided to the delay element through the feedbackbus. As an example, in Fig. 8 the timing diagram of the signals ofthe differential dynamic delay element in a typical commutationare reported. When the i+k-th cell is precharged the signalOutN iþk goes low. In this phase the signal Global Enable isasserted, hence Gen is zero and the signal EnNi goes high. At thispoint the NORA inverter in the upper part of Fig. 7 is enabled andthe signal OutNi will go low as soon as the signal OutPi−1 goeshigh. It is worth pointing out that the parameter k must be chosenin order to ensure that the signal EnNi goes high before the signalOutPi−1 goes high, otherwise the NORA inverter is not enabledwhen its input changes and the ring oscillator does not workcorrectly. The NORA inverter in the lower part of Fig. 7 is driven bysignals behaving in a similar way.

The feed-back bus of Fig. 5 is used to feed-back the signalsOutN iþk and OutP iþk to the i-th delay element. This mechanismallows the dynamic delay elements to be used within a ringstructure. The CMOS inverters used to compute OutN i and OutP i

make the delay of the dynamic inverters independent from thecapacitive load of the feedback bus.







The sync and static latch in Fig. 7 is used to synchronize theoutputs of the two NORA inverters and to allow the latching ofthe state of the delay line. Fig. 9 shows the Sync and Static Latchcircuit. This circuit resembles the input stage of the strong-armflip-flops [22]. During the measure the signal Gen is asserted(Gen¼1, Gen¼0) whereas Static¼0 and Static ¼ 1. The gray-edMOSFETs in Fig. 9 are turned off and the circuit is used as a synclatch between the signals OutNi and OutPi. In this configuration atransition high-to-low of OutNi produces a transition low-to-highfor outPi whereas a transition low-to-high of outPi produces atransition high-to-low on OutNi. When the measure ends thesignal Gen goes low (Gen¼1). In this configuration the delay chainfreezes (see Fig. 7) and the nodes OutNi and OutPi are floating. Thelatch is used to make these nodes static. When the signal Staticgoes high (Static ¼ 0) the circuit in Fig. 9 acts as a standard latchand the signals OutNi and OutPi become static. In this phase, thestate of the ring structure, that encodes the fine measure of theTDC, can be read by using the outputs OutN i and OutP i of the twoinverters shown in Fig. 7. Please note that, differently from the

Fig. 9. Sync and static latch.

Fig. 10. Differential dynamic initial element.

Fig. 11. Analysis of PVT variations robustness: waveform representing the (a) OutP outoutputs of three subsequent single-ended dynamic delay elements.


general scheme of Fig. 1, in proposed circuit no flip-flop is neededto latch the state of the ring.

The Differential Dynamic Initial Element in Fig. 5 is used tostart the ring oscillator. It has the same topology as the pseudo-differential dynamic delay element in Fig. 7, but the two NORAinverters are implemented as shown in Fig. 10. The MOSFETsdriven by Start and Start allow enabling the oscillation of the ringwhen OutNL¼1 and OutPL¼0.

The pseudo-differential structure of the delay elements makesthe circuits robust against PVT variations. Considering processvariations and large volume production, the TDCs based on thescheme of Fig. 1 can exhibit poor non-linearity because of thedifferent low-to-high and high-to-low delays of the inverters. Inparticular, when the signal START goes high, the first inverter (andall the odd inverters) in Fig. 1 has a low-to-high transition, whilethe second inverter (and all the even inverters) has a high-to-lowtransition. Considering the “slow-n/fast-p” process corner, thedelay of odd inverters—due to the p-channel MOSFETs—is smallerthan the delay of the even inverters—related to the n-channelMOSFETs. The proposed TDC does not have this weakness since allthe inverters have the same transition: a low-to-high transition onthe out-P output and a high-to-low transition on the out-N output.As an example, in Fig. 11 a, the OutP signals of three subsequentdelay elements are reported. The waveform are obtained simulat-ing a long chain of pseudo-differential delay elements realized inUMC 90nm technology considering the “slow-n/fast-p” processcorner. As can be seen the three waveform are equally spaced by11ps. A similar simulation has been done on a chain of singleended dynamic delay elements. The waveform obtained in the“slow-n/fast-p” process corner are reported in Fig. 11b. As can beseen, in this case, the three waveform are not equally spaced andthe delay between the first and the second waveform (8 ps), whichis due to the fast p-channel MOSFETs, is smaller than the delaybetween the second and the third waveform.

As a consequence process variations have a weaker influenceon the non-linearity of the proposed TDC. This characteristicmakes proposed solution useful in all the applications wherelow INL is of primary concern.

3.1. Self-charging mechanism

Each delay cell in the proposed TDC is used to pre-charge anothercell through the self-charging feedback bus. In order for this mech-anism to work, the feedback bus must be properly designed. Asshown in Fig. 7, the i-th cell is precharged (PreNi ¼ 0 and PrePi¼1)

puts of three subsequent pseudo-differential dynamic delay elements and (b) the






Fig. 13. DNL of proposed TDC.


when the i+k-th commutates (OutNi+k-0 and OutPi+k-1). Once thei-th cell is precharged, the i+1-th cell has a floating output. This eventmust only happen when the i+1-th cell has completed its commu-tation. As a consequence k cannot be chosen too small.

On the other hand, the i-th cell is enabled (enPi ¼ 0 andenNi ¼ 1) only when the i+2k-th cell commutates (OutNi+2k-0and OutPi+2k-1). Hence k must be chosen small enough to allowthe i-th cell to be enabled before its input changes. This constraintcan be written as in the following equation:

ðL−2k−1Þτp4τpre þ τen ð1Þwhere τp is the propagation delay of one delay element, L is thetotal number of delay elements in the ring, τpre is the time neededto precharge the i+k-th cell and τen is the time needed to enablethe i-th cell. Since τpre and τen depend on the capacitive load of theself-charging bus, they can be large delays. As a consequence, inorder to meet the constraint (1), either k must be small enough orL must be large enough.

The proper values of L and k in a real design can be obtainedwith the aid of a simulation using (1) as a constraint. In general thechoice of L and k is not unique.

Fig. 14. INL of proposed TDC.

4. Circuit implementation

In order to experimentally verify the proper functionality of theproposed TDC, we have fabricated a chip whose micrographs isreported in Fig. 12. The chip features two identical TDCs (namedTDC1 and TDC2 in Fig. 12). The use of two TDCs allows estimatingthe effect of voltage and temperature variations on the measure-ment. In our test chip TDC1 is used to measure the period of astable reference clock. This measure allows estimating the resolu-tion of the TDC. Furthermore it allows tracking the resolutionchanges due to temperature and voltage variations. The TDC1 andits control logic work synchronously with the reference clock andprovide a digital word (the measure) that can be used to computeand track the LSB of the TDC. The control signals of this TDC(Global precharge, global enable, global static, start/stop signal)are computed by a dedicated circuitry so that the TDC can conti-nuously provide the measured value.

TDC2 is used for the actual measurement of the period of anexternal signal. TDC2 works in an asynchronous way. It receivesthe control signals directly from the pads of the chip.

The test chip in Fig. 12 is fabricated using a 90 nm CMOStechnology. The TDCs in this chip are both formed by 52 pseudo-differential delay elements and the parameter k is equal to 10.We used the Agilent 81134A pulse/pattern generator to providethe reference clock and the signal whose period is measured bythe TDC2. The testing setup is completed with a Tektronix TLA721

Fig. 12. Micrograph of pseudo-defferential TDC in 90 nm.


that we used to drive the control inputs and to store the resultof a large number of measurements. The mean value of theobtained measurements allowed us to compute the non-linearityof the TDC.

Fig. 13 shows the measured DNL of the TDCs while Fig. 14shows the measured INL. As can be seen both non-linearitiesremain below the LSB. During the design process we couldestimate the effect of PVT variations on the DNL and INL. Theproposed TDC did not show any evident relation between thetechnology corner and the INL or DNL due to its differential nature.

Beside non-linearity the measurement's accuracy depends onthe single-shot precision. Some TDCs can give different resultswhen the same time value is measured repeatedly. The reason isthat the TDC intrinsic jitter might be larger than the LSB. Thisphenomenon is frequent in Vernier based TDCs or TDCs based ontime expansion, where the time amplification can be non-constantand a measurement jitter can be added. However the meanoperation used to extract the non-linearity of the TDC can hidesuch measurement jitter. In order to compute the single-shotprecision for the proposed TDC we have repeated the measure of4 time values about 1000 times. The values we analyzed are 10 ns,20 ns, 50 ns and 60 ns and for each measured value an histogramwas plotted. As shown in Fig. 15 the measurement is stable in thefour considered points. The analysis reported in Fig. 15 shows thatour TDC jitter does not worsen the measurement accuracy andthat the TDC LSB is equal to its resolution.

Table 1 shows the performance of the proposed TDC andcompares with state of the art TDCs. As can be seen there areseveral differences between state of the art TDCs. In termsof resolution (LSB of the TDC) the proposed circuit does notreach the final performance of other architectures. However the






Fig. 15. Single shot precision analysis: histogram of the results obtained measuring 10 ns (a), 20 ns(b), 50 ns (c) and 60 ns (d).

Table 1Comparison with state of the art.

TDC type Technology(nm)

Resolution(ps)

Range Area(mm2)

Powerdissipation(mW)

MaximumINL (LSB)

MaximumINL (ps)

Measurementspeed

PVT variationsrobustness

This paperpseudo-differential

Precharged dynamicdifferential delay elements

90 25 10.6 μs 0.10 19 0.65 16.2 Fast Yes

[15] Precharged dynamic delayelements

180 41 18 μs 0.09 25 0.77 31.6 Fast No

[20] Multi-path ring oscillator 130 6 12.3 ns 0.04 2.2–21 N.A. N.A. Fast No[19] Successive approximation 350 1.2 327 μs o4.45 33 1-6.5 1.2-7.8 Slow Yes[10] Vernier 90 1* 200 ps* N.A. N.A. 5.6* 5.6* Slow Yes[3] Multi-phase ring oscillator 130 13 67 ns N.A. 15 1.2 15.6 Fast No[12] Multi-level interpolation 350 12.2 202 μs N.A. 40 0.4 4.88 Fast No

n simulation results.


non-linearity of the proposed TDCs remains very small ensuringaccuracy of the measure.

Comparing to the multi-path ring oscillator technique [20] theproposed architecture exhibits PVT variation robustness that ispaid by an increment in the resolution. Both proposed and multi-path ring oscillator TDCs exhibit small measurement time. Asshown in [20] this feature can be exploited to modulate thequantization error in applications such as all digital PLL designs.

With respect to Vernier based and Successive approximationmethods, the proposed TDCs exhibit a low measurement time anda better non-linearity.

The measurement range of the proposed TDC is quite largeallowing the proposed circuit to be used in several applications.Furthermore the absence of high-to-low and low-to-high delaysasymmetry makes the pseudo-differential topology a robust solution.

5. Conclusions

We propose a novel TDC architecture based on dynamic no-race NORA delay elements. The TDC exploits a self-prechargingmechanism where each delay element provides the control signalsneeded to precharge and enable the other delay elements. Theproposed TDC exhibits 25 ps resolution with a dynamic range of10.6 μs and a low INL. Experimental measurements of fabricated


ICs are reported in the paper to verify the performance of theTDCs.

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NORA based TDC in 90nm CMOS