Oled Display Training

- 1 -

OLED Display 기술

1 Introduction

2 OLED amp PLED materials

3 Device Operation

4 Device Performance

5 OLED Display- Full color OLED 구현방법- PMOLED and AMOLED- Emission type- AMOLED products

6 Summary

1 Introduction Display 분류

- 2 -

Electronic information displays

Projection Direct-view Off-screenDMDTMA

Light valveLCOS

Flat-panel

Shadowmask

Beamindex

Mono-chrome

Emitter

Nonemitter

Luminescence Incandescence

CL (Flat CRT)

Liquid-crystal Electro-chromic

Electro-phoretic

Ferro-electric

Activematrix

Passivematrix

Plasmaaddressed TFT MOS MIN Diodeothers TN STN FLC others

EL LED Gas discharge (PDP)

OrganicInorganic

Non-coherentdisplays

Coherentholograms

CRTCRT

FED VFD AC DC

Polymer Small Molecule

1 Introduction

- 3 -

Luminescence의종류

구분 Excitation Source 적용분야

PL Photoluminescence 광 PDP 형광등

EL Electroluminescence Electric Field OLED laser diode

CL CathodeluminescenceCathode Ray

(Electron)CRT FED

i

V

p n

bull Inorganic Semiconductor LEDs(p-n junction LED)

1 Introduction What is OLED display

- 4 -

유기화학물에전류를흘릴때발광현상을디스플레이에적용

Light

투명 Substrate

Anode (ITO IZO)HIL HTL

EMLEIL ETLCathode

bull OLED (Organic Light Emitting Diode)유기화합물에전류를흘릴때발광하는소자

- 양극과음극에전압을가하면 전극으로부터전자와정공이주입되어전자와정공의재결합으로여기분자가

(Exciton) 생성되고 여기분자로부터표시를원하는빛을발산함

1 Introduction History of OLED

- 5 -

LTPS-TFT 242rdquo Full color OLED - 2003 Sony

LTPS-TFT 17rdquo Full color OLED - 2002 TMD

LTPS-TFT 155rdquo Full color OLED - 2003 SS SDI

a-Si TFT 20rdquo Full color OLED - 2003 CMO LTPS-TFT 201rdquo Full color OLED - 2004 LGPhilips LCD

a-Si TFT 21rdquo Full color OLED - 2004 Samsunga-Si TFT 40rdquo Full color OLED - 2005 Samsung

1 Introduction OLED의 분류

- 6 -

발광 재료 저분자(Small molecule)

고분자(Polymer)

발광 메카니즘 형광(Fluorescence)

인광(Phosphorescence)

발광 방향 Bottom Emission

Top Emission

Color 구현 방법 RGB LED

Blue EL + CCM 법

White EL + CF 법

구동 방식 Passive Matrix

Active Matrix

1 Introduction AMOLED vs TFT-LCD

- 7 -

AMOLEDAMOLEDTFT- LCDTFT- LCD

LC CF

BL

TFT

bull No backlight Thinner amp lighter

bull No LC Fast Response time

bull Less cell process Simple process

bull Wide viewing angle

bull High brightness

bull Better color purity

bull Easily applicable to flexible display

Polyimide

PolyimideLC

ITO CathodeOrganic ELTFTGlassPolarizer

Advantages of AMOLED

TFT

OLEDPolyLED

PolarizerGlassCF + BM

Encapsulation

TFT

PolarizerGlass

Back Light

1 Introduction Market Forecast

- 8 -

bull 2007년에 휴대폰 main display 시장은 AMLCD가 전체의 507를 차지할 것으로 예상되며 OLED가 탑재된휴대폰 main display는 5300 만개의 수요가 기대되는데 이는 전체 main display의 10에 해당하는 수준임

Mobile Phone Sub Display(년도별수요)

0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007

Mobile Phone Main Display (년도별수요)

대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)

Source DisplaySearch Q4 rsquo03 Quarterly mobile phone shipment and forecast report

1 Introduction Display Market

- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi

DesktopMonitorNote PC

Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED

1 Introduction OLED Product Roadmap

- 10 -


- 11 -

중대형 Display

소형Display

특수특수 용도용도

OLEDs 2003 by UDC

1 Introduction OLED Display History

- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled

1 Introduction Emission Mechanism

- 13 -

2 OLED amp PLED Materials Small molecular OLED

- 14 -

최초의 Small molecular OLED

Formation of organic film and cathode metal

Vacuum evaporation


- 15 -

Optical absorption and photoluminescence

bull I-V characteristics of the ITOTPDAlq3Al device

bull Absorption and PL emission spectra of Alq3

2 OLED amp PLED Materials Polymer LED

- 16 -

Polymer LED

JH Burroughes et al- Nature 347 539 (1990)

Glass

ITO

External circuit

Al or Ca

PPV

Formation of organic film

Spin coating Dip-coating Ink-jet

Formation of cathode metal

Vacuum evaporation


- 17 -

Optical absorption PL and EL of PLED

bull I-V and L-V characteristics of the ITOPPVPPVAl device bull Absorption PL and EL emission spectra of PPV

- 18 -

bull 고순도 (수명 휘도와 관련)

bull 진공증착 (가능)

bull 무정형 (소자 작동 시 발생하는 Joule열로 야기되는 결정화에 의한 소자의 파괴를 방지)

bull 높은 열 안정성 (유리전이온도Tg 열분해온도)

bull 우수한 계면 특성 (인접한 다른 층과의 높은 접착력 다른 층으로의 비이동성)

bull 적당한 HOMO LUMO 준위를 가질 것

OLED 재료의 요구특성

2 OLED amp PLED Materials

Emissive materials Small-molecular


- 19 -

Emissive materials Dye


- 20 -

Phosphorescent sensitizer

Emissive materials Polymer


- 21 -


Hole Transporting Materials

3 Device operation

- 22 -

(i) Quantum efficiency

(ii) Carrier injection and transport mechanism

(iii) Photonic effects

bull Internal quantum efficiency ηint = γrstq

bull γ is the ratio of number of excition formation events within device to number of electrons in external circuit

bull rst is fraction of excitions formed as singlets

bull q is efficiency of radiative decay of excitions

γ

rst

q

ηext

h+ - e- pair

SingletexcitonSingletSingletexcitonexciton

Triplet excitondirect deactivation

Triplet Triplet excitonexcitondirect deactivationdirect deactivation

EmissionEmissionEmission Thermaldeactivation

ThermalThermaldeactivationdeactivation

ExternalemissionExternalExternalemissionemission

Internaldissipation

InternalInternaldissipationdissipation

h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

h+ - e- pairh+ - e- pair







Internaldissipation


h+h+ e-e-

25 75

Basic processes

(i) injection of electron and hole

(ii) capture to form exciton

(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)

형광형 OLED(25)인광형 OLED(100)

Singlet(25)

Ground state

인광(저분자)형광(저분자 amp 고분자)

특성

당면과제

bull Fast decay time(lt1)bull내전류특성우수bull PM-OLED에적당

bull상대적으로낮은효율bull Green 수명향상

bull높은발광효율bull(이론적최대효율 100)bull AM-OLED에적당

bull Blue 수명 lt 1000시간bull Hole blocking layer가추가로필요하여구동전압 1~2V 상승

3 Device operation

- 26 -




bull LUMO Lowest Unoccupied Molecular Orbitalbull HOMO Highest Occupied Molecular Orbital

3 Device operation Injection of Charge

- 27 -

Injection dominated mechanisms thermionic and tunneling emission

Thermionic emission J Gmeiner et al Acta Polym 44 201 (1993)

Φ

Thermionic emission

Tunneling emission

Tunneling emission J Appl Phys 75 1656 (1994)

I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3

A Richardson constant m effective mass

In MEH-PPV devices F-N tunneling model applies at high fields and the barrier is determined by the metal work function and the energy levels of MEH-PPV (ID Parker J Appl Phys 75 1656 (1994))

3 Device operation

- 28 -

Conduction in organic semiconductor ohmic conduction and SCLC

Ohmic conduction

J = qn0microVd PWM Blom et al Appl Phys Lett 68 3308 (1996)

Space Charge Limited Current

JSCL = 98εsmicroeV2d3 no traps

RN Marks et al Synth Met 55 4128 (1996)PWM Blom et al Appl Phys Lett 68 3308 (1996)

JSCL ~ V(m+1)d(2m+1) exponential distribution of traps (m=TtT)

PE Burrows et al J Appl Phys 79 7991 (1996)

3 Device operation

- 29 -




Fraction of internally generated light that emerges in forward direction is approx 12n2 where n is the internal refractive index

External quantum efficiency ηext ~ 1(2n2)

OLED

glass

Forward emission

4 OLED Performance

- 30 -

Current balance is set by the size of the barriers at the two electrodesbull Lower voltage operationbull Higher efficiencybull Good thermal stabilitybull Longer life time

To improve device performanceTo improve device performance

Introduce HTL ETL HIL EILIntroduce HTL ETL HIL EIL ie) Heterostructure

HTL Hole transporting layerETL Electron transporting layerHIL Hole injecting layerEIL Electron injecting layer

Balancing of electron and hole currentsBalancing of electron and hole currents

4 OLED Performance

- 31 -

Schematic diagram of the EL emission process in a typical multilayer OLED

ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å

Cathode(low work function metal Ca AlLi MgAg etc)

Anode(Transperent electrodeITO IZO etc)

4 OLED Performance

- 32 -

4 OLED Performance Lifetime

- 33 -

수명의 정의 초기 휘도가 frac12로 될 때까지 걸리는 시간

가속수명

- 전류가속(휘도 가속) 강한 전류(고휘도)를 흘려주어 소자의

열화를 가속시켜 실제구동전류에서의 수명을

예측하는 방법 (수명 prop 1L0 L0 초기휘도)

- 온도가속 높은 온도를 가하여 소자의 열화를 가속

시켜 상온에서의 수명을 예측하는 방법

Log(T) = -a middot Log(I) + b (T 반감수명 I 전류밀도() a 가속계수)


- 34 -


- 35 -

5 OLED Display

- 36 -

디스플레이응용을위한 OLED 소자및공정요구조건들

bull OLED with high efficiency

- Device structure

- Material(Phosphorescent OLED)

- Processing

- Outcoupling향상

bull대면적고정세 full color 구현기술

bull소자신뢰성

-소자수명

-열적안정성

5 OLED Display What is pixel

- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G

(a) Stripe (b) Delta Triad (c) Quad

Cf) RGBW sub-pixel

5 OLED Display Color Mix

- 38 -

Color mix of sub-pixel

θ lt 003 mixed color

bull 150rdquo XGA 0297mm x 0099 (855 ppi)

bull 170rdquo SXGA 0264mm x 0088 (962 ppi)


bull 201rdquo UXGA 0255mm x 0085 (996 ppi)

ppi pixel per inch

5 OLED Display Color Generation

- 39 -

Number of Color White balance Control

of Color = 2n (R) x 2n (G) x 2n (B)n of video data bits

bull Dynamic range of RGB data - current voltage

bull RGB driving TFT size bull RGB emission timebull White OLED + color filter

bull 3 bit= 8-grayRGB = 512 colorsbull 4 bit= 16-grayRGB = 4096 colorsbull 6 bit= 64-grayRGB = 262144 colorsbull 8 bit = 256-grayRGB = 16777216 colors

색재현율

100

times=

면적삼각형좌표계의표준

면적삼각형좌표계의의색재현율

NTSCRGBDisplay

참고) LCD 경우- Note PC 45~65- Monitor 65~72- LCD-TV 72

5 OLED Display Driving Method of FPD

- 40 -

CRT E-beam scanning

FPD Electrical signal scanning

01~1 msec

Brightness

time

bull Passive matrix bull Active matrix

Brightness Brightness

timetime

- 41 -

5 OLED Display

(b) Color Filter(CF) 방식

(c) Color Change Media(CCM) 방식

White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM

구 성RGB 재료를

각각 Patterning

기술과제RGB 발광재료의미세 Patterning

청색 발광재료

색변환 효율

백색발광재료

광변환효율

ColorReproductionQuality

Approaches to Full Color OLED

청색유기 EL amp녹색형광색소적색형광색소청색 Color

Filter

백색유기 ELamp

Color Filter

5 OLED Display RGB OLED

- 42 -

Shadow mask 방식(저분자)bull Pattern 된얇은 Metal Mask (Shadow Mask)을이용하여 Pixel에유기물을증착하는방법

항목 Issues

Fine Metal Mask

- Mask 제작의 어려움 (두께 lt 50 폭hellip)- Mask 처짐

- Mask 세정 (Mask 세정방법 개발 필요)

설 비 - Mask와 기판의 정밀 Alignment (기판 및 Mask 처짐 방지기구)

- 복사열에 의한 Mask 팽창 (냉각기구 필요)

특성 - Mask제작의 한계로 인한 High Resolution어려움

- Mask에 붙어 있는 Particle(유기물Metal)에의한 Device 불량(Line 불량 Dark Spot)

Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -

Ink-Jet 방식bull 양극인 ITO위에 고분자 유기물 방울로 떨어트려 발광층을 형성하는 방법bull Ink- Jet Printing에적합한 Polymer의개발bull Ink- Jet Print Process의정확성및재현성확보

ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator

Conducting polymer (PFDTPSS)

Bank 형성

Red emitterRhodamine 101PPV)

Ink-jetGreen emitter (PPV)

Blue emitter (Poly(dialkylfluorene))

Cathode 증착


- 44 -

bull Laser를이용하여고분자유기물 Coating된 Donor Film 위에 Coating된저분자또는고분자유기물을 Pixel에형성하는방법-저분자 Evaporated onto the LITI Donor Film-고분자 Blending onto the LITI Donor Film

Laser Induced Thermal Imaging (LITI) 방식

Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating

Cathode(Evaporation)

LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion

LITI Process(RGB 3 times)

LTHC Light-To-Heat Conversion Layer LEP Light Emitting Polymer

5 OLED Display

- 45 -

Passive matrix

Digital driving method- Time ratio gray scale method - Area ratio gray scale method

Analog driving method- Simple pixel circuit(Two TFT + 1 Capacitor)- Compensation pixel circuit

Active matrix

OLED Displays

아이콘 형

5 OLED Display PMOLED vs AMOLED

- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT

bull Matrix 전극사이에 EL device

Line 선택구간만 Emission

Passive Matrix (PM) Active Matrix (AM)

bull Matrix 전극사이에 EL 구동 TFT

Frame time 동안 Emission 가능

1)

1) TFT Thin Film Transistor

5 OLED Display PMOLED

- 47 -

Glass

ITO Inter Insulator

Organic layerCathode

Cathode separatorInter insulator

ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann

Data1 Data2 Data3 Datam

A Arsquo


- 48 -

PMOLED 구동bull Scan Line이순차적으로선택될때 Data Line의신호에따라선택된 Pixel이순간적으로발광하는방식

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4

5 OLED Display PMOLED Layout

- 49 -

Metalmiddotmiddotmiddot

MetalITO

middotmiddotmiddot middotmiddotmiddot

Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1

5 OLED Display PMOLED Process

- 50 -

(1) Metal amp ITO patterning (2) Inter-insulator 형성

bull ITO glass Cleaningbull Metal(Mo Cr) Sputtering

(투명전극저항보완)

bull Metal amp ITO patterning Mask 1bull Metal patterning Mask 2

bull Insulator layer formation MASK 3(ITO edge에서전기장집중으로소자 breakdown 방지)

- Photosensitive polymer


- 51 -

(3) Cathode Separator 형성 (4) 유기박막증착

bull Pretreatment- Plasma treatment ITO Work function 향상- UV cleaning

bull 유기물증착(Shadow mask 이용한진공증착)

bull Cathode separator 형성 Mask 4 (각 pixel들의 cathode line에의한 short 방지를위해형성)

Reverse Taper angle 필요( Negative PR 사용이적합)


- 52 -

(5) 금속전극(Cathode) 증착 (6) UV를이용한소자봉지공정

Out Going InspecCOF BondPol Lamin Probe TestCell CutAging

COF Film


COF FilmCOF Film

(7) Aging Scribing 검사및 Module 공정

5 OLED Display PMOLED Grayscale

- 53 -

Grayscale methods

1datai 2datai 3datai tandai

bullPulse-Amplitude modulation(PAM)- Current level control- Multiple Current sources- Matching problem

bullPulse-Width Modulation(PWM)- ONOFF timing control- Only One current source

CCV


- 54 -

AMOLED 및 PMOLED 구동방식(가정 Resolution =gt 640 x 480 Luminance =gt100cdm2)

100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간

bull1 Frame Time 167 ms( 60Hz )bull1 line scan time 32 us( 525 line in 1 frame )bullDuty Driving에필요한휘도 = 100 x 167m 32u ≒ 52500 cdm2

5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]

AM Operation PM Operation

PMOLED vs AMOLED

효율사용영역

5 OLED Display PMOLED Power dissipation

- 56 -

In a poly-LED display there are three sources of power dissipation

1 Light productionPlight = ILED times VLED

2 Capacitive lossesPcap = C times Vswing times Vsupply times freq

3 Resistive lossesPres = I2 times R

Power Dissipation in poly-LED Displays with Increasing Size and Resolution

Resolutioncolumnrow

80 times 60160 times 120320 times 240640 times 480

Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103

(Pixel 300times300 um luminance 100 cdm2 efficiency 15 cdA green poly-LED)

5 OLED Display AMOLED

- 57 -

TFT-LCD 패널bull 전압구동방식bull화소내 TFT switching

AMOLED 패널bull 전류구동방식bull화소내 TFTs switching + current driving

Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line

Data line Pixel array

SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED

5 OLED Display AMOLED Process

- 58 -

INPUTINPUTTFT for AMTFT for AM

Evaporation

Seal Dispensing Canister CleanGetter Input


Encapsulation

Evaporation

Back End

Sealing

UV Expose

EvaporationMetal Source RGB Source

COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -

AMOLED 구동bull Scan Line이 순차적으로 선택될 때 Data Line의 신호에 따라 선택된 Pixel이다른 신호(다음 Frame)가 입력될 때까지 계속 발광하는 방식

t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -

TFT(Thin Film Transistor)의기본구조들

Gate

Source Drain

G

S D

TFT의종류 CdSe TFT Organic TFT a-Si TFT Poly-Si TFT 등등

5 OLED Display Silicon

- 61 -

Semiconductor layer

bull Single Crystalline Silicon bull Polycrystalline Silicon bull amorphous Silicon

Grain boundaryGrain

결정특성Long range orderEg = 11 eVNo defect

CMOSHigh mobility=gt ~ 600Low leakage

소자특성

Long range orderEg = 11 eVGrain boundary

No long range orderLarge bandgapMany Trap states

CMOSMedium mobility=gt 수십 ~ 수백High off current

NMOS Low mobility=gt 05 ~ 1High photo current

5 OLED Display a-SiH

- 62 -

a-SiH formation

bull SiH4 + H2 amorphous Si deposition

Gas phase transport

Migration amp chemical reaction

Surface desorption of byproduct(Exhaust)

Plasma

Deposition film

Substrate

Electron drift mobility 1 cm2VsHole drift mobility 0003 cm2VsOptical band gap 15~18 eV300K conductivity 10-11Ωcm n+ a-Si conductivity 10-2 ΩcmH content 10 at

5 OLED Display a-SiH TFT

- 63 -

a-SiH TFT 제조공정

GATE 전극 DATA 전극 보호막 화소전극 Bank 층형성절연막 반도체막유리판

증착 패턴공정(Deposition amp Patterning Process) ndash Photo Lithography

Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)

PR 도포(PR Coating)

노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)

습식 식각(Wet Etch)

건식 식각(Dry Etch)

FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -

a-SiH TFT의 I-V 특성

Transfer curve Output curve


- 65 -

a-SiH TFT Stability SNU (SID 2005)

5 OLED Display Poly-Si TFT

- 66 -

Poly-Si formation

Solid Phase Crystallization (SPC) base

bull Pure SPC

- High Temperature SPC

- Low Temperature SPC

bull Metal induced Crystallization ( MILC )

- Metal Induced Lateral Crystallization ( MILC )

- Continuous Grain Silicon (CGS)

- Field Enhanced Metal Induced Crystallization (FEMIC)

bull Alternating Magnetic Field Crystallization (AMFC)

Laser base

bull Excimer Laser Annealing (ELA)

bull Sequential Lateral Solidication (SLS)

5 OLED Display LTPS TFT

- 67 -

Excimer laser crystallization

Overlapped pulse scanning

ScanningDistanceper Pulse(Ls)

Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]

Laser Energy Density [mJcm2]E0 E0+10 E0+20

1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region

Overlap 90 (10 Shot)




E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots

Multiple shot effect



- 69 -

LTPS TFT ProcessBuffer SiO2 depo

a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping

p-type dopingBank Patterning

Bank layer depo

n-type TFTp-type TFT

Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -

I-V characteristics of LTPS TFTs

-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)

Mobility 68 cm2VsecIoff 016 pAum


Transfer curve


- 71 -

Uniformity of LTPS TFTs

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m

5 OLED Display TFT Hysteresis

- 72 -

a-Si TFT Hysteresis SNU (SID 2005)


- 73 -

LTPS TFT Hysteresis POSTECH amp LPL (JJAP 43 p L482 (2004)

10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]

TFT WL=820 [micrommicrom] forward gate voltage sweep reverse gate voltage sweep

I ds [A

]

Vgs [V]


- 74 -

Two TFT and One capacitor pixel structure

Saturation region operation

Device-to-device variation on panel

Brightness uniformity on panel

Run-to-run variation

Panel-to-to panel brightness uniformity

VDD IR drop problem

TFT hysteresis Image Sticking

2)(2 thpSGpoxDSsatOLED VVL

WCII minus== microdata Line

Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD

VOLED lt Chess pattern gt

VGS

І Vds ІVTFT ltMiddle graygt


- 75 -

Voltage distribution of VDD line POSTECH amp KIT (ITC 2005)

ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]

lt Voltage distribution for full white gt

RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B

lt Voltage distribution for test chess patterngt


- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -

Poly-Si TFT AMOLEDbull Non-uniformity of electrical characteristics in driving TFTs

ndash Mobility subthreshold swing threshold voltageLuminance non-uniformity

a-Si TFT AMOLED

bull Low cost flexible displays

ndash Well-established large manufacturing base for AMLCD displays

bull Poor mobility and reliability

ndash Large-sized driving TFT

ndash High operation voltage power consumption increase

ndash Stress-induced threshold voltage shift

Luminance non-uniformity amp degradation

5 OLED Display AMOLED Driving Methods

- 78 -

bull 전압 피드백

bull 전류 피드백

bull 광 피드백

bull 전압 및 전류 기입

Digital DrivingDigital Driving

Conventional Voltageprogrammed

Compensation CircuitCompensation Circuit

Analog DrivingAnalog Driving

AMOLED DrivingAMOLED Driving

bull 구동 TFT 직접 보상

bull 구동 TFT 이웃하는

TFT로 보상

1) Area ratio gray scale method2) Time ratio gray scale method

Hybrid Driving Feedback Driving

Voltage Programmed Current Programmed ARG1 TRG2



TFT로 보상

5 OLED Display Digital Driving Methods

- 79 -

Area ratio gray scale method (ARG)

bull 2m gray scales can be acquired

bull m=2 the areas of the sub-pixels are 1 2

bull Four gray scales are acquired


- 80 -

ARG amp TRG

bull The frame time is divided into plural sub-frames

bull 2m middot n gray scales can be acquired

bull m=n=2 the time of the sub-frames are 1 4

bull 16 gray scales are acquired


- 81 -

bull Similar to PDP driving methodbull TU has no contribution to light emissionbull Cathode voltage variation requiredbull TLn have the ratio of 12481632 in length

ltPixel circuitgt

ltCircuit diagramgt

SF1 SF2 SF3TU1 TL1 TU3 TL3

OFF ON

ltTiming diagram of DPS driving methodgt

SEL (SID 2000) Display Period Separated (DPS) Driving

Gate 1

Gate 2

Gate NEL_cathode


- 82 -

SEL (SID 2000) Simultaneously Erased Scan (SES) Driving

bull Good uniformity

bull Difficult to embody the driver system

ndash Frame memory is needed

bull The degradation of image quality is more serious than analog driving method

ltTiming diagram gt

ltPixel circuitgt


- 83 -

Hitachi (SID 2002) Clamped Inverter Driving

bull SID 2003 bull SID 2004 bull SID 2004

ltPixel circuitgt ltTiming diagram gt


- 84 -

Ryukoku (IDW 2004) TRG + Current uniformization



- 85 -

SEL amp Pioneer (SID 2004) - Resolve Luminance variation depending on ambient temperature amp

degradation of OLED

ltPixel circuitgt ltOLED Luminance gt

5 OLED Display Voltage Programmed Driving Methods

- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=

minusminusminussdotsdot=

minussdotsdot=

there4 If Vth_T3=Vth_T2

ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt

bull Compensation Vth (o) mobility (x) VDD (x)bull Mismatch problem between T2 and T3bull Low contrast ratio

Emission control SW between OLED amp T2 (IDW 2002)


- 87 -

Hanyang Univ amp SS SDI (Euro-display 2002)

( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt

Compensation Vth (o) mobility (x) VDD (x)Mismatch problem between T3 and T4Low contrast ratio (CR)


- 88 -

SS SDI (SID 2003)

ltPixel circuitgt

Hanyang Univ (IMID 2003)

VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt

Improve contrast ratio (CR)


- 89 -

Sarnoff Corp (IEDM 1998)

ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED

Compensation Vth (o) mobility (x) VDD (o)


- 90 -

SS SDI amp Hanyang Univ (IDW 2003)

12

ltTiming diagram gt

th_M1dataSG_M1 VV +minus= VVDD

2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

bull Compensation Vth (o) mobility (x) VDD (x)


- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -

Hanyang Univ amp SS SDI (SID 2004)

th_T1DDdataCST VV-V +=V

+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=

bull Compensation Vth (o) mobility (x) VDD (o)

ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line

(1) Initialization VG_T1 = GND(2) Compensation VC1 = Vth_T1

(3) Data input VG_T1 = Vdata +Vth_T1

Vcomp

ltPixel circuitgt

ltTiming diagram gt

bull Compensation Vth (o) mobility (x) Vc (X)


- 94 -

SSE (SID 2005)

TNO

+-


(1) Initialization VC1=VDD (when Vref = 0 V)(2) Compensation VC1= VTO_OLED +Vth

(3) Data input VG_DTFT = Vdata +VTO_OLED +Vth

bull Compensation Vth (o) mobility (x) GND (x)bull Low contrast ratio

5 OLED Display Current Programmed Driving Methods

- 95 -

Sarnoff Corp (IEDM 1998) Toshiba (SID 2003)

ltPixel circuitgt ltPixel circuitgt

bull Compensation Vth (o) mobility (o) VDD (o)bull Difficult to display low gray level

2

21 )V( I th Data minus= SGVK

KIV Data

SG 2+= thVltTiming diagram gt

1 Programming Period 2 Driving Period

Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -

Sony (SID 2001) Current mirror type


bull Compensation Vth (o) mobility (o) VDD (o)bull WL of T4 is larger than that of T2

rArr Reduce settling time bull Mismatch problem between T2 and T4


- 97 -

SNU (IDW 2002) Current scaling type


bull Compensation Vth (o) mobility (o) VDD (o)bull Current scaling type



- 98 -

Hanyang Univ amp SS SDI (IDW 2002)

ltTiming diagram gt ltPixel circuitgt

bull Compensation Vth (o) mobility (x) VDD (o)bull Capacitive coupling of C2

rArr Solve settling problem


- 99 -

Michigan Univ amp Kyushu Univ (IEEE2001)

Waterloo Univ (Eurodisplay 2002)


5 OLED Display Feedback Driving Methods

- 100 -


ltTiming diagram gt

ltPixel circuitgt ltOperation Algorithmgt

ltSimulation resultgt


- 101 -

Waterloo Univ amp Ignis (SID 2005)




- 102 -

Philips

bull SID 2002 bull SID 2004


5 OLED Display Hybrid Driving Methods

- 103 -

Hanyang Univ (AMLCD 2005)

ltData drivergt ltPixel circuitgt ltTiming diagram gt


- 104 -

Ignis (SID 2005)

ltOperation Algorithmgt

ltSchematic diagramgt

ltPixel circuitgt

5 OLED Display Emission Type

- 105 -

Bottom Emission OLED Top Emission OLED

Metal Anode

Semi-transparent Cathode

Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light

Metal Cathode Transparent Anode

Emissive Layer

Pixel 구동회로부

- 106 -

Shift Register

Sampling Latch

Holding Latch

Voltage or Current DAC

Output Buffer

ReferenceVoltage or Current

Integrated data driving circuitbull Voltage mode

- Accurate output buffer

bull Current mode- Accurate current DAC

Control nano-level currentDevicersquos non-uniformities

- Accurate current SH circuit design- Accurate pre-charge circuit design- gamma correction

Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs

5 OLED Display Integrated Data Driving circuits

- 107 -

SS SDI (IDW 2004) External D-IC + analog sampling

ltSchematic diagram of data driving circuitgt


- 108 -

SS SDI (SID 2005) RGB adjustable gamma compensation


ltgamma compensation circuitgt

bull 6-bit DAC 3-bit decoder and voltage selector+ 3-bit decoder and resister ladder


- 109 -

SS SDI amp Hanyang Univ (IDW 2004) External D-IC + DeMux

ltSchematic diagramgt lt13 Current DeMuxgt

ltCurrent sample and hold circuitgt


- 110 -

AU (IDW 2004)

ltSchematic diagramgt ltCurrent DACgt

ltData driving circuitgt ltCurrent SH circuitgt


- 111 -

AU (SID 2004)


ltPixelgt

ltData driving circuitgt

ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)


ltPre-charge circuitgt

ltPixelgt ltTiming diagramgt


- 113 -

NEC (Eurodisplay 2002)


lt1 bit DCCgt

ltDAC block diagramgt

ltTiming diagramgt


- 114 -

AU (IDW 2003)

ltData driver diagramgt

lt6-bit DACgt

ltSH circuitgt ltPre-charging circuitgt

5 OLED Display AMOLED Product

- 115 -

Digital Still Camera ( Kodak Easyshare LS633 2003 5 )

bull 216 inch 521 x 218bull Dot pitch 0084 x 0151 mm2

bull Color arrangement RGB delta bull Gate driver integrationbull Analog sampling data driver integration

5 OLED Display PHOLED Product

- 116 -

Sub-Display of Mobile Phone ( Fujitsu F5005iGPS 2004 4)

bull 11 inch 96 x 72

bull Pioneer PM-PHOLED

bull 4096 color

bull Phosphorescent developed by UDC


- 117 -

PDA ( Sony Clie PEG-VZ90 2004 9 )

bull 38 inch 480 x 320bull Top emissionbull Contrast ratio 1000 1bull Viewing angle 180degbull Response time 1 us

슬라이드식 조작 패널

5 OLED Display AMOLED Development

- 118 -

SS SDI (SID 2005)- LTPS TFT - 26rdquo 480 x 640 (302ppi)- LITI (Laser-induced thermal imaging)

- Top emission-200 cdm2

LPL ndash LGE (2004)- LTPS TFT - 201rdquo 1280 x 800- Small Molecule- gt 1000 cdm2

SSE (2005)- a-Si TFT- 40rdquo 1280 x 800- White OLED + Color filter- 600 cdm2

- Color Purity 80

6 Summary

- 119 -

OLED performance is rapidly improvingbull Lifetimebull Efficiency amp power consumptionbull Color purity

Innovation is neededbull OLED performance amp fabrication processes

bull Brightness uniformity

ndash Global uniformity IR drop of power lines

ndash Local uniformity Electrical characteristics of Driving TFT (Poly-Si TFT)

bull Reliability

ndash OLED device lifetime thermal reliability

ndash Driving TFT degradation (a-SiH TFT)

In the near futureOLED display will be widely used and the most attractive display of FPD

1 Introduction Display 분류

- 2 -

Electronic information displays

Projection Direct-view Off-screenDMDTMA

Light valveLCOS

Flat-panel

Shadowmask

Beamindex

Mono-chrome

Emitter

Nonemitter

Luminescence Incandescence

CL (Flat CRT)

Liquid-crystal Electro-chromic

Electro-phoretic

Ferro-electric

Activematrix

Passivematrix

Plasmaaddressed TFT MOS MIN Diodeothers TN STN FLC others

EL LED Gas discharge (PDP)

OrganicInorganic

Non-coherentdisplays

Coherentholograms

CRTCRT

FED VFD AC DC

Polymer Small Molecule

1 Introduction

- 3 -






(Electron)CRT FED

i

V

p n



- 4 -


Light

투명 Substrate


EMLEIL ETLCathode





- 5 -







- 6 -


고분자(Polymer)




Top Emission


Blue EL + CCM 법

White EL + CF 법


Active Matrix


- 7 -


LC CF

BL

TFT








Polyimide

PolyimideLC



TFT

OLEDPolyLED


Encapsulation

TFT

PolarizerGlass

Back Light


- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




1 Introduction

- 3 -






(Electron)CRT FED

i

V

p n



- 4 -


Light

투명 Substrate


EMLEIL ETLCathode





- 5 -







- 6 -


고분자(Polymer)




Top Emission


Blue EL + CCM 법

White EL + CF 법


Active Matrix


- 7 -


LC CF

BL

TFT








Polyimide

PolyimideLC



TFT

OLEDPolyLED


Encapsulation

TFT

PolarizerGlass

Back Light


- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 4 -


Light

투명 Substrate


EMLEIL ETLCathode





- 5 -







- 6 -


고분자(Polymer)




Top Emission


Blue EL + CCM 법

White EL + CF 법


Active Matrix


- 7 -


LC CF

BL

TFT








Polyimide

PolyimideLC



TFT

OLEDPolyLED


Encapsulation

TFT

PolarizerGlass

Back Light


- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 5 -







- 6 -


고분자(Polymer)




Top Emission


Blue EL + CCM 법

White EL + CF 법


Active Matrix


- 7 -


LC CF

BL

TFT








Polyimide

PolyimideLC



TFT

OLEDPolyLED


Encapsulation

TFT

PolarizerGlass

Back Light


- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 6 -


고분자(Polymer)




Top Emission


Blue EL + CCM 법

White EL + CF 법


Active Matrix


- 7 -


LC CF

BL

TFT








Polyimide

PolyimideLC



TFT

OLEDPolyLED


Encapsulation

TFT

PolarizerGlass

Back Light


- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 7 -


LC CF

BL

TFT








Polyimide

PolyimideLC



TFT

OLEDPolyLED


Encapsulation

TFT

PolarizerGlass

Back Light


- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 8 -



0

200000

400000

600000

MSTN 179554 132761 115590 110917

CSTN 160027 170368 128770 100852

AMLCD 153524 194789 239895 272791

OLED 2266 10990 41120 53495

2004 2005 2006 2007


대수( x 1000개)

0

50000

100000

150000

200000

MSTN 50251 47442 22282 17059

CSTN 34562 52706 34329 21562

AMLCD 30537 45217 59154 62002

OLED 18115 20780 22720 24152

2004 2005 2006 2007대수( x 1000개)



- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 9 -

10 40

VGA

Size (Inch)

20 30

SVGA

XGA

UXGA

Digital HD TV

QVGA

SXGA

QXGA

D-Paper

IMT2000

PDA

Car Navi


Monitor

EWS

FPD PRT TV

TVMonitor

Resolution

50 60

CRT TV

Monitor Zone

TV ZoneMobile Zone

TFT

AMOLED


- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 10 -


- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 11 -

중대형 Display

소형Display


OLEDs 2003 by UDC


- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 12 -

Sony 38rdquo

2004

LPL 201rdquo

SS 21rdquo

Epson 40rdquo Tiled


- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 13 -


- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 14 -



Vacuum evaporation


- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 15 -





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 16 -

Polymer LED


Glass

ITO

External circuit

Al or Ca

PPV




Vacuum evaporation


- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 17 -



- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




- 18 -











- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 19 -



- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 20 -




- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 21 -



3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 22 -








γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-

25 75

γ

rst

q

ηext

h+ - e- pair







Internaldissipation


h+ e-








Internaldissipation


h+h+ e-e-

25 75

Basic processes



(iii) emission

3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 23 -

3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 24 -

3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 25 -

Excited State

Triplet(75)


Singlet(25)

Ground state


특성

당면과제





3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 26 -






- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 27 -



Φ

Thermionic emission

Tunneling emission


I prop F2exp(-κF)

κ = 8π(2m)12ϕ32(3qh)-12

MetalPPV

J = AT2exp(-φbkT)

A = 4πqk2mh3



3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 28 -


Ohmic conduction







3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




3 Device operation

- 29 -






OLED

glass

Forward emission

4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




4 OLED Performance

- 30 -






4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




4 OLED Performance

- 31 -


ITO

HIL

HTL

ETL

EIL

EML

Metal

Exciton

1000 ~ 1500 Å



4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




4 OLED Performance

- 32 -


- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 33 -


가속수명








- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 34 -


- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 35 -

5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




5 OLED Display

- 36 -



- Device structure


- Processing

- Outcoupling향상


bull소자신뢰성

-소자수명

-열적안정성


- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 37 -

Sub-pixel

Pixel

R G B

R G

BGR G B

RG

BR B

G


Cf) RGBW sub-pixel


- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 38 -







ppi pixel per inch


- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 39 -






색재현율

100

times=



NTSCRGBDisplay



- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 40 -

CRT E-beam scanning


01~1 msec

Brightness

time



timetime

- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




- 41 -

5 OLED Display



White OLED

Blue OLED

(a) RGB 방식

발광효율

RGB CF구 분 CCM


각각 Patterning


청색 발광재료

색변환 효율

백색발광재료

광변환효율




Filter

백색유기 ELamp

Color Filter


- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 42 -


항목 Issues

Fine Metal Mask







Source

Substrate

Shadow Mask

Source

Substrate

bull 10-7 Torr

Shadow Mask


- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 43 -


ITOPassivation

TR Units

Glass Substrate

Bank Channel

Insulator


Bank 형성




Cathode 증착


- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 44 -



Substratewith

Anode

HTL (Spin Coating)

Laser

Donor Film

LEPCoating


LITI PLEDDevice

Encapsulation

NdYAGLASER Beam

Substrate

Donor Film

LTHCLEP

adhesioncohesion

adhesion



5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




5 OLED Display

- 45 -

Passive matrix



Active matrix

OLED Displays

아이콘 형


- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 46 -

Cathode

Organicfilm

AnodeGlasssubstrate

Glasssubstrate

TFT






1)



- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 47 -

Glass

ITO Inter Insulator



ITOGlass

AArsquo

Cathode

Anode(ITO)

Glass

Scan1

Scan2

Scan3

Scann


A Arsquo


- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 48 -


Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

t1 t2 t3 t4 t5

Data 5

Data 6

Data

1 2 3 4 5 6

Scan

1

2

3

4


- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 49 -


MetalITO


Inter-Insul Cathode

Separator

Mask 4Mask 3

Mask 2Mask 1


- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 50 -








- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 51 -







- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 52 -



COF Film


COF FilmCOF Film



- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 53 -

Grayscale methods




CCV


- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 54 -


100cdm2

52500cdm2

167ms32us

AM

~~~~ ~~ ~~

PM

휘도

시간


5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




5 OLED Display

- 55 -

0 5000 10000 15000 20000 25000 300007

8

9

10

11

12

Luminescence [cdm2]

Effic

ienc

y [c

dA

]

0

2

4

6

8

10

Voltage [V]


PMOLED vs AMOLED

효율사용영역


- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 56 -






Resolutioncolumnrow


Diagonal(in)12245

10

Plight(mW)

15804002000

Pcap(mW)

1011013001800

Pres(mW)

1103008000

Ptotal(mW)

262002000

28000

Efficacy(lmW)

53281103



- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 57 -



Pixel array

LCCst

Storage line

Gate line

Data line

Data

Gat

e

VDDGate line


SW

DRV_TFT

Cst

OLED

GND

Data

Gat

e

TFT-LCD AMOLED


- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 58 -


Evaporation



Encapsulation

Evaporation

Back End

Sealing

UV Expose


COF Film

Pre Treatment


Evaporation



Encapsulation

Evaporation

Back EndBack End

Sealing

UV Expose

Sealing

UV Expose


COF FilmCOF Film

Pre Treatment


- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 59 -


t1 t2 t3 t4 t5

Data

1 2 3 4 5 6

Scan

1

2

3

4

Scan 1

Scan 2

Scan 3

Scan 4

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6


- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 60 -


Gate

Source Drain

G

S D



- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 61 -

Semiconductor layer


Grain boundaryGrain



소자특성






- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 62 -

a-SiH formation


Gas phase transport



Plasma

Deposition film

Substrate



- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 63 -




Patterning

세정(Cleaning)

SUBSTRATE

Al

DCAlAlAl

Al

Ar+

Al

Ar+

TARGET

SPUTTER

R F

HSi SiNSi N

HSiH

HHN

N

H H

HHH

PECVD

증 착(Deposition)


노광(Exposure)

현상(Develop)

PR 박리(PR Strip)

검사(Inspection)



FOSi

SiF4

Si

PLASMA

Gas RF

식각(Etch)


- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 64 -




- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 65 -



- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 66 -

Poly-Si formation


bull Pure SPC








Laser base




- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 67 -




Laser BeamWidth(Lw)

Lase

r Bea

m L

engt

h

OverlappingRate

= 100 X (Lw-Ls)Lw

Avr

g G

rain

Siz

e[A

]


1000

2000

3000

4000

5000

6000

7000

8000

Non-Uniform Grain

Region





E0+30 E0+40 E0+50 E0+60


- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 68 -

1 Shot 5 Shots

10 Shots 20 Shots




- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 69 -


a-SiH depo

Dehydrogenation

Laser annealing

Active patterning

Gate SiO2 depo

Gate metal depo

Gate patterning

Annealing

LDD doping

Interlayer SiO2

Contact hole open

Passivation depo

ITO Patterning

ITO depo

SD metal depo

SD Patterning

Passi hole open

Storage doping

n-type doping


Bank layer depo


Buffer SiO2

Source

Passi-SiNx

INT-SiO2Drain

P-Si

Gate

Drain Source

ITO

P-Si

Bank layer

Gate

Storagecapacitor


- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 70 -


-20 -15 -10 -5 0 5 10 15 20 251E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

001

Dra

in C

urre

nt(A

)

Gate Voltage (V)

-20 -15 -10 -5 0 5 10 15

Gate Voltage (V)



Transfer curve


- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 71 -


Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

Vth [V]

-25

-225

-2

-175

-15

-125

-1

1 4 7 10 13 16 19 22 25 28

Vth

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 4 7 10 13 16 19 22 25 28

ufl_m

ufl_m [cm2Vs]

50

55

60

65

70

75

80

85

90

1 3 5 7 9 11 13 15 17 19 21 23 25 27

ufl_m


- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 72 -



- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 73 -


10 5 0 -5 -10 -151E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

Vds = -01V

Vds = -10 V

∆Vth = 06 [V]


I ds [A

]

Vgs [V]


- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 74 -







VDD IR drop problem




Gate Line

SW_TFTDRV_TFT

Cst

OLED

GND

VDD

Ids

VDD


VGS



- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 75 -


ColumnRow ColumnRow

VD

D [V

]

ColumnRow ColumnRow

VD

D [V

]


RP

RPV

RHIPIXEL

VDD 1

VDDN

VDD2

IPIXEL

IPIXEL

IPIXEL

IPIXEL IPIXEL

RH

RH

RH

RH RH

RP

RPV

RPV

RP

lt VDD structure gt

A

Arsquo

B

Brsquo

Row Column

A

Arsquo

B

Brsquo

A

Arsquo

B

Brsquo

Row Column

VD

D [V

]

150 300 450 60013

135

14

145

15

VD

D [V

]

A-AB-B



- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 76 -


R P

`

IPIXEL

RH

RV

RPV

VDD1

VDDN

VDD2

R P

R P

RPV

RPV

RPV

RPV

RPVRV

IPIXEL

IPIXEL

RH

RH

RH RH

RVRV

RV

RHRH

IPIXEL

IPIXEL IPIXEL

R P

R P

R P

RV RV RV

RH

RVRVRV

VDDN

DDV1

DDV1

DDV2

DDV2

VDDM

DDV1

DDV2

VDDM

R P R P R P

R P R P R P

RPH RPH RPH

RPH RPH RPH

lt VDD structure gt

ColumnRow

VD

D[V

]

ColumnRow

VD

D[V

]


Row Column

A

Arsquo

B

Brsquo

VD

D [V

]

Row Column

A

Arsquo

A

Arsquo

B

Brsquo

B

Brsquo

VD

D [V

]

150 300 450 60013

135

14

145

15

A-AB-B



- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 77 -



a-Si TFT AMOLED









- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 78 -



bull 광 피드백









TFT로 보상






TFT로 보상


- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 79 -






- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 80 -

ARG amp TRG






- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 81 -


ltPixel circuitgt

ltCircuit diagramgt


OFF ON



Gate 1

Gate 2

Gate NEL_cathode


- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 82 -






ltTiming diagram gt

ltPixel circuitgt


- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 83 -





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 84 -




- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 85 -


degradation of OLED



- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 86 -

2

223

222

21

21

21

)(

)])([

)_(

__

_

dataDD

TthTthdataDD

TthTGSD

VVk

VVVVk

VVkI

minussdotsdot=


minussdotsdot=


ResetStoring Data

VDD

C1

T2

T4

T3

T1Vdata

Select

OLED

GND

A

B

SNU (SID 2002)

ltPixel circuitgt

ltTiming diagram gt




- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 87 -


( ) ( )22

21

21

dataSGOLED VVDDKVKI

VI

minus=minus=

=

ltlt=

th_T4

th_T3dataG

th_T3dataG

V

V-VV2

V-VV1


1

2

ltTiming diagram gt

ltPixel circuitgt



- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 88 -

SS SDI (SID 2003)

ltPixel circuitgt


VDDData Line

Select [n]

Select [n-1]

C1T1

T2

T4T3

em [n]

T5

ltPixel circuitgt

ltTiming diagram gt

em[n]

II IIIISelect [n-1]

Select [n]

ltTiming diagram gt



- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 89 -


ltPixel circuitgt

∆Vdata

1 2 3

ltTiming diagram gt

( )2

2

21

21

⎟⎠⎞

⎜⎝⎛

+times∆

=minus=

+times∆

=

=

ltlt

C2C1C1VV

C2C1C1V-V-VDDV3

V-VDDV2

V-VDDV1

datath

datathG

thG

thG

KVKI SGOLED



- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 90 -


12

ltTiming diagram gt


2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt



- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 91 -



2

21

2121

)(

)V( I th_M1_ OLED

dataDD

MSG

VVK

VK

minus=

minus=

ltPixel circuitgt

ltTiming diagram gt



- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 92 -



+ -

1 Scan ON

2 Scan OFF

th_T1SUSdata

_SG_T1

VV-

V

+=

minus=

V

VV TGDD 1

2

21

2121

)(

)V( I th_T1_ OLED

SUSdata

TSG

VVK

VK

minus=

minus=


ltPixel circuitgt

ltTiming diagram gt

1TthDDdataSUS VVVV

V

_

CSTSUSG_T1 V-V

minus+minus=

=


- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 93 -

KAIST (IDW 2001)

VD

VC

Data line

Select2 Select1

Select1

C1C2T1

T2

T3T4OLED

(1) (2) (3)

Select1

Select2

Data line



Vcomp

ltPixel circuitgt

ltTiming diagram gt



- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 94 -

SSE (SID 2005)

TNO

+-






- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 95 -




2


KIV Data



Data

SG

I

VK

=

minus= 2

21 )V( I th OLED


- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 96 -






- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 97 -






- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 98 -






- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 99 -





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 100 -


ltTiming diagram gt




- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 101 -





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 102 -

Philips




- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 103 -




- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 104 -

Ignis (SID 2005)



ltPixel circuitgt


- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 105 -


Metal Anode


Transparent Plate

Light Buffer Layer

Emissive Layer

Al Wiring Light


Emissive Layer


- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




- 106 -

Shift Register

Sampling Latch

Holding Latch


Output Buffer







Data Driver IC

Data driver IC

5 OLED Display

HSYNCHCLK

RGB data

LOAD

Channel Outputs


- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 107 -




- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 108 -






- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 109 -





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 110 -

AU (IDW 2004)




- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 111 -

AU (SID 2004)


ltPixelgt


ltLAAT SH circuitgt

5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




5 OLED Display

- 112 -

NEC (IDW 2002)





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 113 -



lt1 bit DCCgt


ltTiming diagramgt


- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 114 -

AU (IDW 2003)


lt6-bit DACgt



- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 115 -





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 116 -




bull 4096 color



- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 117 -





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability





- 118 -





- Color Purity 80

6 Summary

- 119 -






bull Reliability




6 Summary

- 119 -






bull Reliability




Documents

Oled Display Training