pdfeetejulaug2013

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July/August 2013

Report: MulticoreChallenge Conference

Special Focus:Flexible Electronics

europeanusiness press www.electronics-eetimes.com

Smart grids and IoT convergenceturns more data into cash

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ON ORDERSOVER 65!

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DESIGN & PRODUCTS

SPECIAL FOCUS:

- EDA & DESIGN TOOLS

Version control in EDA for

optimum hardware design

Timing closure highlights the

challenges of 45nm silicon

design and below

Modeling skew requirements

for interfacing protocol signals

in an SoC

- FLEXIBLE ELECTRONICS

Predictive modeling approach boosts

the development of thin-film organic electronics

Imec (Belgium), University ofBologna (Italy) and University ofMons (Belgium) have developeda unique multi-scale methodol-ogy to model the developmentcycle for thin-film organic elec-tronic materials and devices.

A new class of flexible

semiconductors enters the market

Printed electronics opens up large flexible sensor

design opportunities

Compared to traditionalelectronic solutions, printedelectronics offers several dif-ferentiating factors which makethem particularly well suited to sensing application.

- NAVIGATION & GEOLOCATION

Efficient geolocation using

swarm radio

REaDER OffER

The FiND-iT is a PC and Androidsmartphone or tablet solutionthat enables users to associatepassive UHF radio frequencyidentification tags with items,as well as create inventory listsand find those objects using anAndroid smartphone or tablet.

Three such kits are for grab.

DISTRIbUTION CORNER

WhITEPaPERS

OPINION

Uncommon Market: Smart grids and IoT

convergence turns more data into cashWhile the smart grid sensor market is set to doublein size by 2014, growing to wellover $200 million of annual rev-enue by 2018 according to IMSResearch, it only represents afraction of the global market forM2M data collection, aggregationand actuation devices.

Last Word: Wearable computing: lets get it on

NEWS & TEChNOLOGY

Multicore systems face the

tools challenge

The move to more hetero-geneous multicore systemsis going to fundamentallychange the way code is developed in mobile.

Organic electronics another step closer to

commercialization

Organic and printed electronicshas been a promise for the future -over ten years or more.

Single die MEMS oscillator hitsthe mainstream

Printing microbatteries could

unravel new designs in medical

applications

Imagination tips Warrior

MIPS cores

Direct semiconductor wafer

bonds target next-gen solar cells

Toyota connects navigation

systems to the cloud

A new traffic information systemfor Toyota drivers blends a varietyof parameters including vehiclelocation data, current speed, roadconditions and even disasters.

Intel joins A4WP wireless charging group

Embedded Linux kernel tuned for

virtualization and determinism

Non-volatile CBRAM memory block

operates at less than 1VAdesto Technologies has presented a paper on theultra-low power operation of its proprietary CBRAM(Conductive Bridging RAM) memory, exploring theuse of the non-volatile memory technology embed-ded in a body sensor.

3 Electronic Engineering Times Europe July/August 2013 www.electronics-eetimes.com

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4/664 Electronic Engineering Times Europe July/August 2013 www.electronics-eetimes.com

Smart grids and IoT convergence

turns more data into cashBy Jui Hppich

WHIle tHe smart grId sensork i ub i iz by 2014,wi w v $200 ii f -u vu by 2018 cci Imsrch, i y p fci fh b k f m2m cc-i, i cui -vic. acci c yi bymchi rch, chi--chicuici y ccu f 2bii m2m cci y w 18 bii i 2022, h icib Cagr f 22%.

Viii h s gi C iPi h, h hwi ui, cu i-iy ic h phi , yi izi ppuii. Whi uiiypvi h i ui ipy, ik h liky

f erdF viu pu hpvi pw cupi fy ppic cc huh h,h c bi fcu y w hw k h b u f huh ip u ifc. Uiiypvi w h , bu -users would most probably be oered

subsets of metering data with simplied

response scenarios and nancial incen-iv uv h i picuy-pi hbi.

Whi hhw uibu f pwmetering, guring

u h v f h hub ipy -u f hiw f ip-i ipu-

i uc hi y-bi i vyuch wk i p wih uupi pjc c eup.

I Fc, h tBH aic (tbu B Hbi which cu h hui vih b) h ju b uchu h hip f ecCo2 - www.cc2.c - vu hw -

u u hi y c-upi p c up hpi h yp f ifi iciviy h i pvi h.

thi pi xpi wi p 4000ii cu c yp fhui vi, wh wi b ivh ppuiy icwih f

ten dierent user-interfaces.

o f h ic p, Fui -www.udia.com is in the business of

pvii y cupi y-i u by -u. F ii, h cpy h vp - pic , hFui, which i cpb f ipicy - (uch cic wih w-

i ih cchic wih bck k ic). th c h i p f iu .

a pu upu cuic hu y ki f i u-i. Wih h cc ifi,Fuvi ih i hdata and gures out what comes from

h hi, h w-h, ppici -by, h fi, h ihi . th u h ivhuh wb-vic m2m uif h uiiy pvi cc f h ifi hi -cu- vi ii p.

thi i wh i pviv-i, ic y-i -h c ifccu iy b bu wih h i- cc p (i f i ic c i h hu-h), b ipy icy h

cu w bi vic.dui h c, Buyu

tc, Ijk Is2t hv wh hy c FifhPy i y vic, -

b i Buyu tc Bbxsi I wy. thvic i h Ijk pfi h cu h Is2t miceJjv b pf which -b h Bbx wy c,cy y viy f p cu.

th wy, h I ccu bc hub f h- ppic, i k hcci bw h i h w f h I-

Fluvias optical reader allows the company to extract power con-

sumption information and to perform data analytics from old electricity meters.

Already rolling out, ERDFs Linky.

Examples of housing environment dash boards

as proposed by the TBH Alliance.

Washing Machine

Refrigerator

Boiler


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Ever wished for abetter bench scope?The new RTM: Turn on. Measure.

Easy handling, fast and reliable results exactly what users expect

from a bench oscilloscope. Rohde & Schwarz opens the door to

a new world: Work with two screens on one display. Access allfunctions quickly. Analyze measurement results while others are

still booting up. See signals where others just show noise.

Thats the RTM.

Ever wished there was an easier way? Ever wished for more

reliable results? Ever wished you could do your job faster?

Then take a look.

www.scope-of-the-art.com/ad/rtm-video



f-thi (It) wh m2m c-uici ky fi vi h cu.

Ijk cu-b y

ui whi pi (uiii, c, vic ) pytheir software and oer energy

eciency and demand response

vic hi iicu. thi hp uiiipiiz h bc bw, ic-i (icui h u f hybi c bckupy ).

Looking at dening the most

pppi iuiiv uifc f -u cu h y-data, the company co-nances

h mc pjc f uiiypvi dic ei (fygup Pw dic ei).

th pjc icu iwih 2000 cu quippf hf f h wih h liky , f h hhf wih h f . th xpi ivv cii wh wi y

ip h -cupcpi f hi w i y cupiprole (and maybe how to raise

hi y w).The idea is to dene the best

i (h cvici) f h cu opt-in for self-eacing low-en-y cupi bhviu pk i ( uc h h i), pbbythrough tari incentives.

s u p

cu w h uiiy pvi remotely turn-o a selected list

f ppic w h- i ui pk i.a w pvii piztips for better energy-eciency,

h -u ifc cu -cu w picipi iiviu cciv ch- h hi xpi-c wih hi cuiy b pcic ciwk.

I i xpc h h uiici wih hi -uwu w uiiy pvi ipvtheir forecasting and protability through

vc yic bhviuproling.

Ijk H ey msvic hv b h w I Pu 6 mui svicgwy, bu h cpy u-

fcu i w y -wy i pu i cic ppiccupi c h

y. oh i- vic icu ycb h, -pu hyy - i p/cwich c h c sms i c f iuiupici.

H tchy www.h-chy.u w xhibii -c h wy h wihviu cubi w hi h cy y,ih vi bb cc-i huh h bi gPrswk (hk isIm c).

o c, uu i pjc uwy i h f f -ceco-districts, specically de-i xpi u vp pii y-

ui.a 50/50 ji vu c-

i 2001 bw a Buyu, ebix pviy- vicf uch c-iic, iii

icy wih c uhii buii w, pii iuc iic v.

th cpy ivy i h iic vp- ph h pih y piizi h

ihbuh-v huh iUb Pw pf, ivvi h cu ss (sfw svic). th pf i- ccib -i-i hwih c y puci storage uxes.

o uch pjc i Iygii h si ou buiiic i Iy--muiux Pi. Jiy upp by

micf, Buyu Ibii,

Buyu tc, schiecic, t, a, erdF,

etde si, h pjc iii i2012 w cv h f y10,000 pp i 160,000 qu-- . I i xpc icu by

Engage

Ijenkos cloud-based energy management solution.

Home Technologys smart home gateway enables dwellers to

manage their home remotely.

Embix provides energy-management services to so-called

eco-districts such as the IssyGrid project in Issy-les-

Moulineaux near Paris


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ii buii i 2013.

a h eup v, h gi4eU-c i pjc

bi h ciu f ix eu-p y iibu (erdF, ediibuzi, Ib, CeZ dii-buc, Vf eiibui rWe) h pi f i i - uch wb y i-i, cic vhic vp, iui, y , yeciency and load reduction.

six wi b v pi f fu y (i i2016) i ch f h eup cu-i p i h ciu.o f h cuy ip i nic gi (i C, suhf Fc), upi 1 500 -cu-. I xp wb yi wih 200 fp,i 100 bi quiv 2mWh f cpciy, ip- cui wih h quip. such -cpjc hp uiiy pvi new forecast algorithms and gure out

wy uc cupi vui pk .

Founded in 2011 and spun-o from

mic, V-sy k i -yic fw ui, Vey,to help oce and residential building

p icip fuu y . th yicfw ui y hyic f i y i h cc , i bi i h qui whcii pici, y picuctuations and availability (distant,

c u-c uc i h cof connected buildings) to oer more

ccu iiviuiz y pi-

ii chic ( ju ui yproles). The tool will be a central piece

of the urban project Lyon Conuence

2 which wi icu 16000 f pivp ci hui. a hw ccup wi b iv cc hi y-cupi huh ii b i b chi y cupi cci hi cf z (wih h uu ic-tives for self-eacement).

A dedicated communication

network for the IoTnw cuic hi , f h p u i h buii cu y ZiB, eh cci c bb cc, i

Pw li Cuici ik, gsmu, xii WiFi p h ppiy rF ik.

F w huhpu ppiciuch i i, h chi vki cci luvic l m,Ceo f sifx, cpy h cycelebrated the rst anniversary of what it

claims to be the worlds rst low-power

cu ifucuic h I--f-thi. siffxchy bui upu w b i,cbi wih fwdened radio techniques

pf b -i v chiv vy hih iiviy fvy ic c-uici (f 3 10k i ub ,

30 50k i u v 1000k fu bjc i i i f ih).The company oers its

wk vic f i

p y f hcci f It-i (f y bjcquipp wih h sifx

i) f pc-i ui i vi hcu y hi pyppici. o xph cpy iv i iphip wih maaF a-uc, i Fchiuc cpy whichwi y h sifxnetwork to oer re and/

iui vic i cu icyhuh sms. F w,sifx wk cvFc, bu h cpyh bi p f xpii eup. By pipy f iicu wk, hi Itwk ifucuh h pi vhu f w/hu i w wih biif cc bjc, yh cpy.

Vesta Systems dynamic software solution for interconnectedbuildings provides accurate and individualized energy

optimisation choices.

Sigfox low data throughput IoT network infrastructure

could prove more economical than traditionnal carriers.


9/66www.electronics-eetimes.com Electronic Engineering Times Europe July/August 2013 9

Multicore systems face the tools challenge

By Nick Flaty

The move To more heTerogeNeous ltic yti in t fndantally can t way cd i dlpdin bil, ay a ladin IP ppli. Ti i t t xcitindcad I a n f cptin, aid Tny Kin-sit, x-cti ic pidnt f aktin at Iainatin Tcnli,talking at the Multicore Challenge Conference run by verication

xpt Tvs. T a pptniti t lad ti lbal can in t uK.

h pint t t incain plit in t bil akt b-tween ARM and other processor architectures all running dier-nt in f gl pn c Andid patin yt.

Intl a tatd t a cc wit x86-bad Atpc in bil andt and tablt, wil Iainatina acqid t mIPs pc lin and i cbinin ti witit Pwvr apic and id tcnly and it pa-abl adi fnt nd. Cpld wit t t tcnlic a ay tacin, ti cat a widly ayin t f qi-nt, ay.

W a t acitct in t Andid wld bt tapp a t b abl t ta CPu in t a way ty dac gPu and adi. W a t bak ti dpndncy nt CPu intctin t acitct and ti i pat f t ftf tn pcin, aid Kin-sit. gl iwll awa f ti pbl, aid.

There are dierent ways to tackle this issue, he says, includ-in nw capabiliti in t LLvm tl cain ( bx). W aqit xcitd abt LLvm and t ptabl binay fat witbinay tanlatin, aid. Ant xcitin appac actallycan t way yt a dlpd. Intad f dwnlad-

in an app f a paticla IsA, a nic app i dwnladdtat intiat wat adwa c a aailabl. Tidicy app cld b wittn wit LLvm binay tanlatincapability a i ll lana c a Jaa.

onc t dicy app dtin t adwa aailabl, itdownloads dierent optimized blocks for the dierent hardware

lnt, catin t ptial ftwa. Ti i nt ipl td. Dicy will b a ftil aa f ac and innatin,aid Kin-sit.

m iptantly it al can t way t ftwa ideveloped, he says. Instead of starting o with the data struc-t, y tat wit t dicy app. Tat pid t basoftware that is already available, and the developer then lls

in t ap in t ftwa cyt, cncntatin n tadded value rather than re-inventing software for multiple dier-nt platf.

Pttin all ti tt wit t it balanc f y andpfanc dtin t pw cnptin and pf-anc f t yt. Ti i a y ky aa, aid. At-tention to detail makes a huge dierence. Ive seen four to ve

times the performance dierence using exactly the same set of

IP, ttin t balanc i ttly ky in akin t ytwk.

T tl i i t ain an wy ltic cptin

has been slow to take o, says Prof David May at the Universityf Bitl. h pint t n acitct w tprogramming is signicantly easier. This was the approach he

tk wit t ltic yt d by Xmos sicndctw i a fnd.

Fig. 1: Imagination Technologies sees a discovery tool that looks at the hardware and downloads the relevant optimized code to

build the code base for heterogeneous multicore devices.

Multicore challenge conference



h al pint t ld lana c a Ftan wicincld ppt f paalll patin tan dn day Cand C++. hw, t i a lt f fc n t paalll capa-biliti bin addd t t lana. Pal Ki f dlp

CodePlay in Edinburgh points to the C++ AMP 1.0 specica-tin tat i aailabl f aytcic ltipcin, wit amicft iplntatin incldd wit vial stdi 2012. TCitt Daft (CD) f C++14 i t f Pblic riw, wilopnmP 4.0 i xpctd ti wit rla Candidat 2nw aailabl f pblic cnt.

T nxt opnCL, opnCL hLm, will incld C/C++ yntax/cpil xtnin, and t a n a nw in f F-tan, Ftan 201x, in dlpnt. Cbinin t dbinand proling tools pays dividends, says David Lecomber, COO

f Wawick-bad i pfanc cptin tl nd Al-lina, w dntatd t tl at t mltic Cnfnc.

scintit, tdnt, and dlp lan nc and wintwice as they prole and debug their code with two tools that

lk and fl t a, aid Lcb.Wit t la f in 4.1, dlp and cintit can

Allina DDT and Allina mAP intcanably. Ti jintlicnin ptin i a natal pin tat bin al t ct. hPC cnt a alady tllin tat adptinn pat f t tl-it nca t adptin f t tant ti .

Weve noticed uidity in the workow. A developer uses Al-lina DDT t t t cd it, tn Allina mAP t ndtandits performance, and then icks back into Allinea DDT to un-

c a pfanc i t ca, ay mak oCnn,Allina vP f Pdct manant. W wantd t ppttat.

Wkin btwn Allina DDT and Allina mAP i f patic-

lar interest to organizations like Cenaero, an applied researchcnt in Bli tat dlp ilatin td and ft-wa tl.

Lat ya, it wa appintd by t Wallnian minit f r-ac t pat a Ti-1 pcpt, wic will xtnd itcnt clt f 3,000 c t tan 10,000 c.

on f t iin apct f hPC ta i t analyiand ndtandin f t I/o pattn f applicatin. AllinamAP nw pid ky tic, c a t at f ad/witcall and ncacd data tanf, akin it ay t pt anddian lin f cd wit lw I/o pfanc in ial andpaalll applicatin.

Bt cintit and dlp, w fac a cbinatin fftwa pbl and p t adanc ti ac, f-tn pt f t fal cny f tyin tin witt takin tti t l t, aid oCnn. Allina DDT 4.1 atatically,cd actin takn and t aiabl n dlp cancck t cnt cd aaint t bai f a pi -sion or even run it on a dierent system.

Allina DDT 4.1 a al bt in cntl it int tcode display, showing the age of dierent lines of code along

wit a ppl wt t dcib ti can.When youve got this information, its much easier to x the

t ca f pbl, ay oCnn. It a pwfl db-in aid and t i ntin l lik it n t hPC akt.

GCC vs LLVM: Its all about the skills

as $99 supercomputer shipssouThAmPToN-BAseD tl cainpid ebc a dlpd afll gNu Cpil Cllctin (gCC) tlcain f a nw lw pw ltic p-c tat aid it dlpnt nyn t Kicktat tatp wb it.

us-bad Adapta aid naly $1f ppt n Kicktat t dlpa 2W, 64 c, 100gFLoP dic n28n, and t $99 bad tatd ippinin Jn. ebc a n f t alydlpnt bad f wkin n ttl cain. It a 5 ta, dal i pip-lin and ac pc a it wn lcaly and w n-ll t cd lpt t t pfanc, aid D JyBnntt, fnd and Ceo f ebc.W a a in f gCC tat ipiplin ccpancy f 70%, and tatc f a dp knwld f gCC

wit t lp nllin. T a pbably50 d gCC nin in t wld andw a n f t. T dntatinw a 512 atix calclatin andldin 68 at tan cnd. Ti i t

ll f pfanc w nd f sft-ware Dened Radio, he said.

T a t t cpani wk-in n Lw Ll vital macin (LLvm)f t Adapta pat. Wat w witLLvm i, a a cpil it i d, takint 30 ya f xpinc inc gCC,said Bennett. What I see as a diculty

i t bi play diin it, Arm, Qal-c, Intl. T a 8 acitctin t tandad ditibtin cpad t 40 in gCC.

on an f in t LLvm i tl ticti licn cnditin. TgPL licn fc gCC t b kpt t-t. LLvm ak it ai f ppl td ti wn tin and nt c ttand tat a wakn, aid.

Bt tat al an t a nin wkin wit LLvm. Wit

LLvm a d ftwa nin can bp t pd in a ya , aid Bn-ntt. hain t bt an tialy and tat incdibly alty f tcyt.

The Adapteva Parallella development

board a $99 supercomputer with

Embecosms GCC tool chain.

Multicore challenge conference


11/66

Our world changes by the nanosecond. New connections are

formed. Old problems are solved. And what once seemed

impossible is suddenly possible. Youre doing amazing things

with technology, and were excited to be a part of it.

2013 Maxim Integrated Products, Inc. All rights reserved. Maxim Integrated and the Maxim Integrated logo are trademarks of

Maxim Integrated Products, Inc., in the United States and other jurisdictions throughout the world.

THANK YOU FOR

AMAZING YEARS


12/66

Your Global Link to the Electronics World

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POWER MANAGEMENT

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engineering europeengineering europe



Organic electronics another step

closer to commercialisationBy Citp hacidt

orgANIC AND PrINTeD lctnic a bn a pi ft ft - tn ya . Bt nw t tcnlyis ready for commercialization, believes Wolfgang Mildner,

pidnt f indty aciatin oe-A (oanic and Pintdelctnic Aciatin). At t LoPe-C anic lctnictad fai cntly ld in mnic, claid tat ti tcnl-y alady bca cnplac in a nb f applica-tin, in paticla in atti paactical and packa-in indti.

mildn citd pintd antnna and at ccpancy nwic a aid t b alady in in t atti indty.T nxt tp will b t aailability f tc n and di-play f dplynt in icl. At t fai, t oe-A al di-tibtd a bc wit pintd batti and LeD intatdint t fnt c - pn t p f an qally pintdbutton, the LEDs were lit see gure 1. In order to drive com-mercial viability, it now is necessary to rene the technology,

bt al t tink it at pint w t dynaic f titcnly and it akt a cand, mildn aid.

Twad ti nd, t indty aciatin al intdcd amodied roadmap for the further development of this tech-nology and its commercialization. The roadmap breaks the

technology down into ve segments - organic photovoltaics,exible displays, OLED lighting, electronics and components,

and integrated smart systems see gure 2. At the pres-nt ll, t tcnly i at a ta w latily iplpdct a pibl - f xapl, ptabl ca in teld of organic photovoltaics, or garments with integrated sen-, anti-tft pdct in t nt f intatd atyt. T tat f oLeD tcnly nly pit dintdi.

T adap nw tat t al in t t, diand ln t. In t nt f anic ptltaic,

t al incld, fexample, customized

bil pw; in t -ment of exible displays,

the companies organized

in t oe-A intnd tdlp bndabl oLeDdiplay, platic LCD, llabl cl diplay.In oLeD litin, ty ain f tanpant anddcati litin d-l. st t f tt ti pan f 2014t 2016.

Ln-t al (ya2021 and bynd) incldbildin intatin andid cnnctin f tnt f anic p-tltaic, llabl oLeDTv and tldicin

applicatin in t -ment of exible displays,

wil oLeD litin willb pat f t nallitin tcnly. Inthe eld of electronics

and cpnnt, tcintit ad dictlypintd batti a ln-t al, and in tintatd at ytnt, oLeD will b

intatd int ant, and alt nitinyt will b ad f anic lctnic pat -

t na jt a fw al.Din a pntatin at t fai, Adi dicd

it swa tdy f an oLeD-lit ca bdy gure 3. While the mock-up oers a spectacular

lk, t tcnly i nt qit ady f al-wld dplynt, paticlaly nt f attiqint. oLeD i t it tcnly, btit i nt yt p t atti tandad, aidStephan Berlitz, Head of Lighting Innovations at

Adi.T ain calln ain t lifti f t

dlicat lctnic. T cd oLeD dntwittand bad wat cnditin, and al at

y i lw tpat ty tnd t fail.Another issue is cost, Berlitz admitted. Neverthe-l, initd, oLeD will a a at ft.T nti atti indty a alady bnt intat oLeD int ti ca, aid

Fig. 1: Printed electronics in real-world

applications - the LEDs on the cover of

an OE-A brochure can be lit by the push

of a button.

Fig. 3: Impressive lighting effects from

Audi - longevity is still a challenge.

Fig. 2: From simple to complex functions and applications - the new roadmap

for organic electronics.

report: lopec



Single die MEMS oscillator hits the mainstream

B Nk FSilicoN laBS haS ported w mu MeMs

ng qu w su Sn cks n 2010

cns fun SMic. ts ws SG suu b bu

n f ssvn f cMoS g usng

xsng cMoS un n n m-

ns f bms f u vs

as the materials are specically chosen to

un m f.

t gmmb ss un u

100Mhz w fqun sb wn

20m n m s-snsv, w-

w n g-vum nus, mb

n nsum ns ns su

s g ms, sg n mm,

atM mns, n-f-s qumn n

mu-funn ns. hg s vs

nn, ss Mk pwsk, v s-

n n gn mng f Sn lbs

mng us.

t cMoS MeMs (cMeMS) ng nbs gun

s fmn w 10 s f fqun sb

nung s sf, ung, Vdd vn, ng

mu ng, vbn n sk. ts gun -

ating life performance is 10 times longer than typically oered

b mb s n MeMs ss. t ss

g u MeMs sn w cMoS mu

sns n mnsn u, nsung g sb

fqun uu n f f m nsns n v

fu nus mu ng. t n su s -

b, b fqun fn v

ng ng fsns f nus n

mb ns.

t S50x cMeMS ss su

n fqun bwn 32 khz n 100

Mhz. Fqun sb ns nu

20, 30 n 50 m ss xn

mm (-20 70c) n nus-

(-40 85c) ng mu

ranges. The CMEMS oscillators also oer

extensive eld- and factory-programmable

fus nung w-w n w-

j ms, gmmb s/f

times and polarity-congurable output-

nb funn.

Usng cMoS MeMs n s fs usm-

s fm su n bms f n

quz-bs suns. Bus cMeMS ss n-

g, mn ics, kg n w u,

m-mun 4-n kgs, gn nsung -

b n b su n.

Printing microbatteries could unravel

new designs in medical applicationsB Jun h

a teaM BaSed at harVard UNiVerSity n Unvs f

ins Ubn-cmgn, s mns w 3d nng

n nw b us n um-n mbs sz f

grain of sand, which could be small enough to t in tiny devices for

m mmunns ns.

in n s ngns v nvn mn mnuz -

vices, including medical implants, ying insect-like robots, and tiny

cameras and microphones that t on a pair

f gsss. Bu fn bs w

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bung sm. t g un s bm,

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s. hwv, u u-n

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not pack sucient energy to power tomor-ws mnuz vs.

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The interlaced stack of electrodes,

printed layer by layer, create the working

anode and cathode of a microbattery -

Source and top image: Harvard


15/66

Baseband & RFMIMO & FadingRohde & Schwarz SMW 200AThe new vector signal generator for wideband communications systemsUnique generator with baseband, signal calculation, fading, MIMO, AWGN

and RF generation in a single box. Two paths up to 6 GHz. Full modularity.

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All key MIMO modes, including 3x3, 4x4 and 8x2

All key communications standards

Comprehensive help for efficient working

Outstanding modulation and RF characteristics

SMW 200A. The fine art of signal generation.

www.rohde-schwarz.com/ad/smw-mr

Watch the video



Imagination tips Warrior MIPS cores

By Pr Crkimagination teChnologies grup pc (K ly, e-

d) ucd p uc r

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performance proles. The Warrior generation includes 32- and

64-bit variants with a focus on performance eciency across

-d, d-r d ry-v/crcrr CPU,

i d.

i d w rduc x-r Wr-

rr cr r yr d bu r d w

cur. t cpy d Wrrr wud prvd

bry cpby w cy 32-b d 64-b miPs cd.

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print single-core version to the interAptiv family and a oating

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provide levels of performance, eciency and functionality that

go beyond other oerings in the market.

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Direct semiconductor wafer bonds

target next-gen solar cellsBy Ju hppcthe fRaUnhofeR institUte foR solaR ery sy

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version eciency toward 50 percent, stated

Dr. frk Dr, hd dpr iii-V

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cells for more than 20 years and has reached record device

eciencies of up to 41 percent with its metamorphic triple-

junction solar cell technology on Ge. Higher eciencies require

the development of four- and ve-junction solar cells with new

r cb p u brp r

suns spectrum between 300-2000 nm. Integration of III-V solar

c c p r ppruy rduc uc-

ur c, pcy w cbd w dr ubr

lift-o technologies. Direct wafer-bonding is expected to play

pr r dvp x-r iii-V

r c dvc w ppc pc w rr-

r ccrr pvc (PV).

eVg CBd cy b

dvpd rp rk d r

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for combining materials with dierent lattice

constant and coecient of thermal expan-

(Cte). t prc d qup

cy b r bd

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uc c cpud -

cducr, cpud cducr

cpud cducr, g c

d g cpud cducr

r prur, w cv xc

bd r.t CBd cy w b crcy vb

later this year on a new 200-mm modular platform currently in

development, called EVG580 ComBond, which will include pro-

c du r dd prr urc prpr

prc b cducr r d .

III-V multi-junction concentrator solar

cells on 4-inch diameter wafer. (c)

Fraunhofer ISE.



Toyota connects navigation systems

to the cloudBy Crp hrcd

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information being shown along with T-Probe trac information,

ru ry, d zrd p prvdd by c vr.

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tics systems. Suitable processing of T-Probe trac information

enables map-based route planning for eective guidance to

up d, w c rck d rv

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t rvc w b vb y Jp, ty d.

Intel joins A4WP wireless charging groupBy Pr Crk

intel has JoineD the allianCe r Wr Pwr (a4WP)

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drd rz Wr Pwr Cru (WPC),

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A4WP, which species the use of magnetic resonance tech-

y, cpb uu cr up dvc

and the exible positioning of devices and a charging platter.

Intel believes the A4WP specication, particularly the use

of near eld magnetic resonance technology, can provide a

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development organizations, management of an A4WP certica-

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Embedded Linux kernel tuned for

virtualization and determinismBy Nck Flrty

WiNd RiveR has tckl on of t mn objcton to un

rtulzton n ntworkn n communcton pplcton by

optmzn t mb Lnux krnl for Rl

Tm prformnc.

The Open Virtualization Prole is an add-onsoftware prole for Wind River Linux developedby optimizing open source Kernel-Based Vir-tul Mcn (KvM) tcnoloy. T pro

a real-time deterministic KVM solution, withrtul mcn mnmnt to llow ypr-or n rtulzton tcnoloy to ruc

rwr cot n pro oftwr ntll-nc portblty cro t ntwork.

The Open Virtualization Prole allows the deployment ofntwork rc on rtul mcn wtout t prformnc

loss associated with using traditional, propriety IT-like virtualiza-tion products. This real-time approach enables products thatcan exibly run intelligent services anywhere on the network,from access right to the core, driving up network eciency andubtntlly lowrn oprtonl ntwork cot.

The prole includes low latency with less than 3 microsec-onds minimum latency, exible provisioning of virtual machines,

l mrton of rtul mcn n CPU iolton for -vanced security application. It is open source-based and com-

patible with frameworks such as the Yocto Project, OpenStack,OpenFlow, oVirt and others, with broad support for a variety of

ut oprtn ytm

T krnl ntrt wt intl dt

Pln dlopmnt Kt (intl dPdK) n up-port intl dPdK acclrt Opn swtc

As networks are pushed to their limits,rtulzton bcomn n ncrnly

mportnt pproc. Oprtor r look-n towr NFv to upport t trnton

to scalable platforms that enable exibledeployment of network services, said JimDouglas, senior vice president of marketing

at Wind River. With Wind River Open Virtualization Prole, weare delivering a real-time virtualization solution that will supportt rorou sLa of crrr ntwork n nbl tm to n

the exibility, scalability, and cost and energy benets clouddata centers already enjoy.

By mon from trbut rwr nronmnt to

exible and virtualized environment or cloud, operators canrply ploy nw pplcton n rc wr n wn

they are needed instead of updating individual central oce

locations or hardware, he said. Wind River Open VirtualizationProle will be available in Q3 2013

Non-volatile CBRAM memory block

operates at less than 1VBy Julien Happich

adesTO TeChNOLOgies has prnt ppr on t

ultra-low power operation of its proprietary CBRAM (ConductiveBridging RAM) memory at the 2013 Symposia on VLSI Technol-ogy and Circuits in Kyoto, Japan. The paper explores the useof the non-volatile memory technology embedded in a bodysensor, a device developed to operate without a battery in thesystem, through the use of energy harvesting.

T ppr follow t uccful complton of projct n

cooprton wt tm of tcnolot from t Unrty

of vrn to crt low nry c to cqur pyolo-cal data from the human body, process that data, and transfert trou wrl communcton. T projct w prtlly

fun by daRPa trou t Us ornmnt prorm to

nt n n wr mll bun nnoton rrc (sBiR).

CBRAM is an emerging, disruptive memory technology whichcan be integrated in standard CMOS processes, function as adiscrete memory device or be embedded in microcontrollers,System-on-Chip (SOC) or Field Programmable Gate Arrays(FPGA). The paper demonstrates the ability of a non-volatileCBRAM memory block to operate at less than 1V supply volt-

age for read, program and erase functions without the need for

charge pumps. This low-power functionality translates to 3xlower write voltage and approximately 10x lower write energycompared to other low energy non-volatile memory devices.

W bult om xctn wrbl wrl boy sn-sors that run completely without batteries from body heat, butone key missing piece was non-volatile memory (NVM). ExistingNVM devices are way too power-hungry for our aggressivepower budgets, said Ben Calhoun, associate professor at theUniversity of Virginia, This integrated ultra-low-power CBRAMfrom Adesto is an important advance for self-powered sys-tems.

Ultra-low energy non-volatile memory like CBRAM is es-

ntl to t lopmnt of nry tr tcnolo ttrqur tor ntructon n t collcton or n xtn

period, said Shane Hollmer, VP of Engineering at Adesto.T c mut prr t n n t nt of powr

interruptions and failures. CBRAM is a natural t for these ap-plications.



EDA & DESIGN TOOLS

Version control in EDA

for optimum hardware designBy Robrt huxl

AS A TYPICAL PRACTICE, mot lrEDA vendors conduct a costly on-sitec tuy of propct clnt

xtn ytm t cot tt cn run

nto t mllon of ollr. in t nxt

step of the scenario, they deploy a Fieldapplcton ennr (Fae) on t to

mnully prouc co. T objct:

an integrated design solution. Instead,t rult prouc lnty n cotly

proc tt oftn fl to ntrt

n mjorty of t propct -sired functionality, especially for versioncontrol.

Unfortunately, electronic engineeringuctor typclly o not tc ron

control. vron control ctully ol

oftwr bt prctc mtoolo-y. it bcm n bolut ncty for

oftwr lopr bcu prorm

rw to uc lr z tt ty r-qur r lrr n tm. Tryn to mn t olum

of code without an eective version control system provides anexcellent denition of hell. Version control allows multiple teammmbr to b multnouly workn on oftwr prorm

wtout rk of lon or orwrtn notr mmbr co.

Unless a companys sole business is to design boards, mostpopl n t lctronc prouct nutry unrtn tt

oftwr tm conrbly outnumbr tr rwr coun-trprt. Bcu rwr n tm nrlly tn to b

smaller, they have typically adopted document control typesof ytm wt ron numbrn cm. Tm mmbr

share folders on a server or even from a ling cabinet! Thesesolutions fall into the organize-it-into-a-box approach. Whichr t quton: tt rlly ron control?

Complexity in software developmentOver the past 20 years, software programs have grown rapidlyand become more complex. With each new software release,t co n to b rulrly upt to ncorport nw or

improved features and bug xes. To cope, the software industryimplemented modular design practices, a form of design reuse.However, modular design and reuse of code segments led tootr clln.

Compn foun tt run oftwr moul lr

many benets. Modules resulted in increased dependability be-cu ru oftwr lry bn tt n workn y-tems. Reuse also reduced process risk, since the functionality,

risk, and cost of existing software was already known. In addi-tion, reusable software makes eective use of specialists, since

t oftwr mbo tr knowl. Prp mot compl-

ling, design teams realized that reuse resulted in accelerateddevelopment, reducing the time spent in coding and validation.As a result, they could meet accelerated time-to-market objec-t n prouc nw trton of prouct ron ftr.

However, implementing software design reuse did not comewtout t clln. gnrlz pplcton of oftwr mo-ules doesnt just happen. First, the modules must be maintainedn lopmnt proc pt n ubqunt rl.

Ru moul my lo bcom ncrnly ncompt-ible with system changes in subsequent releases, resulting inincreased maintenance costs. To actually have value, reusedelements must be discoverable in the library, understood, andsometimes adapted. In subsequent versions, new or upgradedn lmnt wll lkly mpo prrqut n pnn-c to wc t ru lmnt mut comply. Prp mot

challenging in the IP ecosystem, many companies believe theycn n oul rwrt componnt bcu ty bl ty

cn mpro or own tm.

Software complexity leads to team approachIn a development team environment, multiple people touch thesame code. To manage the team, engineering managers needvisibility of their teams work. As a rst requirement, the teamn nl cur tor rpotory for tr rou

design modules. Once established, the design team neededn ncrmntl tory of cn m to t ourc co.

To achieve eective reuse in a team environment therefore also

required an eective method to check-in and check-out designourc.

Over the past 20 years or so, software design teams realizedthat an eective design management system must facilitatecollaboration between team members. As suggested above, theytm mut lo crt n mntn n ncrmntl tory of

Robrt huxl rponbl for t cr of altum cutomr n

Europe in his role as Industry Specialist - Enterprise Solutions -www.ltum.com

Fig. 1: Aberdeen Groups research report, Need to Save PCB Design Time? established

three categories of survey participants; best-in-class, average, and laggards.



EDA & DESIGN TOOLS

changes made to the source code in real-time. This also meantthat the system captured metadata for each change, includingwho made the change. This facilitated full traceability, mean-n t blty to ocumnt wc tm mmbr work on

which module, made what changes, and when. It also enabledmpro rportn n montorn o nnrn mnr

coul trck prouctty n n pror. all of t -nc rult n ccountblty by ll tm mmbr.

Version control for hardware designPCB design teams can typically range from one to 20 design-ers with an average of approximately ve for mainstream designrms. Large semiconductor companies may employ FAE teams

numbrn n t unr wo o rfrnc n work.Commonly, small to medium hardware design teams maintainlctronc n t on c nr nul r

drives. Unfortunately, no one then actually knows where all thet for t n loct.

As companies have realized this shortcoming, they havecommtt to mntnn tr corport knowl n

ct tb. elctronc rwr n tm

had some diculty implementing version control because theproc n tool r tll lrly b on oftwr nnr-n prncpl. Wtout n ntrt ron control ytm n

their EDA tools, hardware designers have tried freestandingversion control programs with check-in and check-out capa-

bilities. However, non-integrated solutions fall down becauset nul nr n/or t mnr cn mk no ul

compron to t cmtc n t PCB from on ron to

t nxt.

In EDA software with fully integrated version control, teammembers see the status of all templates, updates to relevantregulatory standards, and changes to any designs. As a resultall team members are automatically notied when a changeoccurs. In software, a manager or team member can run a dif-ferencing tool in the software under development to identify,rol n commt cn btwn ron.

However, EDA tools produce binary and graphical output, nottxt b output n oftwr co. T mk ntfyn

hardware changes via a text-based, non-integrated tool ex-tremely dicult and error-prone. Managers and designers needto see the changes graphically, merge them into the design, andcommit to the change. Simply put, none of these capabilitiesare possible with non-integrated version control systems.

Adjusting hardware design best practiceshrwr n prctc n to cn u to comptt

pressures as noted in the Aberdeen Groups research report,Need to Save PCB Design Time? The report is based on

interviews and surveys of 133 electronics companies. Oncethe research team gathered all of the data, they assembled acomptt mnt of t ury compn. Ty -tablished three categories of survey participants; best-in-class,average, and laggards.

As shown in the survey, each of the three categories ofcompanies exhibited common performance levels for ve keyprmtr:

Proc (t pproc ty tk to mn PCB t)

Ornzton (wo t xpo to)

Knowl Mnmnt (ow t knowl n t PCB

t mn)

Prformnc Mnmnt (t blty of t ornzton to

mur t rult to mpro t PCB t mnmnt

prctc)

Tcnoloy (t pproprt tool u to upport PCB t

mnmnt)

Version control, as noted in the Aberdeen report, falls into thecategory of Knowledge Management. Note that the Knowl-edge category in gure 1 cites three items:

scmtc n PCB lyout r yncronz

scmtc n BOM r yncronz

an tr ron control for c t lmnt on t

PCB

Any stand-alone version control software can performbasic check-in and check-out. However, design teams quicklydiscover that they cant automatically lock a checked-out item.T rult n tr orwrttn or lot n work. Tm

prtcpnt r lo unbl to ully compr ron n t

cmtc or t PCB. Ty lo pnfully lrn tt t oluton

lacks built-in data management functionality. Merging collab-orative work performed on dierent parts of the project posesfurther time-consuming challenges.

eda tool wt n ntrt ron control ytm (vCs)

deliver full check-in and check-out functionality including lock-ing of checked-out items. Like their software counterparts, anntrt vCs tbl nl rpotory for ll projct.

all n moul n componnt r cck nto t vr-on Control Rpotory.

Each individual le contains extensive meta data including arecord of design changes, the designer, date of change, etc seegure 2.

Wn two (or mor) tm mmbr multnouly cck out

an item, the le is formally checked out to the rst user. De-pending on the actual version control backend, the user eitherautomatically or manually locks the le from any other teammembers. When a second user checks out the same le, thisdesigner can work on it only as a copy. Once the rst designercompletes work on the le and saves it to the repository, thatcton rl t lock. Wn t con nr ropn

the now unlocked le, his work will be marked out of date.

He or she can review the changes made by the rst designerand merge the work previously done as a copy into the le andcck t bck n f pproprt.

To establish an Incremental history, the projects engineeringmanager performs the initial check-in and labels the project asREV 0. This becomes the starting point for the design.

Fig. 2: Version control basics.


21/66

Generation 10

Portfolio from Altera

Company Announcement

Visitwww.altera.com for more information

Ultra high definition broadcast

equipment, 400G Ethernet systems and

computer data centres all feast on vast

quantities of data. Consuming and

processing that level of data with any

electronic system is difficult. You will

need to be at the leading edge of

technology, both with the architecture

you use to process the data and the

manufacturing process you use to

generate the device.

FPGAs have for many years been at this

forefront of technology, Moores law has been

kind to FPGAs - with the right process/

architecture design decisions you can reduce

power, increase per formance and reduce cost/

increase density at each generation. Each

generation of FPGA captures more applications

that previously would have had to be designed

with ASICs, and opens a new market due to the

performance, flexibility, power or cost that

couldnt be reached with the older technology.

There are three key aspects to consider when

creating an ideal modern FPGA.

Leading-edge manufacturing processes

technology

Investments in innovative architecture and IP

High-performance integration of processors

with programmable fabric

Advanced process technologies are key for next

generation FPGAs. For example, a new 3D

transistor technology known as Tri-Gate or

FinFET transistor technology is a breakthrough

change in process technology. It halves leakage

current of transistors, which enables high

performance or low power capabilities.

Most process-technology foundry suppliers are

in the early test chip stages of finFET. At the

time of writing, Intel is the only manufacturer

who has production quality products shipping

using a 3D (Tri-gate) transistor technology.

Customers looking and asking for performance

improvements will not get this from 3D

transistor technology alone, but they will also

need a process shrink. The recently announced

14 nm Tri-Gate process from Intel provides

this process technology. Alteras future Strat ix

10 FPGAs will be built using Intels 14 nm

Tri-Gate process.

Process is only part of the story; Altera is

currently developing a new architecture which

is capable of astonishing core speeds of up to

1 GHz. The enhancements to the digital signal

processing (DSP) architecture delivers a

dramatic improvement to DSP capability

enabling over 10 TFLOPs of single precision

floating point operations. Transceiver

performance also gets a boost with the ability

to run at up to 56 Gbps data rates.

Within the Generation 10 portfolio Arria 10

FPGAs use a 20 nm planar transistor process

to implement sixteen 28 Gbps transceivers

for next-generation multi-100G optical

interfaces. With enhanced signal conditioning

techniques , such as adaptive decis ion feedback

equalizers (DFE), and hardened forward error

correction (FEC), high loss backplane

applications can be addressed.

Processor Integration

FPGA integration of discrete components on a

board has reduced the complexity and cost of

many customer systems, but one of the most

important changes has been the recent

integration of an ARM-based hard processor

sub-system (HPS). Altera Arria 10 SoCs offer

enhanced dual core ARM Cortex-A9 HPS,

this is a boost for customers wanting tighter

integration between CPU and FPGA fabric. The

next generation HPS is shown in Figure 3.

Figure 3: Second-Generation HPS

Block with ARM Cortex-A9 Processor

Next-Generation FPGAs andSoCs Are Coming

Altera uses a tailored innovative approach to

portfolio design, coupling new architectures to

the latest process technology to br ing together

an exciting suite of FPGAs. Its fair to say the

Generation 10 portfolio will have the largest

leap in capabilities that hardware architects

and system designers are yet to see thus far in

an FPGA.

Figure 1: Tri-Gate Process Technology

Figure 2: 28 Gbps Operation on 20 nm

Process Technology from Altera



EDA & DESIGN TOOLS

all cn r ubquntly only mntn ncrmntlly.

snc rptly n t complt n nw ron

number takes up enormous volumes of data storage space, theytm only t ncrmntl cn.

On potntl ourc of n cn proc rfrr

to a branching. Branching allows the design team to explorewhat-if scenarios as a branch of the main line of development.

any utorz tm mmbr cn tbl brnc t ny

point in the main development line. If V1.0 is released, branch-ing allows for minor xes. Branching allows for these xes,if appropriate, to be incorporated into subsequent productrl. dn tm un eda tool wt fully ntrt

version control system experience many benets, the rst ofwc ructon n rror.

accountblty n prouctty mpro bcu c

nnr cn w wo mkn cn n t n n

tt nnr work. ec tm mmbr cn tn rly

ask questions of that designer regarding that specic change.Further, because all team members can see each others work,prouctty mpro.

After implementing an integrated VCS, documentation andreporting also improve. Each time a team member checks a leback in, he or she must add a comment. This facilitates projectmanagement, QA, and standards compliance to get productscertied to current relevant industry standards. Further, with fullgraphic and onscreen visual comparisons between two dierentrevisions, team members can view highlighted changes side-by-side.

altum dnr nwr t ron control n of r-wr n tm. it lr t only fully ntrt eda r-on control ytm. all n t r mntn n nl

rpotory n t t rmn fully yncronz. T ytm

ply cn n up to four pnl on crn. T nc

cpblty furtr lt ll cn n bot t cmtc

and the PCB see gure 3. All changes are also documented txt to nnc mnmnt ort.

Timing closure highlights the challengesof 45nm silicon design and belowBy Chi-Ping Hsu

iNNOvaTiON is The CORNeRsTONe of t mconuctor

nutry n bn rponbl for m cn n ll

parts of the industry, from design through fabrication, assemblyn tt. T fountonl rqurmnt of nnoton n n

r cnn; ty r xpnn n cop. Pont oluton tt

locally optimize a single design process by some metric, suchas power, are more often than not proving to be a net disruptionto design closure, rather than a benet.

The necessarily expanded scope of innovation, especiallytrue for advanced node design, means that the most signicantnnoton wll com from lr ornzton tt r wlln to

mk bol ntmnt.

We estimate that the EDA investment for the move to 20nmand 14nm FinFET to be in the $1B range. For the size of ourindustry, this is indeed a bold, albeit necessary, investment.

We can regard the issue of timing signo as a microcosm oft wy n wc nnoton n eda cn n ow t

oln now n nto t futur.

Cnc dn sytm rpon wt t rcnt

introduction of its Tempus Timing Signo Solution, a new staticn tmn nly clour tool tt yl up to n orr of

mntu ftr tn trtonl tmn nly oluton.

Although start-ups have developed new technologies thatsolve individual parts of the signo problem, those innovationssometimes do not make it through to the implementation owsused by system-on-chip (SoC) engineering teams because theyo not ol t orrcn problm.

Over the past decade and a half, the physics of nanometertechnology have taken an increasingly rm grasp on the designprocess and created a much more complex situation for signo.T ft from asiC to soC n tt bn n rnt t

t trt of t mllnnum ccompn rmtc cn

n mtooloy n lo t wy n wc nnot n

tcnolo cm to t mrkt.

Just 15 years ago, signo for digital logic-dominated designs

w rltly trtforwr tnk to t u of wly c-cpt pproxmton. gt ly tronly outw wr

delay, which could be treated as practically negligible. Signow lrly mttr of prformn tmn nly b on

the results provided by the ASIC vendors golden gate-levelmultor.

Chi-Ping Hsu is Senior VP, Research and Development, SiliconRlzton group t Cnc dn sytm

www.cnc.com

Fig. 3: Collaborating, comparing and merging hardware

building blocks in Altium Designer.



dn tm rully took on mor of t rponblt

of signo work from the ASIC vendors as they moved produc-tion to foundries. At the same time, layout-dependent eectsply n ncrn rol n t prformnc of n. gt

ly mo to bcom l mportnt on crtcl pt. Wr

ly took or t ky u to ol. T cll for nw

generation of layout-aware tools developed by both large,broad-based EDA tools suppliers and start-ups.

Start-ups played a crucial role with their technology. Eachcould tackle a hole in the oerings of mainstream suppliers by,

very often, recruiting a small and select group of teaching cus-tomr wo coul f bck tl nformton on tool prfor-mance from real designs. Engineers from these start-ups wouldoftn n n clo collborton wt t n tm n

t cutomr rponbl for bncmrkn n workn wt

tr oftwr.

In recent years, many of the nanometer eects with whichsoC n tm mut n bcom cloly ntrcon-nected. Just ten years ago, a timing violation on a critical pathcould easily have been solved by the insertion of a buer, or themomnt of om of t t to ruc t wr tnc n

wt t ly. a pont tool optmz for t nly n oluton

could easily be inserted into a broader design ow.anly w oftn optmz for cpcty rtr tn ccu-

racy. As designs moved to millions of gates, runtime overheadwas often the primary issue. Parasitics could, to a large extent,b btrct out xcpt for pt tt wr xtrmly clo

to the timing margin. At 130nm, for example, the gap betweenmtl ntrconnct ln wr uc tt tr coupln cpc-tnc wr orow by roun n pn cpctnc. For

the inter-track coupling capacitance, it was generally easier andftr to mll mrn.

The number of timing runs was also quite limited. In general,it was sucient to analyze a best-case, nominal and worst-case scenario for three of the key parameters: process, volt-age and temperature. This would eectively encompass all therltc oprtn pont for t n on t trt proc. it

w ronbl to mk t umpton tt ly woul bat maximum temperature, lowest voltage and worst processconton.

As process dimensions shrank, assumptions that previouslyl up wll bn to brk own. T coupln cpctnc

between metal interconnect became much more signicant at

65nm because the line pitch was much tighter and the tracestml bcm tllr n orr to kp prtc rtnc

under control. As a result, the lines began to behave more liket prlll plt of cpctor.

At 45nm, the variation in metal thickness became a keyconcern, increasing the range over which designs needed to besimulated to provide best-case and worst-case delay values.Below 45nm, lithographically-induced variations in transistor,gate and local interconnect structures became signicant, lead-n to t ntroucton of lrr mrn to ccommot t

dierence across the process variability range.Other, more subtle, eects of the shift to nanometer dimen-

sions have led to an explosion in the eort needed to achievetiming signo.

T orrcn u t ntrcton btwn lobl n

local eects. Since the beginning of the past decade, behaviorunder temperature changes became more dicult to predict, atuton tt bn n t nm tmprtur nron

dependence. The issue is caused by the use of lower sup-ply voltages in order to provide greater energy eciency seegure 1.

Instead of running faster than a hot corner, the circuitrymy run mor lowly unr crtn trol olt t

temperature falls and the eect is dependent on the thresh-ol olt u n t c tt l lon t pt bn

analyzed. The reason for the eect is that two eects combineto trmn t ly trou loc t. at t r olt-ages used traditionally, mobility controls the drain current of anactive transistor. But as voltages drop, the threshold voltage hasa much larger role in determining drain current. As a result, old

umpton brk own n mn tt lrr numbr ofnly r n to cck proprly for rton.

In nanometer processes, variability is more localized than itw on olr proc. Mtl ln wt bcom mll

nou to mpct t rtnc of t wr wt jut mll

mount of rton. gn tt mtllzton prt

process from base layer processing, engineers cannot assumett proc rton wll mo n t m rcton for bot

base and metal layers. Therefore, at 45nm and to a larger extentat 28nm, multiple extraction corners were required for timingnly n optmzton.

doubl pttrnn pro furtr ourc of rblty n

sub-28nm processes. Because lithography under double pat-

terning calls for two masks for the same layer, the masks mustb prcly ln uc tt t pcn btwn pttrn

contnt cro t . altou founr r workn r

to minimize the eect, there will always be some phase shift int mk rlt to c otr n t my not b pobl to

predict what that phase shift is see gure 2. Timing views arerequired that reect the impact of phase shifts in dierent direc-

Fig. 1: Temperature inversion.

Fig. 2: Mask shift occurs with double patterning.



EDA & DESIGN TOOLS

tions for a given combination of temperature, voltage and otherproc rton.

The focus on low-energy design adds a further layer of com-plexity in timing signo. Designs that employ techniques such ynmc frquncy n olt cln n orr to optmz

their energy eciency will need to be analyzed at multiple oper-ating points to ensure that eects such as temperature depen-dence inversion do not adversely aect the timing reliability oft soC. T nly oul b prform nt t otr

sources of variability, leading to a combinatorial explosion.With just eight dierent operating modes, it is easy to reach

the situation where more than 200 timing views need to benlyz. Trou crful lcton n prunn of t com-binations removing those that are unlikely to provide signi-cantly dierent results to other tests it is possible to reduce

t numbr. But t soC mplmntton tm tll lft wt large number of timing views to generate - see gure 3.

The problem is not just conned to the leading-edge pro-cesses. Increasingly, low-power design techniques are beingppl to n m t olr proc. altou t

processes will have fewer sources of variability, as voltages arereduced to take advantage of power savings, eects such astmprtur pnnc nron bcom mor pprnt.

T tm t tk to nrt c tmn w only mll

part of the problem. Up to 40 per cent of the chip implementa-tion ow is now consumed by the time it takes to act on the re-sults of the analyses see gure 4. Each timing view generates t of olton tt n to b corrlt wt t rult

from the other timing views. Consolidating the data takes time,

engineering insight and, for many teams today, custom scriptsto proc t t. Tr tn t u of mplmntn t

cn n to clo tmn.

Todays signo timers are not physically aware. Any changes,such as buer insertion, are left to the implementation environ-ment as a post-processing step for engineering change order(eCO) nrton. Oftn t plcmnt of nw cll rmt-cally dierent from what is assumed by the optimization algo-rithms because available vacant space is hard to nd in highlyutlz n.

The result is a signicant mismatch between the assumedntrconnct prtc urn t optmzton tp n t

ctul plcmnt n routn tt rult from t eCO. Cn

may aect the timing of paths that may have already met tim-ing, causing them to violate timing in the timing views from thesubsequent iteration. What previously may have been a timing-cln w coul potntlly mny olton ftr plc-mnt n rroutn.

On tn bcom clr from n nly of t wy n

which timing signo has evolved over the past decade. Ampl tcnoloy upt not nou to ol t problm.

Conntonl wom ol tt trtup pro muc of t

nnoton for tcnoloclly rn mrkt. strtup tr-tonlly u tcn cutomr to lp r tm towr

market-ready solutions. However, such solutions do not alwaysmk t to mrkt bcu t n no lonr for nrrowly

dened solutions but for a tool infrastructure that cuts acrossthe dierent pieces of the implementation ow.

a mor ccurt mplmntton nn woul ruc om

of t or of ln wt multpl tmn w. But

nun oluton rqur ttnton to multpl pont n tt

ow, involving a more holistic approach.Tr r numrou ctor n t soC coytm wo cn

n o pro ntl knowl n fbck on u

that aect design and implementation. It is extremely dicultfor a start-up with a more restricted set of partners to engagewt ll of tm n orr to r t bt oluton. altou t

cor tcnoloy bn lr my mny tron pont

and provide better support for certain issues, the key today isto b bl to brn ll of t tcnoloy to bul mor co-sive solution. It involves input from foundries and IDMs, withtheir knowledge of the way that variability issues aect timing.Lbrry nor tr prt to ply n unrtnn t -u cu by mo to mllr omtr n t mpct of

tcnolo uc oubl pttrnn. an tr r t rly

adopter customers who can provide real-world designs thatexercise all parts of a design ow.

Tn tr t rol of t eda tool upplr to brn t

inputs together and develop new ways of dealing with the inuxof t. T upplr n to t cop to look t t

ow in a holistic manner and understand which are the choke-pont tt lmt n p. a mor ccurt mplmnt-ton nn for eCO on pobl nwr to t problm of

timing signo. But a more eective approach may be to look atthe overarching requirements of signo and to work out ways inwhich the application of timing xes and ECOs are made so thatthey are more closely integrated with the timing signo process.Tt rqur combnton of nw tcnoloy n ttnton

to detail in the architecture of the overall ow that a player withc of xprnc n mplmntton cn brn.

As a result, the industry is moving towards a new develop-

mnt ppln tt nol mtrx of prtnrp rtr tnindividual links between design and tools-development groups.By bringing these dierent views together, EDA tools developerscan react much more quickly to the needs of design and reectt pc of nnoton tt tkn plc n prouct n n

proc nnrn.

Fig. 3: Trend of analysis views (MxC) at shrinking nodes. Fig. 4: Aggregrate runtime with increasing views.



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Modeling skew requirements for

interfacing protocol signals in an SoCB Ha Kuar Ja, Gurav Kar ad Babul Aua

A system on A cHip (SoC) today consists of several dier-

rrr ub, r ad ur fr i/o

rfa uh a JtAG, ehr, Dspi, sent fr -

munication with the outside world see gure 1. All these are

universally accepted and have some timing requirements which

may be in form of input/output delay requirements or special

timing requirements (like transition and skew requirements for

dierent signals), which need to be taken care of at the STA

end. In this article, we will be focusing on one of these maxi-

mum and minimum skew between two signals.

Some of these protocols (like DDR) have requirement for a

nite maximum skew (dierence in delays) between the vari-

ous signals of a bus. All data has to change within a very small

timing window. On the contrary, minimum skew requirement is

generally specied to prevent the race condition between two

signals. This is usually one sided; e.g. signal a should follow b

after some nite time. Until recently, these skew requirements

wr dld a rudabu ar ad had b udad

regularly which adversely impacted the STA analysis time of

ah daaba a hr wr ull ra fr io -

straints maturity. Also, the constrained signals timing may get

deteriorated during optimization in the absence of constraints

on these signals. There can be dierent ways of implementingthis using multiple command combinations. Each has its own

merits and demerits. Lets look at three methods to achieve this

ur:

- Applying minimum/maximum delay constraints on data

signals

- Modeling as input/output delays

- Applying setup/hold checks considering one of the datasignals as reference signal

Applying minimum/maximumdelay constraintsWe can apply min and max delay constraints on data signals so

that data changes only within a given window. This method can

be used to constrain multiple signals for skew requirement as

discussed below. We are essentially assuming these signals to

Hans Kumar Jain is Lead Design Engineer at Freescale

sdur ida - www.freescale.com

Gourav Kapoor and Babul Anunay also work at Freescale

Semiconductor India as Design Engineers.

Fig. 1: SoC interfacing with the outside world

through I/O protocols.



EDA & DESIGN TOOLS

have some characteristic delay range, which is a pure assump-

tion or based on prior experience. The EDA command to apply

min/max delay is:

set_min_delay/set_max_delay signal

A data bus can be constrained to be within a specic win-

dow by constraining each bit signal with min and max delays

(where max_delay > min_delay) see gure 2.

set_min_delay data_bus[*]

set_max_delay data_bus[*]

The maximum skew requirement window will then be:

Max_skew_requirement = Max_delay_value Min_de-

lay_value

Similarly, the timing requirement for minimum skew can be

justied by applying max_delay constraint to one signal (the one

which is to occur rst) and min_delay constraint to the other

(the one which is to occur later see gure 3).

set_max_delay signal_1

set_min_delay signal_2

Whr:

Min_skew_requirement = Min_delay_value Max_delay_

value

The application of min/max delays oers some advantages,

the uncertainty values applied on path dont need to be taken

into account and delays can be modied in any of the data sig-

nal path as long as the above conditions are met. This method,

however, faces some limitations as it takes a couple of itera-

tions to decide upon the values of the min-max delay.

It is important to keep the values slightly pessimistic (com-

pared to the expected optimized value of delay) in the rst

iteration so as to eciently optimize the path delay as well. The

valu d b udad a wll afr uh ra bad

how much the tool was able to optimize the delay.

Also, the values need to be updated at regular intervals

as we make transitions across the stages since delay values

change. As delays of nets and cells scale across process, volt-

age and temperature variations, min/max path delays will be dif-

ferent across these. We have to calculate scaling factors across

corners and constrain these accordingly.

Constraining IOs by modelinginput/output delaysIn this method, we dene the relationship of interface signals

with respect to some clock. We may use it to implicitly dene

skew requirement by dening input/output delays of dierent

signals with respect to same clock such that they are con-

strained to have the required skew. Basically, by dening input

and output delays, we are dening setup and hold timings ofthe signals in the SoC as seen from the outer world. The de-

signer just needs to constrain these by dening valid and invalid

windows. I/Os may be constrained in EDA tools using the fol-

lowing commands:

set_input_delay/set_output_delay port_

name min/-max

To constrain signals to be within a timing window (maximum

skew requirement) using this technique, we need to dene

setup and hold checks (min and max input delays) for all signals

with respect to the same clock such that all signals are allowed

to change nowhere except the required window - as shown in

gure 4.

Considering both signals to be input signals,

max_input_delay = clock_period setup_requirement

min_input_delay = hold_requirement

Under the condition

setup_check_for_signal1 + hold_check_for_signal2 20 years

Essential Features

5V+ operation

EEPROM

LCD, mTouchSensing Solutions

USB, CAN, Ethernet

Analog Integration

Core Independent Peripherals

Confgurable Logic Cell (CLC)

Complementary Waveorm/Output Generator (CWG/COG)

Numerically Controlled Oscillator (NCO)

Programmable Switch Mode Controller (PSMC)

Intelligent Analog

Rail-to-rail op amps

Fast comparators

12b/10b/8b ADC

9b/8b/5b DAC

Zero Cross Detect (ZCD)

Voltage reerence

Design Support

Free MPLABX Integrated Development Environment

Free C Compilers

Comprehensive technical documentation

World-class, 24/7 technical support and training

Small Form Factors

As small as 8-pin 2 3 UQFNand 28-pin 4 4 UQFN

Many other package optionsavailable, e.g. 3 3 QFN, 5 5 UQFN

Faster Time-to-Market

Free sotware

Pin and code compatibility, easy migration

Pre-programmed parts via Quick TurnProgramming (QTP)

8-bit PIC Microcontroller Key Highlights


32/66

4 8-bit PICMicrocontroller Solutions

Baseline

Architecture

Mid-Range

Architecture

F1

Enhanced Mid-Range

Architecture

PIC18

Architecture

Families PIC10, PIC12, PIC16 PIC10, PIC12, PIC16 PIC12F1, PIC16F1 PIC18

Pin Count 6-40 6-64 8-64 18-100

Interrupts No Single interrupt capability Single interrupt capability

with hardware context saveMultiple interrupt capabilitywith hardware context save

Performance 5 MIPS 5 MIPS 8 MIPS Up to 16 MIPS

Instructions 33, 12-bit 35, 14-bit 49, 14-bit 83, 16-bit

Program Memory Up to 3 KB Up to 14 KB Up to 28 KB Up to 128 KB

Data MemoryUp to 134B Up to 368B Up to 1.5 KB Up to 4 KB

HardwareStack 2 level 8 level 16 level 32 level

Features Comparator

8-bit ADC

Data memory

Internal Oscillator

Op amp

In addition to Baseline:

SPI/I2C

UART

PWMs

LCD

10-bit ADC

Op amp

Configurable logic cells

Numerically controlled

oscillator

Complementary

waveform generator Hardware CVD

High speed comparators

In addition to Mid-Range:

Multiple communicationperipherals

Linear programmingspace

PWMs with independenttime base

Programmable switchmode controller

12-bit ADC

USB

PPS

In addition to EnhancedMid-Range:

8 8 Hardwaremultiplier

CAN

CTMU

Ethernet

Baseline

5 MIPS0.3753 KB Flash

640 Pins

Increased Memory

Interrupt Capability

Deeper Stack

Mid-Range5 MIPS

0.4814 KB Flash

664 Pins

PIC1816 MIPS

4128 KB Flash

Hardware Multiplier

18100 PinsF1

Enhanced Mid-Range8 MIPS

1.7528 KB Flash

864 Pins

Increased Performance

Hardware Multiplier

Advanced Communications

Optimized for C

Performance UpgradeOptimized for C

Cost Optimization

Unified MPLAB Tool Suite/XC8 CompilerFree IDE Free C Compilers Free Software Libraries

PIC106 Pin

PIC128 Pin

PIC161464 Pins

PIC1818100 Pins

Continuous development across all architectures and families.

Family:

Architecture:

8-bit PIC MCU Architectures


33/66

Featured Core Independent Peripherals Product Families

Family PinsFlash MemorySRAM (Bytes)

CaptureCompare/

PWMAnalog

CoreIndependentPeripherals

CommunicationsSerial I/O

AdditionalFeatures

PIC10(L)F32X 6448896

6402

8-bit ADC (3)CLC, NCO,

CWG

PIC16(L)F150X 8/14/201.75K14K

6451204

10-bit ADC (4-12),5-bit DAC (0-1),

Comparators (1-2)

CLC, NCO,CWG

UART, I2C/SPI Fixed Voltage Ref

PIC12LF1552 82K256

00

10-bit ADC (5) HCVD I2C/SPI Fixed Voltage Ref

PIC16(L)F151X 282K4K

12825622

10-bit ADC(17) HCVD UART, I2C/SPI Fixed Voltage Ref

58-bit PICMicrocontroller Solutions

Core Independent Peripherals

SummaryThe following Core Independent Peripherals take 8-bitMCU performance to a new level, while requiring noprocessor overhead.

CLC (Configurable Logic Cell): The CLC providesprogrammable combinational and sequential logic. Italso enables on-chip interconnection of peripheralsand I/O, thereby reducing external components, savingcode space, and adding functionality.

NCO (Numerically Controlled Oscillator): Aprogrammable precision linear frequency generator,ranging from


34/66

Featured Intelligent Analog Product Families

Family PinsFlash MemorySRAM (Bytes)

Intelligent AnalogCore

IndependentPeripherals

Additional Features

PIC16F527/570 20/281.5K3K64132

8-bit ADC (8),Comparator (2), Op amp (2)

-

PIC16F75X 8/141.75 KB3.5 KB

64128

10-bit ADC (4), 5/9-bit DAC (1),Comparators (2), Op amp (1),

High Current Pins (2)CWG/COG

Internal Shunt:providing high voltage

input capability

PIC16(L)F170X 14/203.5 KB14 KB256 B1 KB

10-bit ADC (8-12), 8-bit DAC (1),Op amps (2), Comparators (2),

Zero Cross DetectCLC,COG I2C/SPI, UART

PIC16(L)F171X 28/40/447 KB28 KB5122 KB

10-bit ADC (1728), 5 & 8-bit DAC,Op amps (2), Comparators (2),

Zero Cross Detect

CLC, NCO,COG

I2C/SPI, UART

PIC16(L)F178X 28/40/442K - 16K256 - 2K

12-bit ADC (1114), Comparators (34),Op amps (23), 8-bit DAC, 5-bit DAC (03)

PSMC I2C/SPI, UART

www.microchip.com/intelligentanalog

SummaryWith Microchips Intelligent Analog solutions, engineerscan reduce their component count, design smaller,

more cost effective boards, and benefit from simplified,higher performance designs and easier procurement ofcomponents. In addition, designers benefit from increasedflexibility like analog topology agility, utilizing the MCUsprogrammable analog interconnects and programmability.

To simplify your next design, Microchip has integrated thefollowing Analog Peripherals.

Op Amps

A basic building block in electronic design. Integrating opamps into the Microcontroller offers increased flexibilityand reliability while reducing BOM costs and board space.

High Speed Comparators

Comparators have be in the PIC Microcontroller lineup formany years. We are now offering feature rich High Speed(50 nS) variants to enable faster responding/more efficientclosed loop feedback designs.

Fixed Voltage Referrence

Fixed Voltage Ref provides an integrated stable voltagereference, independent of VDD.

Analog to Digital Conversion

16, 12, 10 and 8-bit ADCs available in our 8-bit offering

Digital to Analog Conversion

9,8, and 5-bit DAC options available in our 8-bit offering

High Current Sink/Source Pins

High Current Sink/Source pins with the ability to sink/source50 mA the high currents pins enable direct MOSFET drivefrom the microcontroller.

Zero Cross Detect

Enables the micro to be connected directly to the AC

input via a current limiting resistor. The ZCD will flag the

micro when the Zero Cross is approaching so any requiredswitching can be synchronized to reduce power andeliminate any switching related artifacts/noise.

Development Tools

F1 PSMC 28-pin Evaluation Board (DM164130-10)

PSMC development platform usingthe PIC16F1783

Break-out headers forapplication development

Connect to any F1 motor control add-on

Prototyping area

PICDEM Lab Development Kit (DM163045)

Development platform for 6 to20-pin parts

Work across differentarchitectures

Includes comprehensive user guide,labs, and application examples

Support for PICkit 3 and Expansion Headers


Intelligent Analog


35/66


36/66


37/66


Development Tools

PICDEM LCD 2 Demo Board (DM163030) Illustrates and supports the main

features of Microchips 28-, 40-, 64-and 80-pin LCD PIC microcontrollers

LCD glass with icons, numbers,alphanumeric and starburst display

Separate Processor Plug-in Modules (PIMs) areavailable to evaluate all of the LCD products

Booster capability for contrast control and dimming

LCD Explorer Development Board (DM240314)

Supports PIC24 & PIC18 LCD PIC

MCUs with XLP technology Current measurement terminals,

mTouch sensing solutions &expansion connector

Eight common LCD glass

Support 1/3 biasing

CTMU switch to showcase touch sensing

Four switches implemented for software demonstration

Power the board using 9V power supply, USB connector, twoAAA batteries or Connector for VBAT current measurement

PIC18F97J94 PIM Demo Board (MA180034)

Features 100-pin PIC18F97J94 for evaluation

of all 100-, 80- and 64-pin PIC18F97J94LCD/USB/General Purpose MCUs

Plugs into LCD Explorer Board(DM240314) for additional functionality

Contains code examples

PIC Microcontrollers with LCD

Segmented DisplaysSegmented displays are used in a wide variety ofapplications, ranging from meters to portable medicaldevices to thermostats to exercise equipment. PIC MCUswith integrated LCD drivers can directly drive segmenteddisplays with letters, numbers, characters and icons. Themain features of Microchips LCD portfolio include:

Flexible LCD segments

28 pins: up to 72 segments





Variable clock inputs

Integrated voltage bias generation

Direct drive for both 3V and 5V powered displays

Software contrast control for boosting or dimming fordifferent temperature or lighting conditions

Drive LCD while conserving power in Sleep mode

Integrated real time clock and calendar for displayingtime and date information

mTouch capacitive touch sensing capability

Crystal-free USB 2.0 options

Direct Drive for Segmented Displays

The LCD PIC microcontrollers support direct LCD paneldrive capability with no external components needed,lowering total system cost. They have integrated voltagebias generation which allows the MCU to generate the

different voltage levels that are required to drive the LCDsegment pins and provide good contrast for the display.The LCD MCUs support a range of fixed and variable biasoptions as well as variable clock inputs that enable theflexibility to work with many different glass vendors.

Contrast Control

Software contrast control is a key feature using firmware toeither boost or dim the contrast of the display. Boost thecontrast up to VDD or beyond if you are using one of theMCUs with an integrated charge pump. Software contrastcontrol allows the designer to vary the contrast on theLCD to account for different operating conditions such astemperature, lighting, and humidity. Also, software contrast

control can be invaluable for portable applications. As thebattery level starts to drop, the firmware can apply a boostto the contrast helping extend the battery life while stillseeing a crisp image on the display.

Featured LCD Product Families

Device Family PinsFlash(KB)

MaxSegments

Voltage(V)

Additional Features

PIC16LF1907 2840 3.514 116 1.83.6 10-bit ADC, EUSART

PIC16(L)F1947 2864 728 184 1.85.5 10-bit ADC, EEPROM, I2C, SPI, Comparators

PIC18F87K90 6480 32128 192 1.85.5 10-bit ADC, EEPROM, I2C, SPI, RTCC, Comparators, ECCP

PIC18F97J94 64100 32128 480 23.6 Crystal-free USB, VBAT, 12-bit ADC, ECCP, UART, I2C, SPI, Comparators

www.microchip.com/lcd


38/66


Development Tools

Low Pin Count USB Development Kit(DV164139/DM164127)

Development platorm or 14 and20-pin USB MCUs

For evaluation oPIC18F14K50/13K50 20-pinUSB MCUs + 145X

Contains hardware, sotware and code examples

Sel-directed course and lab materials

PICDEM Full-Speed USB Demo Kit (DM163025-1)

Evaluation platorm or

PIC18F2X/4XK50 amily oUSB MCUs

Full speed USB 2.0 device withoutthe need or an external crystal

Populated with the PIC18F45K50

PIC18F87J94 PIM Demo Board (MA180033)

Features 80-pin PIC18F87J94 MCUor evaluation o all 80- and 64-pinPIC18F97J94 USB/LCD/GeneralPurpose MCUs

Can be used with PIC18 ExplorerBoard (DM183032) or additional

unctionality Contains code examples

USBUSB communication is growing in popularity or remoteupgrades, downloading data and other portable serialcommunication applications. Microchips USB PIC

MCUs bring the beneits o ull-speed USB to a broadrange o embedded designs that can operate in variousenvironments and locations, enabling easy access to otherUSB devices such as printers, handheld devices or PCs.

Full-Speed USB 2.0 (Device)

Microchip oers USB solutions capable o ull-speed USBoperation with the PIC16 and PIC18 amily o devices. IUSB On-The-Go is a requirement we have solutions in our16 and 32 bit amilies.

Crystal-Free USB

USB communication requires 48 MHz with 0.25%

accuracy over temperature. This is typically done with anexternal crystal and an internal USB. We have recentlyimplemented technologies that allow a crystal-reeimplementation with the ollowing beneits:

Lower BOM cost

Tiny PCB ootprint

Simplifed design

More robust solution

Free USB Software

Microchip has USB sotware to support USB on 8, 16 and32-bit MCUs. This sotware is royalty-ree source code andalso includes sample projects. The 8-bit amily supports

USB device mode with ull speed operation. Additionalsotware support includes ull C and RTOS developmentenvironments. Included within this USB Framework Libraryis Microchips USB Framework Coniguration Tool.

Generates confguration fles with just a ew clicks Royalty-ree source code

Firmware projects and USB drivers or the PC

Add USB to any PIC MCU with UART

The MCP2200 is a stand-alone USB to UART serialconverter that enables ull-speed USB connectivity inapplications containing a UART interace. The MCP2200has 256 bytes o EEPROM and 8 general purpose I/O.

It oers a simple plug-and-play solution, allowing USBconnectivity with very little design eort.

PIC Microcontrollers with Integrated USB

Featured Crystal-Free Product Families

Device Family PinsFlash(KB)

Voltage(V)

Crystal-Free Additional Features

PIC16(L)F1459 1420 714 1.85.5 CWG, 10-bit ADC, DAC, I2C, SPI, UART

PIC18(L)F45K50 2844 1632 1.85.5 10-bit ADC, Comparators, ECCP, UART, SPI, I2C

PIC18F97J94 64100 32128 23.6 VBAT, 12-bit ADC, LCD, ECCP, UART, I2C, SPI, Comparators

www.microchip.com/usb


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Local Interconnect Network (LIN)Microchip oers a LIN compatible USART on a widevariety o microcontrollers. We have recently taken our LINoering to a new level by oering microcontrollers withintegrated LIN transceivers.

Development Tools

PICDEM CAN-LIN 3 Demonstration Board (DM163015)

Demonstrates CAN module eatures

Includes both frmware and PC sotwareor simulating a CAN network

In addition, the board employs a LINsub-network

Embedded EthernetMicrochip addresses the growing demand or embeddedEthernet products with the ENC624J600, ENC424J600and ENC28J60 as standalone Ethernet controllers,

and the PIC18F97J60 amily, which are IEEE 802.3compliant and ully comp

Documents

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