Progettazione di circuiti e sistemi VLSI

Sistemi Elettronici Programmabili

1

Progettazione di circuiti e sistemi VLSIProgettazione di circuiti e sistemi VLSI

Anno Accademico 2010-2011

Lezione 115.5.11

Memorie

(vedi anche i file pcs1_memorie.pdf pcs2_memorie.pdf – pcs3_memorie.pdf )


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Chapter Overview

Memory Classification

Memory Architectures

The Memory Core

Periphery

Reliability Case Studies


3

Semiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


4

Memory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

DATA

WRITE

READ


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Memory Architecture: Decoders

Word 0

Word 1

Word 2

WordN- 2

WordN-1

Storagecell

M bits M bits

N words

S0

S1

S2

SN-2

A0

A1

AK-1

K= log2N

SN-1

Word 0

Word 1

Word 2

WordN- 2

WordN 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals


Decoder

-


6

Ro

w D

eco

de

r

Bit line2L2K

Word line

AK

AK1 1

AL2 1

A0

M.2K

AK2 1

Sense amplifiers / Drivers

Column decoder


Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

-2L-K


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Contents-Addressable Memory

Address Decoder

I/O Buffers

Commands

29 Validity BitsPriority Encoder

Address Decoder

I/O Buffers

Commands

29 Validity Bits

Priority EncoderAddress Decoder

Data (64 bits)

I/O Buffers

Comparand

CAM Array29 words3 64 bits

Mask

Control LogicR/W Address (9 bits)

Commands

29 Validity Bits

Priority Encoder


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Memory Timing: Approaches

DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed

Addressbus

RAS

RAS-CAS timing

Row Address

AddressBus

Address transitioninitiates memory operation

Address

Column Address

CAS


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Read-Only Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2


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MOS OR ROM

WL[0]

VDD

BL[0]

WL[1]

WL[2]

WL[3]

Vbias

BL[1]

Pull-down loads

BL[2] BL[3]

VDD


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MOS NOR ROM

WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND


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MOS NOR ROM Layout

Programmming using theActive Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5 x 7)


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MOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL[3]BL [2]BL [1]BL [0]


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MOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8 x 7)

Programmming usingthe Metal-1 Layer Only


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Equivalent Transient Model for MOS NOR ROM

• Word line parasitics– Wire capacitance and gate capacitance– Wire resistance (polysilicon)

• Bit line parasitics– Resistance not dominant (metal)– Drain and Gate-Drain capacitance

Model for NOR ROM VDD

Cbit

rword

cword

WL

BL


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Equivalent Transient Model for MOS NAND ROM

• Word line parasitics– Similar to NOR ROM

• Bit line parasitics– Resistance of cascaded transistors dominates– Drain/Source and complete gate capacitance

Model for NAND ROMVDD

CL

rword

cword

cbit

rbit

WL

BL


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Non-Volatile MemoriesThe Floating-gate transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D


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Floating-Gate Transistor Programming

0 V

- 5 V 0 V

DS

Removing programming voltage leaves charge trapped

5 V

-2.5 V 5 V

DS

Programming results in higher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection


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A “Programmable-Threshold” Transistor

“0”-state “1”-state

DVT

VWL VGS

“ON”

“OFF”


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FLOTOX EEPROM

Floating gate

Source

Substratep

Gate

Drain

n1 n1

FLOTOX transistorFowler-Nordheim I-V characteristic

20–30 nm

10 nm

-10 V

10 V

I

VGD


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EEPROM Cell

WL

BL

VDD

Absolute threshold controlis hardUnprogrammed transistor might be depletion 2 transistor cell


22

Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1source n1drainprogramming

Many other options …


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Basic Operations in a NOR Flash Memory:Erase

S D

12 VG

cell arrayBL0 BL1

open open

WL0

WL1

0 V

0 V


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Basic Operations in a NOR Flash Memory:Write

S D

12 V

6 VG

BL0 BL1

6 V 0 V

WL0

WL1

12 V

0 V


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Basic Operations in a NOR Flash Memory:Write

S D

12 V

6 VG

BL0 BL1

6 V 0 V

WL0

WL1

12 V

0 V


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Basic Operations in a NOR Flash Memory:Read

5 V

1 VG

S D

BL0 BL1

1 V 0 V

WL0

WL1

5 V

0 V


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NAND Flash Memory

Unit Cell

Word line(poly)

Source line(Diff. Layer)

Courtesy Toshiba

Gate

ONO

FGGateOxide


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NAND Flash Memory

Word linesSelect transistor

Bit line contact Source line contact

Active area

STI

Courtesy Toshiba


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Characteristics of State-of-the-art NVM


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Read-Write Memories (RAM) STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended


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6-transistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ


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CMOS SRAM Analysis (Read)WL

BL

VDD

M 5

M 6

M 4

M1VDDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit


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CMOS SRAM Analysis (Read)

0

0

0.2

0.4

0.6

0.8

1

1.2

0.5

Voltage rise [V]

1 1.2 1.5 2Cell Ratio (CR)

2.5 3

Vo

ltage

Ris

e (

V)


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CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0

Q = 1

M1

M4

M5

M6

VDD

VDD

WL


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CMOS SRAM Analysis (Write)


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Resistance-load SRAM Cell

Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem

M3

RL RL

VDD

WL

Q Q

M1 M2

M4

BL BL


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SRAM Characteristics


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3-Transistor DRAM Cell

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn

WWL

BL1

M1 X

M3

M2

CS

BL2

RWL

VDD

VDD2VT

DVVDD2VTBL2

BL1

X

RWL

WWL


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1-Transistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

M1

CS

WL

BL

CBL

VDD2VT

WL

X

sensing

BL

GND

Write 1 Read 1

VDD

VDD /2 V

V BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V


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DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD


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1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly


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Static CAM Memory Cell

••• •••

CAM

Bit

Word

Bit

••• CAM

Bit Bit

CAM

Word

Wired-NOR Match Line

Match M1

M2

M7M6

M4 M5M8 M9

M3int

SWord

••• CAM

Bit Bit

S


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CAM in Cache Memory

Address Decoder

Hit Logic

CAM

ARRAY

Input Drivers

Tag HitAddress

SRAM

ARRAY

Sense Amps / Input Drivers

DataR/W


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Periphery

Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry


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Row Decoders

Collection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder


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Hierarchical Decoders

• • •

• • •

A2A2

A 2A3

WL 0

A2A3A2A 3A2A3

A3 A3A 0A0

A0A 1A 0A1A0A1A0A1

A 1 A1

WL 1

Multi-stage implementation improves performance

NAND decoder usingNAND decoder using2-input pre-decoders2-input pre-decoders


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Dynamic Decoders

Precharge devices

VDD

GND

WL3

WL2

WL1

WL0

A0A0

GND

A1A1

WL3

A0A0 A1A1

WL 2

WL 1

WL 0

VDD

VDD

VDD

VDD

2-input NOR decoder 2-input NAND decoder


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Sense Amplifiers

tpC V

Iav----------------=

make V as smallas possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition


49

Differential Sense Amplifier

Directly applicable toSRAMs

M4

M1

M5

M3

M2

VDD

bitbit

SE

Outy


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Differential Sensing ― SRAMVDD

VDD

VDD

VDD

BL

EQ

Diff.SenseAmp

(a) SRAM sensing scheme (b) two stage differential amplifier

SRAM cell i

WL i

2xx

VDD

Output

BL

PC

M3

M1

M5

M2

M4

x

SE

SE

SE

Output

SE

x2x 2x


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Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.

EQ

VDD

BL BL

SE

SE


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Other Circuits for Memory Periphery

• Charge-based Amplifiers• Single-to Differential Conversion• Voltage Regulators• Charge pumps

and other solutions…


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Reliability and Yield


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Noise Sources in 1T DRam

Ccross

electrode

a-particles

leakage CS

WL

BL substrate Adjacent BL

CWBL


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Alpha-particles (or Neutrons)

1 Particle ~ 1 Million Carriers

WL

BL

VDD

n1

a-particle

SiO21

111

11

22

22

22


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Yield

Yield curves at different stages of process maturity(from [Veendrick92])


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Redundancy

MemoryArray

Column Decoder

Row Decoder

Redundantrows

Redundantcolumns

RowAddress

ColumnAddress

FuseBank:


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Error-Correcting Codes

Example: Hamming Codes

with

e.g. B3 Wrong

1

1

0

= 3


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Redundancy and Error Correction


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Trends in Memory Cell Area

From [Itoh01]

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Progettazione di circuiti e sistemi VLSI