Temporizzazioni e sincronismo1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 10 3.5.2011 Temporizzazioni e sincronizzazione

Temporizzazioni e sincronismo 1

Progettazione di circuiti e sistemi VLSIProgettazione di circuiti e sistemi VLSI

Anno Accademico 2010-2011

Lezione 10

3.5.2011

Temporizzazioni e sincronizzazione


Synchronous Timing

CombinationalLogic

R1 R2Cin Cout Out

In

CLK

tc-q tp,comb

tc-q,cd tcdlog

tsu, thold


Latch Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

PWmtsu

td-q

Delays can be different for rising and falling data transitions

T

tc-q + tp,comb + tsu ≤ T

tc-q,cd + tcdlog > thold


Register Parameters

D

Clk

Q

D

Q

Clk

tc-q

thold

T

tsu

Delays can be different for rising and falling data transitions


Clock Uncertainties

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty


Clock Nonidealities

• Clock skew– Spatial variation in temporally equivalent clock

edges; deterministic + random, tSK

• Clock jitter– Temporal variations in consecutive edges of the

clock signal; modulation + random noise– Cycle-to-cycle (short-term) tJS

– Long term tJL

• Variation of the pulse width – Important for level sensitive clocking


Clock Skew and Jitter

• Both skew and jitter affect the effective cycle time• Only skew affects the race margin

Clk

Clk

tSK

tJS


Clock Skew

# of registers

Clk delayInsertion delay

Max Clk skew

Earliest occurrenceof Clk edgeNominal – /2

Latest occurrenceof Clk edge

Nominal + /2


Positive and Negative Skew

R1In

(a) Positive skew

CombinationalLogicD Q

tCLK1CLK

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogicD Q

tCLK1

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q


Positive Skew

CLK1

CLK2

TCLK

TCLK

th

2

1

4

Launching edge arrives before the receiving edge


Negative Skew

CLK1

CLK2

TCLK

TCLK +

2

1

4

3

Receiving edge arrives before the launching edge


Timing Constraints

R1

D QCombinational

LogicIn

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Minimum cycle time:T - = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive negative skew)


Timing Constraints

R1

D QCombinational

LogicIn

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Hold time constraint:t(c-q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives lateRace between data and clock


Impact of Jitter

CLK

-tji tter

TC LK

t j itter

CLK

InCombinat ional

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter


Longest Logic Path in Edge-Triggered Systems

Clk

T

tSU

tClk-QTLM

Latest point of launching

Earliest arrivalof next cycle

tJI +


Clock Constraints in Edge-Triggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

tc-q + TLm,cd + tSU < T – tJI,1 – tJI,2 -

tc-q + TLm,cd + tSU + + 2 tJI < T

Skew can be either positive or negative


Shortest Path

ClktClk-Q TLm,cd

Earliest point of launching

Data must not arrivebefore this time

ClktH

Nominalclock edge


Clock Constraints in Edge-Triggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

tc-q,cd + TLm,cd – tJI,1 < tH + tJI,2 +

tc-q,cd+ TLm,cd < tH + 2tJI+


How to counter Clock Skew?

RE

G

RE

G

R

EG

.

RE

G

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing


Latch-Based Design

L1Latch

Logic

Logic

L2Latch

L1 latch is transparentwhen = 0

L2 latch is transparent when = 1


Clock Distribution

CLK

Clock is distributed in a tree-like fashion

H-tree


The Grid System

D r iv e r

D r iv e r

Dri

ver

Driv

er

G C L K G C L K

G C L K

G C L K

•No rc-matching•Large power


Self-timed and Asynchronous Design

Functions of clock in synchronous design

1) Acts as completion signal

2) Ensures the correct ordering of events

Truly asynchronous design

2) Ordering of events is implicit in logic

1) Completion is ensured by careful timing analysis

Self-timed design

1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol


Synchronous Pipelined Datapath

In

tpd,reg tpd1

D

R1

Q

CLK

LogicBlock #1

tpd2

D

R2

QLogic

Block #2

tpd3

D

R3

Q D

R4

Q

Documents

Temporizzazioni e sincronismo1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 10 3.5.2011 Temporizzazioni e sincronizzazione