Bias Circuits for RF Devices

Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul/ A lot of RF schematics mention: bias circuit not shown; when actually one of the most critical yet

often overlooked aspects in any RF circuit design is the bias network. The bias network determines the amplifier performance over temperature as well as RF drive.

The DC bias condition of the RF transistors is usually established independently of the RF design. Power efficiency, stability, noise, thermal runway, and ease to use are the main concerns when selecting a bias configuration. A transistor amplifier must possess a DC biasing circuit for a couple of reasons.

We would require two separate voltage supplies to furnish the desired class of bias for both the emitter-collector and the emitter-base voltages.

This is in fact still done in certain applications, but biasing was invented so that these separate voltages could be obtained from but a single supply.

Transistors are remarkably temperature sensitive, inviting a condition called thermal runaway. Thermal runaway will rapidly destroy a bipolar transistor, as collector current quickly and uncontrollably increases to damaging levels as the temperature rises, unless the amplifier is temperature stabilized to nullify this effect.

Amplifier Bias Classes of Operation

Special classes of amplifier bias levels are utilized to achieve different objectives, each with its own distinct advantages and disadvantages. The most prevalent classes of bias operation are Class A, AB, B, and C. All of these classes use circuit components to bias the transistor at a different DC operating current, or ICQ. When a BJT does not have an A.C. input, it will have specific D.C. values of IC and VCE. These values will correspond to a specific point on the D.C. load line, point named Quiescent Current ICQ.

In the graph above the circuit is said to be midpoint biased since the values of IC and VCE at Quiescent-point are one-half of their maximum values.

Class A single-ended amplifiers are ordinarily used only in small-signal non-power applications.

Class A will generally require a constant current bias source to fix the operating point regardless of the RF drive and output. The circuit will have to have some sort of feedback to keep the output current at a fixed level, or a circuit must be created whose current is large compared to the amount of output power required (i.e., it is quasi class A in that the operating point movement is minimal).

Simply by decreasing the Icq of the amplifier by a small amount, Class AB operation can be reached. But any Class AB single-ended power amplifier will create more output distortion than a Class-A type due the output clipping of the signals waveform. Class AB or B operations require some form of positive biasing - though the operating point will move with RF drive. This will require an open loop circuit with some sort of compensation over ambient conditions.

Class C will generally require a negative bias of some kindor in most cases, the input of the transistor is tied to ground with an inductor or resistor, which is sufficient to keep the conduction angle correct.

Typical BJT Load-Line Characteristic for Different Bias Classes

The most predominant biasing schemes used to obtain both temperature stabilization and single-supply operations are:

base-biased emitter feedback voltage-divider emitter feedback collector-feedback diode feedback active-feedback bias

All five are found in Class A and AB operation, while Class B and C amplifiers can implement other methods. Biasing Considerations for RF Bipolar Junction Transistors (BJT)

Usually the manufacturer supplies in their datasheets a curve showing ft versus collector current for a bipolar transistor.

For good gain characteristics, it is necessary to bias the transistor at a collector current that results in maximum or near-maximum ft.

On the other hand, for best noise characteristics, a low current is generally most desirable. Finally, one must consider the maximum signal level expected at the input of the transistor.

The bias point must be at a sufficiently high current (and voltage) level to prevent the input signal from swinging the collector current out of the linear region of operation. It is assumed that a transistor has been chosen having a sufficient operating current level to prevent the input signal from driving the transistor into the so-called saturated region of operation, which would also be an operating condition that would prevent linear operation.

If the amplifier is to work over a range of temperature, have to design a bias network that maintains the D.C. bias point as the operating temperature changes.

Two basic internal transistor characteristics are known to have a significant effect on the DC bias point. These are VBE and .

The base-emitter voltage of a bipolar transistor decreases with increasing temperature at the rate of about 2.5 mV/C. Emitter voltage VE tends to minimize the effect because as base current increases (as VBE decreases), collector current increases, and this causes VE to increase also. However, as VE increases, collector current tends to decrease.

In the same time, the transistors D.C. current gain typically increases with increasing temperature at the rate of about 0.5% per degree Celsius.

The BJT is quite often used as a Low Noise Amplifier due to its low cost. With a minimal number of external matching networks, the BJT can quite often produce an LNA with RF performance considerably better than an MMIC. Of equal importance is the DC performance. Although the devices RF performance may be quite closely controlled, the variation in device DC parameters can be quite significant due to normal process variations.

Important for an RF BJT is that variation in hFE from device to device (up to 3 to 1) will generally not show up as a difference in RF performance.

Two BJT devices with widely different hFEs can have similar RF performance as long as the devices are biased at the same VCE and IC. This is the primary purpose of the bias network, i.e., to keep VCE and IC constant as the DC parameters vary from device to device.

Base-biased emitter feedback works in the following way: The base resistor (RB), the 0.7 V base-to emitter voltage drop (VBE), and the emitter resistor (RE), are all in series;

Base-biased emitter feedback

- As the collector current (IC) increases due to a rise in the transistors temperature, the current through the emitter resistor will also increase, which increases the voltage dropped across RE. - This action lowers the voltage that would normally be dropped across the base resistor and, since the voltage drops around a closed loop must always equal the voltage rises, this reduction in voltage across RB decreases the base current, which then lowers the collector current.

The capacitor (CE) located across RE bypasses the RF signal around the emitter resistor to stop excessive RF gain degeneration in this circuit. The higher the voltage across RE (VE), the more temperature stable the amplifier, but the more power will be wasted in RE due to VE 2/RE, as well as the decreased AC signal gain if RE is not bypassed by a low reactance capacitor. Standard values of VE for most HF (high frequency, or amateur band) designs are between 2 to 4 V to stabilize VBE. UHF amplifiers and higher frequencies will normally completely avoid these emitter resistors.

For better temperature compensation the most common method is Diode Temperature Compensation. Two diodes, D1 and D2, attached to the transistors heatsink or to the device itself, will carefully track the transistors internal temperature changes.

Diode temperature compensation bias

This is accomplished by the diodes own decrease in its internal resistance with any increase in heat, which reduces the diodes forward voltage drop, thus lowering the transistors base-emitter voltage, and diminishing any temperature-induced current increase in the BJT.

A very low-cost biasing scheme for RF and microwave circuits, but with less thermal stability than above, is called collector-feedback bias.

Collector feedback

The circuit, employs only two resistors, along with the active device, and has very little lead inductance due to the emitters direct connection to ground.

Collector-feedback bias temperature stabilization functions so:

- As the temperature increases, the transistor will start to conduct more current from the emitter to the collector.

- But the base resistor is directly connected to the transistors collector, and not to the top of the collector resistor as in the above biasing techniques, so any rise in IC permits more voltage to be dropped across the collector resistor.

- This forces less voltage to be dropped across the base resistor, which decreases the base current and, consequently, IC. For bipolar transistors, Class-C amplifiers permit the use of three biasing techniques:

signal external self bias

The average Class-C transistor amplifier is normally not given any bias at the base whatsoever, but in order to lower the chances of any BJT power device instability the base should be grounded through a low-Q choke, with a ferrite bead on the base leads grounded end.

These biasing techniques will still require an RF signal with high enough amplitude to overcome the reverse (or complete lack of) bias at the Class-C input.

Class-C signal bias

A less common method in Class-C amplifiers is to use an external bias.

Class-C external bias This circuit uses a negative bias supply to bias the base, and a standard positive supply for the

collector circuit. The RFC acts as high impedance for the RF frequency itself so that it does not enter the bias supply.

Some low-frequency high gain IF amplifiers (Intermediate Frequency) will split the single emitter feedback resistor into two separate emitter resistors, with only one of these resistors having an AC capacitor bypass, while the other one is providing constant degenerative feedback to enhance amplifier stability, reducing the chance of oscillations. This topology allows to solidly setting the gain of the amplifier, just changing the value of R4 resistor.

Stable IF Amplifier

Cascode approach is a configuration that is inherently stable. In the example below the first transistor operates common emitter and sees as its load, the low input impedance of a common base stage. The 10k base resistor is common for both stages, and the bias is done through a 2:1 transformer used to get a wide-band matching.

Stable BJT Cascode LNA with resistive bias scheme

Highly Stable Active Bias for High Frequency Amplifiers The most common form of biasing in RF circuits is the current mirror. This basic stage is used everywhere and it acts like a current source. It takes a current as an input and this current is usually generated, along with all other references, by a circuit called a bandgap reference generator.

A bandgap reference generator is a temperature-independent bias generating circuit. The bandgap reference generator balances the VBE dependence on temperature, to result in a

voltage or current nearly independent of temperature. The most basic current mirror topologies are:

In this mirror, the bandgap reference generator produces current Ibias and forces this current through Q1. Scaling the second transistor allows the current to be multiplied up and used to bias working transistors.

One major drawback to this circuit is that it can inject a lot of noise at the output due primarily to the gain of the transistor Q1 which acts like an amplifier for noise.

A capacitor can be used to clean up the noise, and resistors degeneration can be put into the circuit to reduce the gain of the transistor.

With any of mirror topologies, a voltage at the collector of N.Q1 must be maintained above a minimum level or else the transistor will go into saturation. Saturation will lead to bad matching and nonlinearity.

Temperature Reference Circuits

The general recipe for making temperature independent references is to add a voltage that goes up with temperature to one that goes down with temperature.

If the two slopes cancel, the sum will be independent of temperature. To realize this idea bandgap voltage reference circuits are the most used. It produces an output voltage that is traceable to fundamental constants and therefore relatively insensitive to circuit variations, temperature and supply.

Temperature reference circuit

With proper choice of R1 and R2, the output voltage will have zero variation with temperature,

providing in the same time at the emitters of Q1 and Q2 a voltage proportional with temperature (thermometer output).

Generally is stated that the output impedance of the bias circuitry should be kept small, in order to increase the linearity of the output bias stage. However, the output impedance is typically designed to have a large resistance in order to reduce the noise contribution from the bias circuitry, and to avoid significant loading on the RF input port.

For example, to use an inductor in the bias circuit to form low impedance near DC, and high impedance near the RF signal band.

It is difficult to compare different bipolar LNAs if the biasing arrangement is not mentioned. Using an external bias from an external power supply can increase the IIP3 of an LNA compared

to an LNA with an on-chip bias.

Active bias LNA

The transistor, Q2, increases the accuracy of the current mirror, since the required base current for the LNA and Q1 is not taken from the reference current, IR1.

It may be necessary to remove Q2 for low supply voltages, since the current mirror formed by LNA, Q1, and Q2 requires a supply which is at least two times the base emitter voltage.

Sometimes high-frequency LNAs uses an emitter degeneration inductor for better matching, and is possible that the series resistance of this inductor to affect the accuracy of the current mirror.

The NF of the LNA is increased if the noise from the bias is not properly filtered out. This can be done by using appropriate filtering capacitors. This can be done by using appropriate filtering capacitors as C1 and C2, which shunt the noise from the biasing to ground.

If Q3 is a power amplifier mounted on a heatsink, Q2 shall be mounted on its own heatsink for power dissipation, when Q1 shall be mounted on the main heatsink, as close as possible to the RF transistor, in order to perform temperature compensation.

A different method used to increase the IIP3 of the LNA by biasing is presented below:

Dual-bias LNA

The dual-biasing is constructed using two different bias paths. The primary biasing is a current mirror and the secondary bias a diode bias feed circuit.

With a small signal, the current mirror provides the bias current for the Q3 LNA. When the signal is increased, the Q3 base current increases and the voltage across the biasing

resistor R2 increases, reducing the base voltage. As the voltage drops, the current to the base of the input transistor through the diode bias-feed

(Q4) increases, compensating the base-voltage drop. Therefore, the LNA linearity and compression point are both improved. This bias circuit features the lowest source impedance of the less complex bias circuits.

Therefore, it is recommended for high power device biasing and for other demanding applications. Bias Circuit using supply regulator

The main advantages of the bias source shown in the figure above:

The circuit it provides the lowest source impedance at a relatively low cost, The bias voltage remains independent of variations in the power supply voltage Temperature compensation is easy to implement.

The diode D1 performs this function and should be in thermal contact with the heat source. Depending on the current requirement and the pass transistor used, Q1 may have to be cooled. It has a positive temperature coefficient to the bias voltage, but the temperature coefficient is negligible compared to the negative coefficient of D1. This permits Q1 to be attached to the main heat sink. R1 and D2 are only necessary if the RF amplifier is operated at a supply voltage higher than 40 V, which is the maximum rating for the regulator. This circuit also provides regulation against supply variations. The source impedance mainly depends on the hFE of Q1. Active bias design for LNAs using lumped elements or distributed elements.

Active-bias LNA Lumped elements Active-bias LNA Distributed elements

The bias circuit shown has to be carefully bypassed at both high and low frequencies. There is one inversion from base to collector of RF transistor, and another inversion may be

introduced by RFC, matching components and stray capacitances, resulting in positive feedback around the loop at low frequencies.

Low ESR electrolytic or tantalum capacitor from the collector of Q2 to ground is usually adequate to ensure stability.

Steps designing an active bias for the schematic above: 1. Select an ID current through the diode of 2 mA. 2. Select an appropriate IC current for Class-A bias of the RF transistor amplifier 3. Select a VCC for the active bias network that is approximately 2V or 3V greater than the VCE required for the RF transistor. 4. Select an RF choke (RFC) for the active bias circuit with the appropriate SRF (self resonant frequency) that is greater than the frequency of operation. 5. Select both a silicon PNP transistor with a beta of at least 30 and a low-frequency silicon diode (a PNP transistor is used so that the VCC may be a positive voltage)

The idea adding a diode in the circuit is to compensate for the 2.5 mV/C of the PNP base-emitter junction with the same factor introduced appropriately into the active bias circuit.

Active Voltage-Feedback Bias

A good biasing scheme is shown below and uses two transistors (PNP and NPN) in a voltage-

feedback scheme from the collector to the base of Q1.

Voltage-Feedback Bias

The voltage-feedback it maintains the collector of the RF LNA Q1 at one-half the supply voltage plus one VBE (base-to-emitter voltage, about 0.4V).

Transistor Q2 measures the voltage difference between the collector of Q1 and the center point of the two resistors R1 and R2, which is amplified and fed back to the base of Q1.

Q1s collector voltage holds quite accurately at half the supply voltage plus one VBE because of the gain in the feedback loop.

Gain changes with temperature in all of the transistors are corrected for, and no adjustable resistor is required.

The bias circuit has to be carefully bypassed at both high and low frequencies.

FET Bias Bias networks are what are used to put a FET at the intended quiescent operating point.

For example, you might want to operate a FET in a power amplifier at 12 volts VDS and at 50% of the saturated drain current (IDSS/2). This is the quiescent point.

The same as in BJT case there are at least three ways to bias up a FET amplifier to get to the intended quiescent operating point.

One option is to have separate DC power supplies for the gate and drain connections, with the gate supply being adjustable, and ground the source. Grounding the source will provide the most gain and efficiency from the FET. In this case generally the gate bias supply is a fixed negative power supply -5 Volts, with an adjustable resistor-divider network being employed to supply the needed gate voltage.

Another method of biasing a FET is with an active bias network, generally designed in a feedback configuration to maintain constant quiescent current.

Common-source FETs can utilize a common Class-A biasing technique called source bias, a

form of self bias.

FET Source Bias

With FETs, unlike BJTs, no gate current will flow with an input signal present, so the drain current will always be equal to the source current.

However, source current does flow through the source resistor RS, creating a positive voltage at the top of this resistor.

Since the FETs source is shared by both the drain and the gate circuits, and the gate will always be at 0V with respect to ground (since no gate current equals no voltage drop across RG), then the gate is now negative with respect to the common source. This allows the FET to be biased at its Class A, AB, or B quiescent currents Icqs, depending on the value chosen for RS, while a capacitor can be inserted across RS in order to restrain the bias voltage to a steady DC value.

The Source de-coupling capacitor CS is required to ensure that there is no RF power loss on RS. The downsides to using self-bias schemes are that amplifier efficiency is lost due to the voltage

drop of the source resistor. FET Active Feedback bias example

Suppose that we have the following GaAs FET bias circuit:

432MHz GaAs-FET LNA

1. The DC current through diode D1 increases (due to temperature variation or change in device) 2. Then, the voltage drop across R3 will increase, reducing VBE, Q1. 3. The collector current of Q1 drops, reducing the voltage drop across R4. This reduces VGS and ID

of Q2 to correct for the change in step 1. Negative -5V supply voltage for biasing GaAs FETs The following circuit is providing a -5V bias voltage from a positive +12V power supply. The inverter is based on a NE555 circuit followed by a push-pull amplifier and a voltage doubler detector. The oscillation frequency is approximately 32kHz, which must be well DC filtered at the output to dont pass through the bias of the RF circuits.

-5V bias voltage from a +12V power supply

Biasing of MOSFETs Since MOSFETs have gate threshold voltages up to 5 to 6 volts, they require some gate bias voltage in most applications. They can be operated in Class C (zero gate bias), but at a cost of low power gain.

Zero bias is often used in amplifiers intended for signals that do not need linear amplification (such as FM signals and some forms of CW signals), and efficiencies in excess of 80% are not uncommon.

In Class B, the gate bias voltage is set just below the threshold, resulting in zero drain idle current flow. The power gain is higher than in Class C but the drain efficiency is 10 to 15% lower. Class B is also suitable only for non-linear amplification. Between classes of operation, one must decide whether the system has power gain to spare and how important efficiency is. At higher frequencies, such as UHF, a good compromise may be Class B or even Class AB.

In Class AB, the gate bias voltage is somewhat higher than the device threshold, resulting in drain idle current flow. The idle current required to place the device in the linear mode of operation is usually given in a data sheet. In this respect, MOSFETs are much more sensitive to the level of idle current than are bipolar transistors. They also require somewhat higher current levels compared to bipolars of similar electrical size.

The temperature compensation of MOSFETs can be most readily accomplished with networks consisting of thermistors and resistors.

The ratio of the two must be adjusted according to the thermistor characteristics and the gFS of the FET. The changes in the gate threshold voltage are inversely proportional to temperature and amount to approximately 1 mV/C. These changes have a larger effect on the Idq of a FET with a high gFS than one with a low gFS. Unfortunately, the situation is complicated by the fact that gFS is also reduced at elevated temperatures, making the drain idle current dependent on two variables.

The thermistor is thermally connected into a convenient location in the heat source in a manner similar to that described for the compensating diodes with bipolar units discussed earlier.

The circuit above shows a typical MOSFET bias voltage source using the 723 IC regulator. The temperature slope is adjusted by the ratio of the series resistor (R5) and the thermistor (R6). In addition to maintaining a constant bias voltage, this circuit also features a bias voltage regulation against changes in the power supply voltage. MOSFET Closed-Loop Biasing

Figure above shows a Closed-Loop system for MOSFET biasing.

It provides an automatic and precise temperature compensation to any MOSFET regardless of its electrical size and gFS.

No temperature sensing elements need be connected to the heat sink or to the device housing. In fact, FETs with different gate threshold voltages can be changed in the amplifier without affecting the level of the idle current. This means that the gate threshold voltage can vary within wide limits over short or long periods of time for a variety of reasons.

In addition to temperature, other factors affecting VGS(th) might be moisture, atmospheric pressure, etc.

The principle of operation of the circuit shown as follows: the idle current of the MOSFET amplifier is initially set to Class A, AB, or anywhere in between these bias limits by R7, which also provides a stable voltage reference to the negative input of the operational amplifier U1. Current flows through R1 with a

consequent voltage generated across it. This voltage is fed to the positive input of U1, which results in the output of U1 following it in polarity, but not in amplitude. Due to the voltage gain in U1, which operates in D.C. open-loop mode, its output voltage excursions are much higher than those generated across R1. Thus, if the current through R1 tends to increase for any reason, part of the output voltage of U1 fed to the amplifier gate bias input will adjust to Cascode MOS LNA Bias

Cascode MOS LNA Cascading transistor M2 is used to reduce interaction of the tuned output with tuned input. Transistor M3 essentially forms a current mirror with M1. The current through M3 is set by the supply voltage and R2 in conjunction with VGS of M3.

The bias resistor R1 is chosen large enough that its equivalent noise current is small enough to be ignored. In a 50 ohms system values of several hundred ohms to kilo ohms or so are adequate MMIC Amplifier Biasing

Typical MMIC internal schematic (DC blocking caps, Rbias and RFC are external components)

The current-biased MMIC will attempt to draw more current as the temperature rises. The biasing is primarily determined by the current, where the voltage is relatively unimportant. The effectiveness of this temperature bias control is dependent on the voltage drop across RBIAS,

a value of up to 4 V may be required for proper stabilization across a minus 25C to a plus 100C temperature range.

If the RBIAS does not add up to 600 or more, then the gain of the MMIC stage will suffer. If RBIAS does not compute to be at or over 600, then an RFC should be added in series with RBIAS

to increase the output to this value, or approximately RBIAS + XL > 600. These amplifiers are unconditionally stable at all frequencies, and they can be easily cascaded for

higher gain. The inductor bias-feed circuit is preferable to obtain low-noise performance, high gain, and linearity. By using an inductor as the bias feed, becomes constant and can increase in the large-signal region to extend its output power.

Diode and Transistor bias for Linear Power Amplifiers

The use of Class-A and Class-AB amplifiers for linear power amplification relies on the use of a standing bias current, applied to the base (in case of BJT) in order to bias the RF device into partial or full conduction. This bias current must remain constant, despite the varying envelope of the input signal to the amplifier, which will cause significant variations in the collector current (and hence base current) required by the device.

When considering low power RF amplification, simple resistive biasing techniques may be used however, such techniques are not appropriate for medium or high-power amplifiers due to their requirement for low impedance, relative high current, voltage source.

Class-AB Power Amplifier

Diode biasing provides a low impedance voltage source, and requires a high standing current to flow through it than the bias current required by the transistor.

Whether employing diode or transistor bias, it is essential to thermally connect these components to the RF transistor itself. This allows the semiconductor bias components to track the power amplifiers temperature variations, and thus increase/ decrease the 0.7 V placed across Q1s base, maintaining the PAs collector current at a steady DC level. (As the temperatures rise, a silicon semiconductor junctions voltage decreases from its room temperature value of 0.7 V).

Further, in order to force PA bias stability no matter what the input and output RF power levels may be, the standing current through the diode or transistor bias components must be high enough to permit a steady voltage to be maintained across the PAs base.

Amplified Diode Bias

The clamping diode circuit presented above can be improved by the addition of an emitter follower to amplify the diode current, and hence reduce the required current through the diode by a factor to the current gain of the transistor used. The circuit employs two diodes in series, since one is required to compensate for the base emitter voltage drop of the transistor.

Bias Modulation Effects The function of a bias network is to supply an appropriate (and constant) voltage or current to the gate or base of the device. If the RF signals or their modulation are concerned, it should appear to be a high impedance at RF, and possibly a very low impedance in the case of modulation signals. The bias design should not allow such signals to pass to any part of the power supply and the reflected back to the input of the active device. Signals at the modulation frequency (or harmonics) are generated by nonlinearities in the base or gate of the active device and these are often reflected, rather than absorbed by matching network. These modulation frequency signals must be absorbed by the bias network and not reflect back to the gate or the base of the device, otherwise there will be a modification of the IM products, and in the symmetry of the side shoulders. Low Source-Impedance Active Biasing Complex Thermal Compensated Bias circuit for Class-AB BJT Power Amplifiers

This biasing scheme for RF power transistor provides near-constant low-frequency (1MHz) small-

signal impedance presented at the base of RF transistor. The R2/R3 ratio it will set the bias current. This bias scheme is capable of providing independent control of bias impedance and class of the

power amplifier for optimum efficiency and linearity. Power MOS-FET bias

Biasing Power FET devices is usually simpler than biasing BJT devices. In many cases is sufficient to provide a bias voltage directly on the gate through suitable impedance. This impedance must be capable of minimizing the amount of RF feeding into the bias supply.

A typical network consists of a voltage supply (a variable voltage regulator) fed via a bias resistor whose primary function is to aid the decoupling of the gate from the bias supply, and a quarter-wave transmission line, which provides the RF isolation between gate and the bias supply. Power GaAs MESFET bias

Optimizing of the MESFET for maximum output power requires the device to be capable of sustaining large peak-voltage and current amplitudes. A typical MESFET current vs voltage (I-V) illustrates that with positive gate bias, the MESFET can conduct current levels of 15% to 20% above saturated drain-source current Ids.

Typically Power MESFET Load line

The maximum current is denoted as Idssm, whereas Idss is measured at zero gate-source bias. The transition from the linear operating region to the current saturation region occurs at the drain-

to-source voltage above the knee voltage Vk. The highest voltage that can exist between the drain and the source is the gate-to-drain

breakdown voltage Vgdb minus the pinch-off voltage Vp. This maximum voltage will be reached only as the drain current approaches zero. The drain-to-source voltages below Vk should be avoided because they imply high microwave

losses in the non-saturation region. Power LDMOS Bias LDMOS transistors are CMOS devices designed for high frequency, high voltage operation.

LDMOS transistors exhibit an annoying characteristic called bias or IDQ drift. All LDMOS parts exhibit the hot carrier injection effect to some degree. Hot carrier injection results in charge build-up in the gate-drain region, which causes the gate field

to change. This is seen by the user as a change in the quiescent current (IDQ) with a fixed gate voltage.

The use of adaptive bias circuits it requires a circuit that adjusts VGS periodically to maintain a constant IDQ.

A simplified circuit of an LDMOS amplifier bias circuit is shown below:

The DC bias on these amplifiers is set by applying a DC voltage to the gate (VGS) and monitoring the drain current (IDD). Ideally, this IDD will be constant over temperature, but since the VGS of LDMOS amplifier devices varies with temperature, some type of temperature compensation is required. One method of setting this DC bias involves using an adjustable reference, DAC, or Digital potentiometer combined with a temperature compensation source, such as a transistor VBE multiplier. A new way to bias an LDMOS amplifier involves digitally converting temperature information and adjusting the DC bias using Look-Up Table (LUT) memory. The memory is programmed at final test using measured parameters from the amplifier circuit being tested. DC bias performance is optimized over the required temperature range. A very simple and effective way to construct the lookup table is to make measurements at two temperatures that represent the target range for the product, and then interpolate values for the other temperatures with a linear regression. A more accurate method would include more temperature points and then interpolate between those points. LDMOS amplifiers also have a characteristic IDD drift overtime (drain current reduces for a given VGS), as well as temperature. This can be addressed with lookup table correction with a slightly higher constant bias offset, so that over time the IDD will drift closer to the target bias value, not further away. LDMOS PA bias example

The gate-source bias voltage is supplied through a voltage divider set by adjusting the potentiometer P1 to control the optimum Q2 drain current Idq. In this example Idq was set to 750 mA to achieve the performances. Deviations from this optimal bias point will result in suboptimal trade-offs of performance parameters such as gain compression and efficiency. The device is more linear, but less efficient for the tune shown here at higher drain voltages. If the user has severe efficiency requirements, 26V may be more suitable on the drain. If the user has more requirements for linearity, 30V on the drain may be more appropriate.

LDMOS Power Amplifier with active bias and regulator

Oscillator Bias Circuits

For the design a low phase-noise oscillator, the biasing circuit should be properly regulated and filtered to avoid any unwanted signal modulation ore noise injection. Variations on the supply voltages or currents may also cause undesirable output power fluctuations and frequency drift.

Oscillator biasing of its amplifier section is employed for multiple reasons: To allow the use of a single VCC; to positions the bias point for a certain class of operation to swamp out any device variations in beta to stabilize the active device over wide temperature variations. some oscillator topologies use noise feedback bias for phase noise cancellation.

For accurate design of the bias of the oscillator to meet the gain and phase conditions (G0dB, Phase shift around the loop=0) the closed-loop feed back can be broken in an open-loop analysis. The circuit can be further tuned for optimal performance, in terms of gain and phase margin. Few bias conditions shall be followed for best oscillator design:

Minimize the oscillators transistor bias current as much as possible, since this can substantially lower the 1/f (flicker) noise frequency of the active device, as well as optimize the BJTs noise figure.

Avoid driving the oscillators transistor too far into compression. Most oscillators are biased for equivalent Class-A operation.

For near-class-A operation oscillator, if limiting is due to cutoff, the oscillation amplitude is proportional to the emitter bias current.

If limiting is due to saturation, the amplitude is proportional to the quiescent dc collector-emitter voltage. These parameters may be established with nearly any desired degree of stability by the selection of bias network type and complexity.

In a well-designed near-class-A oscillator, the frequency is determined primarily by the resonator. As the loaded Q is increased, the active-device reactances become less significant in determining the oscillation frequency. Changes in these parameters from device to device, with temperature and with supply voltage, have less effect.

A simple test of how well the active-device reactances are isolated from the resonator is to observe the operating frequency as the supply voltage is varied.

The simplest method of ensuring near-class-A operation is to design the resonator amplifier cascade with small excess loop gain. The problem with this approach is ensuring that the loop gain does not fall below unity with temperature, device, loading, or other circuit changes. A second problem is that starting in an oscillator with low loop gain is slower.

Oscillator with Noise Feedback cancellation

The DC control PNP transistor Q2 acts both as a DC bias stabilization transistor and a noise feedback.

This type of feedback bias circuit can provide a drastic noise improvement within the loop bandwidth of the circuit used.

The noise sampling is done in the collector of Q1. Q3 connected as a diode provide temperature stabilization. The noise improvement can be expanded to 1 MHz off the carrier if the feedback circuit has the

appropriate gain and exactly 180 phase shift within the required bandwidth.

150MHz Oscillator with Noise cancellation feedback bias

Class-C Power Oscillators When high output power is required, and stability and noise are of less concern, the oscillator may

be biased for class-C operation.

High Power Class-C L-band Oscillator

This oscillator has an output power of 2 watts with an efficiency of nearly 30%. The bias is very stiff. There is no collector resistor and the emitter resistance is only 7.8 ohms. High peak currents, limited primarily by the transistor, flow for a small fraction of the waveform period, but supply substantial power to the tank. RF Bias Circuit Issues

Any emitter bias resistor and emitter capacitor can create low-frequency instability and bias oscillations, as well as increasing the NF and decreasing the gain of an amplifier. This demands that RF transistors have a directly grounded emitter lead, with no emitter feedback caused by the lead wire inductance.

Thermal compensation is a concern for most bias circuitries because the bias point for a particular quiescent current will change with temperature. All devices experience this phenomenon, and in some cases (Bipolar transistors) the current gain will change with a positive coefficient eventually causing device destruction if the thermal effects are not accommodated in a bias circuit.

While a BJT will change at fixed rate of 2.4 mV/C, a FET has an inconsistent bias point rate of change with temperature and therefore will have to be empirically measured over the expected operating temperature range for the device chosen.

Supply Modulation Effects - The variation in the current drawn from the power supply for a linear RF power amplifier ranges from almost zero for Class-A amplifiers, to the full current capability of the supply, for Class-B amplifiers. These large current variations should be isolated from the power supply circuitry (which usually has a poor RF and envelope frequency response) by means of the decoupling network. This filter network should be mounted as close as possible to the required point to ensure that all envelope frequencies are adequately decoupled.

References:

1. RF Circuit Design - C.Bowick 2. High Linearity RF Amplifier Design P. Kenington 3. Oscillator Design and Computer Simulation - R. Rhea 4. Radio Frequency Integrated Circuit Design J. Rogers, C. Plett 5. Low-Noise Amplifiers for Integrated Multi-Mode Direct-Conversion Receivers J. Ryynanen 6. The Design of CMOS Radio Frequency Integrated Circuits T. Lee 7. Complete Wireless Design C. Sayre 8. RF and Microwave Circuits, Measurements, and Modeling M. Golio, J. Golio 9. Microwave Circuit Design Using Linear and Nonlinear Techniques - G.Vendelin, A.Pavio, U.Rohde 10. Radio Frequency Transistors - N. Dye, H. Granberg 11. Crystal Oscillator Circuits R. Matthys 12. RF/Microwave Circuit Design for Wireless Applications U. Rohde, D. Newkirk 13. A Comparison of Various Bipolar Transistor Biasing Circuits AN1293 Agilent 14. Microwave Journal 1996 - 2009

Frequency Multipliers

Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul

There are few approaches how to generate a high frequency signal for microwaves frequencies. Direct Signal Generation -

First approach is to generate the high frequency directly, at the fundamental, using an oscillator

tuned on the desired frequency. Few sensitive issues appears here due to high working frequency as, stability, jitter, phase noise, pulling, pushing, low output power, and cost of the active component to meet the performances.

A FET oscillator may be stabilized by a dielectric resonator. Problems may involve in this situation are: phase noise, frequency stability and accuracy.

Sub-Harmonic Mixer -

Another approach how to minimize the issues of a high frequency oscillator is to use a Sub-Harmonic mixer.

Sub-harmonic mixer

Sub-harmonic mixers are useful at higher frequencies when it can be difficult to produce a suitable

LO signal. They have the LO input at frequency = LO/n. Sub-harmonic mixers use anti-parallel diode pairs and they produce most of their power at odd

products of the input signals. Even products are rejected due to the I-V characteristics of the diodes.

Attenuation of even harmonics is determined by diodes balance. The diode matching is critical in this type of mixers.

The short circuit LO/2 stub at the LO port is a quarter of a wavelength long at the input frequency of LO/2 and so is open circuit. However, at RF frequency this stub is approximately a half wavelength long, so providing a short circuit to the RF signal.

At the RF input the open circuit LO/2 stub presents a good open circuit to the RF but is a quarter wavelength long at the frequency LO/2 and so is short circuit.

Up-Conversion Mixer - The third option to generate a high frequency signal is to use an up converter. The design of an up

converter has typically received much less attention in terms of design methodology than down converter design, which is common approach in most of the receiver designs. There are some aspects to up converter design which are not relevant to down converters, and vice versa.

An up-conversion mixer requires high linearity and low noise to minimize the amount of spurious power spread into adjacent channels. Have to take careful attention at LO amplitude, and LO-to-RF isolation.

A good approach for an up-conversion mixer is the balanced mixer which provides good common-mode rejection to suppress LO feed-through and good linearity.

The LO level should provide a reasonable compromise between conversion gain and LO power, but should not limit the 1 dB gain-compression input voltage.

Balanced up-conversion mixer

Frequency Multipliers

Another alternative method to generate high frequency signal power with low phase noise is to

generate a high-quality lower frequency signal and employ a frequency multiplier to deliver the high frequency output at the desired frequency. This approach is the subject of this paper.

Frequency multipliers will always be a way of generating the highest frequencies.

A frequency multiplier has the property that the frequency of the output signal has an integer

multiple of the input frequency.

This approach is commonly adopted in microwave transceivers.

Frequency multiplier based microwave transceiver block diagram

Even if a multiplier introduces no Phase Noise of its own, the process of frequency multiplication even by an ideal, noiseless multiplier, inevitably increases the Phase Noise. The reason for this unfortunate characteristic is that a frequency multiplier is in fact a phase

multiplier, so it multiplies the phase deviations as well as the frequency of the input signal. A square-wave contains odd harmonics. However, by varying the duty cycle of the waveform, so that

rectangular-wave results, even order harmonic content can be introduced. The 2nd harmonic content of a rectangular-wave peaks when the duty cycle is 25%, and a 3rd harmonic

peaks when duty cycle peaks 16%. The minimum Carrier-to-Noise degradation, CNR, in decibels, caused by an ideal frequency

multiplier is: CNR[dB] = 20*LOG (N) where N is the multiplication factor.

Thus, a frequency doubler (N=2) degrades CNR at the input signal by at least 6dB and a

quadrupler (N=4) degrades CNR by at least 12dB. Multiplying a very stable low-frequency reference signal can still produce signals with better

Phase Noise than producing them directly in the microwave frequency range.

For example typical Phase Noise of a 10 MHz Crystal Oscillator is: -170 dBc/Hz @ 100 kHz offset. Using a multiplier chain (10 x 24 = 240) to get a 2.4 GHz signal, degrades this Phase Noise by

20*LOG(240) = 48 dB, yielding: -170 dBc/Hz + 48 dB = -122 dBc/Hz @ 100 kHz offset. Compare this Phase Noise to a standard LC-tank oscillator working directly at 2.4 GHz, which has

a typical Phase Noise of -100dBc/Hz @ 100 kHz offset. A frequency multiplier circuit should contain a nonlinear device and filters that enable to select the desired component at the output and separate the source from the generated harmonics.

Frequency Multiplier Chain with Filters

The nonlinear device will produce voltages of higher order from the current of the first harmonic.

One of these voltages is of the desired order and will be allowed to exit through the band-pass filter. Low-pass and band-pass filters will present high impedance to all unwanted harmonic voltages.

But it turns out that if we allow the currents of the other harmonics to flow, the intermodulation products of those harmonics will contribute to the desired harmonic of the output frequency. That means we should try to short the currents of the non-desired harmonics.

As we want to deliver as much power as possible to the load the frequency multiplier should be matched at the input (for the input frequency) and at the output (for the output frequency).

To obtain higher order frequency multiplication we can cascade several multipliers. This can increase conversion efficiency but also increases complexity. There are different possibilities concerning the nonlinear device:

We need a device with a nonlinear characteristic in order to produce higher order harmonics. The nonlinear characteristic might be a nonlinear I-V or C-V relationship. Usually wideband multipliers use a nonlinear I-V characteristic, but when we want to design a

frequency multiplier with high efficiency, and not high bandwidth, we prefer the nonlinear C-V characteristic. For example a varactor diode has a nonlinear C-V characteristic.

Frequency Multipliers Waveforms

Any non-sinewave repetitive waveform contains energy at harmonics of the fundamental frequency.

The task is to create a non-linear circuit that produces a waveform with significant signal strength at the desired harmonics.

Figure below shows the amplitude terms (peak value of the nth harmonic sine wave) for various waveforms.

Harmonic amplitude terms for various waveforms (C. Wenzel)

Can be seen that waveforms with fast edges have larger high frequency harmonics. Harmonics without vertical edges have n2 in the denominator, but the waveforms with fast edges

only have n in the denominator. The timing (duty-cycle) between the positive and negative edges of a pulse determines which

harmonics are emphasized. For example, a 50% duty-cycle square-wave has only odd harmonics. In this situation the timing is wrong for the buildup of even-harmonic energy, but a 25% duty-cycle contains large even harmonics: the edges occur at the right time to reinforce certain even harmonics.

Figure below shows the harmonic content of a square pulse as a function of its duty-cycle.

Square Pulse Harmonic content vs Duty-Cycle (C. Wenzel)

As was mentioned before the chart suggests that the most 2nd harmonic energy will be generated when the duty-cycle is 25%. But it can also be seen that if the duty-cycle is increased to 33% then the third harmonic drops to zero which could simplify output filtering with little drop in the desired 2nd harmonic.

Frequency Multipliers Characteristics

Conversion Loss and Maximum Input Signal Power Semiconductor diodes used in microwave frequency multipliers are essentially lossy passive devices and for this reason they dissipate energy. Embedding circuits also dissipate energy. As a result, multipliers input/output power conversion efficiency is less than unity. Conversion Loss used to characterize microwave frequency multipliers conversion efficiency is defined as the ratio of the available source power Pin_source to the output harmonic power Pout_harmonic delivered to the load. Conversion Efficiency is defined as the ratio of the output power Pout delivered to the load to the available power of the input source Pin, and usually is expressed in percent. The goal of the circuit design is to minimize the conversion loss (or maximize the conversion efficiency) for a given device and input/output frequencies. When get low conversion efficiency, virtually all the input power is dissipated in the nonlinear element. The maximum input power is limited by the device power handling capability and must be clearly stated when specifying a frequency multiplier. Source and Load Impedance One of the conditions for a diode frequency multiplier to achieve minimum conversion loss is that optimum source and load impedances should be provided to the diode. The source impedance should be very close to the complex conjugate of the multiplier input impedance Zin to minimize reflection loss at the input. The load impedance should be equal to the optimum load value, otherwise leads to an increased conversion loss or decreased output power. Bandwidth BW represents the output or input frequency range over which conversion loss is in the specified limits. Harmonics A nonlinear device produce undesired harmonics along with the desired ones, and this might affect the performance of the system where the multiplier is used. Noise Conversion In all practical situations the resulting noise sidebands are subject of frequency conversion together with the carrier. The multiplier devices add their own noise, and is important to predict the resulting output noise spectrum. Phase Noise Conversion All frequency multipliers will increase the phase noise by the same factor (N) that they multiply, because frequency and phase are both multiplied. In dB this would be 20 log N.

Diode Frequency Multipliers

Diode frequency multipliers can be generally classified as being of varistor (Schottky barrier diode) or varactor type. In the first case, frequency multiplication is performed by a nonlinear resistance or conductance with consequent poor conversion efficiency but a very large potential bandwidth.

In the varactor case a nonlinear reactive element (with nonlinear capacitance) is used. Varactor type multipliers have high potential conversion efficiency, but exhibit a narrow bandwidth

and a high sensitivity to operating conditions, and sometimes stability problems. In theory, a cascade of low-order multipliers usually has greater efficiency than a single high-order

multiplier, but must consider the additional losses in cascading two multipliers (it is invariably necessary to use an isolator between them), and especially the additional cost.

Resistive (Varistor) Frequency Multipliers

Resistive frequency multipliers use the nonlinear I-V characteristic of a Schottky-barrier diode to distort a sinusoidal waveform. This distortion generates harmonics.

The more is distorting the input sinusoid, the greater the harmonic currents in the diode, but the maximum still not very great because resistive frequency multipliers are not very efficient.

In theory a diode doublers have 6dB conversion loss (1/N2) but in reality the conversion loss is about 10dB and there is no reason to make higher-harmonic resistive multipliers.

The advantage of resistive multipliers is, they are very broadband.

Simplified model of a Resistive (diode) Frequency Doubler

The parallel LC resonators are ideal because they short-circuit the diode at the unwanted

harmonics, decoupling the input from the output, and put the diode in parallel with the input at the fundamental frequency and in parallel with the output at the second harmonic. The inductor can be tapped to optimize the source and load impedances of the diode. The frequency doubler using microstrip lines presented below is suitable for microwave frequencies. - The circuit use a /4 at fo, short-circuited through a stub at the input side of the Schottky diode (which is equivalent to /2 at 2xfo), which is used to create a short-circuit at 2xfo to prevent the output power generated in the diode from traveling backward. - Similarly use a /4 at fo open-ended stub at the output side, which creates an RF short at fo and causes the input signal penetrating through the diode to be reflected back to the diode. - A section of the transmission line is used as an inductor to resonate the diode junction capacitance. - The /4 impedance transformers at the input and output are used to transform 50 ohms source and load to optimum diode impedance terminations.

Microwave Microstrip Frequency Doubler

Varactor Diode Frequency Multipliers

A nonlinear reactance also can distort the sinusoidal signal. The pros and cons of varactor multiplier are the opposite of those of resistive multiplier. A varactor is capable of higher efficiency and higher power than a resistive multiplier, theoretically

100% for all harmonics, but they are very narrowband. A design issue of varactor multipliers is they are extreme sensitive to almost every parameter of

the circuit, and small changes in the circuit parameters (tuning reactances, bias voltages, input power level, etc) change the output power.

Making a varactor multiplier work (and keep working) needs a lot of empirical tuning. Varactor diode frequency multipliers in general generate very little noise (phase- as well as

amplitude noise). The only noise source is the thermal noise of the series resistance of the varactor and the circuit loss resistances.

The power capability of a varactor multiplier is limited by the devices break-down. The varactor always has a parasitic resistance in series, which dissipates power.

In order to minimize the loss power, one would tend to present an open for all the undesired harmonics, resulting in zero current and therefore no loss. At the example of the pure square-law diode we see that it produces only a 2nd order harmonic directly. This is the reason to present a short to the undesired (intermediate) harmonics.

The shorting circuits are called idlers. Without idlers the varactor multiplier does not generate harmonics efficiently beyond the 2nd

harmonic. If a current at the 2nd harmonic is prohibited, we dont get the desired higher order harmonics. If current is allowed at the 2nd harmonic, it will mix with the first harmonic and generate therefore

higher order harmonics. A varactor tripler (x3) can be obtained only with a second harmonic idler. A varactor quadrupler (x4) could have a 2nd harmonic idler, or both a 2nd harmonic and a 3rd

harmonic idler. A varactor quintupler (x5) would likely have at least 2nd and 3rd harmonic idlers. Idlers are usually realized as short-circuit resonators that are separate from the input and output

matching circuits. In practice, idlers are usually realized by a series resonance that is chosen more for its convenience

than for high performance. Frequently, the series resonance of the varactors package is used as an idler at high frequencies,

and tuning elements are often included to tune the resonance precisely to the desired harmonic. To minimize power dissipation and thus to obtain high efficiency, is essential to use high unloaded

Q (low-loss) idler resonators. Both phase noise and amplitude noise are strongly dependent on the level of the input signal

pumping the diode. Varactor frequency multipliers are relative unstable. Their instability is a kind of chaotic process,

not a simple oscillation. Controlling the broadband embedding impedance characteristic very carefully is the best way to insure good stability. In particular, the input source and output load must be linear and not vary with input or output level. One must not drive a mixers LO port directly from a multiplier, or the multiplier directly from another multiplier; an isolator should be used. The input and output networks must not have any spurious resonances.

Introducing a resistor in the diodes DC return path, this current can be used to bias the diode. The resistor also helps to reduce the sensitivity of the output power level to the input power level; as input drive is increased, the resulting increase in DC current further reverse-biases the diode, reducing the multipliers efficiency and leveling the output power. The design of the bias circuit often has a strong effect on stability. Low frequency resonances in the bias circuit are a common cause of instability.

Lumped elements Frequency Tripler Distributed Elements Frequency Doubler

A variant of varactors are Schottky-Barrier varactor diodes which can obtain output frequencies of up

to several hundred of GHz.

One of the most important advantages of Schottky-Barrier based multipliers is the generation of odd harmonics without filtering the even ones.

This capability is based on the symmetry of the electrical characteristics for unbiased devices. Thus, the load impedances for even harmonics have no effect on the efficiency characteristic.

Step Recovery Diode and PIN Diode Frequency Multipliers Step Recovery Diodes (also called snap-off diodes) are based on a PIN configuration. They are commonly employed in the design of frequency multipliers of high order. Step Recovery Diodes have relatively little capacitance change under reverse bias and are used for higher efficiency applications. A conventional step recovery diode multiplier consists of a diode, a biasing resistor, and matching filters at input and output. The output filter reflects the un-tuned harmonics back to the diode where they mix to form additional power at the tuned frequency.

Step Recovery Diodes do not require idler circuits to enhance efficiency (as varactors). The SRD multiplier is a reactive multiplier and theoretically doesnt have the efficiency limitation

(1/N2) as resistive multipliers. In the design of high-order frequency multipliers, the efficiency of Step Recovery Diodes is much

higher than that of varactor diodes. There is, however, a limit to the output frequency of the multiplier circuit.

Single Diode multiplier is useful mainly for low-cost, low-performance applications or high frequency waveguide structures where fundamental frequency is easy to reject. A single diode multiplier has the advantage of easy to provide DC bias to it, which will help optimizing the multiplier. A conventional diode multiplier can use one diode or an anti-parallel pair of diodes. The additional diode results in the suppression of even order products, the enhancement of odd order products, and the elimination of the bias resistor.

Single diode multipliers lumped and distributed elements

Single Diode Multiplier Anti-Parallel pair of Diodes Balanced Diode Multipliers have significant advantages compared to single-ended multipliers; the most important are increased output power and inherent rejection of the fundamental frequency and of certain unwanted harmonics. The input or load impedance of a balanced multiplier in some cases differs by a factor of two from that of a single-diode multiplier; therefore, a balanced multiplier sometimes provides more satisfactory input or load impedance. The antiparallel diode connection is probably the simplest form of a balanced multiplier; it rejects even harmonics of the input frequency and consequently can be used only as an odd-order multiplier. In an antiparallel-diode multiplier, each diode effectively short circuits the other at the second harmonic, so each diode acts as a type of idler for the other. This circuit does not reject the fundamental frequency, however, so it requires an output filter.

x5 Frequency Multiplier using anti-parallel PIN diodes

The above circuit is an x5 multiplier operating from a 100 MHz input at +13 dBm, and frequency output at

500MHz and level at about -6dBm. The input was matched with a shunt inductor, and other passive components were added to the output to provide filtering of unwanted signals. Because the stability of a varactor multiplier is sensitive to small unbalance between the diodes, varactor multipliers are rarely realized as anti-parallel circuits.

Frequency Tripler using Step Recovery Diodes The circuit below shows a singly balanced multiplier using a balun transformer. The difference compared to a DC power supply circuit (which looks like) is, that in a power supply we are looking only for DC component, filtering all the harmonics, when here we are looking for 2nd harmonic, shorting the DC current using an RF choke.

Singly Balanced frequency doublers using: Transformer balun, Microstrip balun and Rat-Race Hybrid

The Bridge Rectifier circuit is a practical way to realize resistive frequency doublers. The design of these multipliers is not the same as the design of a diode ring mixer because the diodes are connected as in a different manner. The ring mixers require baluns when the bridge rectifier requires transformers. The voltage and current waveforms in the balanced bridge multiplier are identical to those of a full-wave rectifier in a DC power supply. The current consists of a train of half-sinusoidal pulses, which has no odd harmonic components. Thus, the multiplier inherently rejects the two most troublesome harmonics, the first and third, and the fourth is usually weak enough to require little or no filtering.

Bridge Diode Frequency Doubler Charles Wenzel got an RF Design Award for the bridge frequency tripler presented below.

Wenzel Bridge Diode Frequency Tripler

How the circuit works:

The heart of the multiplier is a sinewave to squarewave converter circuit, which basically is simply a full-wave bridge diode (Schottky barrier) with an inductor short-circuiting the DC terminals.

The inductor is chosen to have high impedance at the operating frequency so that an AC input results in DC in the inductor.

This DC flows through alternate pairs of diodes due to the commuting action of the input voltage. Therefore, if one AC terminal of the bridge is driven with low impedance sinewave, the other AC

terminal will supply a squarewave to a low impedance load. The load must have low impedance since the compliance of this current source is exactly equal to

the input voltage. Because the diodes switch at the input signals zero crossing the circuit introduce a minimum of

AM/PM conversion. The input matching network it provides a low impedance to ground for the switching current; and it

isolates the input from the switching current. The output network presents the required low impedance to the bridge while directing the desired

harmonic to the output. The conversion efficiency is as high as diode frequency doublers, even though the multiplication

factor is higher. Active Frequency Multipliers The main reason using active frequency multipliers is they got better efficiency compared to diode frequency multipliers, at the expense they have worst noise levels compared to varactor diodes. In contrast to diode multipliers which always exhibit loss, FETs or BJTs multipliers can achieve conversion gain over broad bandwidth while getting also good DC to RF efficiency. The same as amplifiers the active frequency multipliers work in different classes. A practical form for an active frequency multiplier is to operate in equivalent Class-B power class, where they are very stable and have good gain, efficiency, and output power.

An active FET frequency multiplier generates harmonics by rectifying the sinusoidal input signal when is biased near its turn-on point (pinch-off), and the input sinusoid turns the device on over part of its cycle.

The condition is obtained by applying a positive drain voltage and a negative voltage to the gate. A practical application is to replace the negative supply to a self-bias source resistance, and a gate grounding resistor.

The duty cycle of the input signal is adjusted to maximize the desired output harmonic. The higher the harmonic, the shorter the duty cycle must be. For a frequency doubler the optimum duty cycle is about 25% (1/4) when for a frequency tripler is

about 16% (1/6). Figure below shows the circuit of a basic broadband frequency multiplier that uses an ideal FET.

Broadband Active Frequency Multiplier (FET)

The output resonator is tuned to the nth harmonic of the excitation frequency, so it short circuits

the FETs drain at other frequencies, especially the excitation frequency (fo) by using an /4 open stub.

The gate-bias voltage Vg in an efficient FET multiplier must be equal to or less than (more negative than) the threshold voltage, Vt. In this case the FETs channel conducts only during the positive half of the excitation cycle, and the drain conducts in pulses; the shape of the pulses is approximately a rectified cosine.

The duty cycle of the pulses varies with the DC gate bias, Vg. If Vg = Vt the duty cycle is 50%, If Vg < Vt (the usual situation), the FET is turned off over most of the excitation cycle. The duty

cycle in this case is less than 50%. If Vg is much smaller than Vt the magnitude of the peak reverse voltage establishes a limit on the

difference. The second important bias point (after Class-B) is with zero gate voltage, which sometimes is referred as Class-A multiplier. This bias point should give the same performance as the pinch-off, if the gate voltage swings from zero to pinch-off and a low-impedance is connected to the drain. Microwave transistors are unconditionally stable only within certain frequency ranges, usually above a certain minimum frequency, and we know that the load termination at the fundamental frequency has a major effect on circuit stability.

Because the load termination controls the series and parallel resonance of the transistor parasitics, and is controlling the peak of the rectified current or the distorted drain voltage, it will affect the multiplier gain, input impedance and bandwidth.

The proper drain termination is the one that induces the highest peak current. This is obtaining by short-circuit at the fundamental frequency. Ideally the load should be short circuit at all harmonic

frequencies, but the presence of a load at a specific harmonic deviates the signal trajectory in the input plane and the load line becomes a function of frequency.

Sometimes using other terminations, especially an open-circuit drain termination at the fundamental frequency, has advantages over a short circuit. The primary advantage of using other terminations is that greater gain can be achieved, although the increase in gain usually is the result of undesirable feedback and getting unpredictable oscillation.

To get a good conversion gain the input power should not be very high. The required input power is proportional to square of fo (fo2), so the required input power increases 6 dB per octave; or, in other terms, the available gain decreases by 6 dB per octave. If the input is well matched across a broad bandwidth, a gain slope inevitably results.

The generation of harmonics using FET transistors can be done not only from current or voltage clipping, but also due to mixing of fundamental frequency, and any one of the generated harmonics. One way to use mixing is to reflect all generated harmonics back to the drain and the other is to feed them back to the gate.

The initial step in an active multiplier design is to find the performances of the active device at fundamental frequency, looking to parameters as: transconductance gm, transition frequency ft, and the maximum oscillation frequency fmax.

The transconductance (gm) has a direct impact in the devices power performance and multiplication gain, and ft and fmax determined the limits to be used as a frequency multiplier.

Harmonic Load Pull Test This is a method which employs no device model and is essentially an experimental process. This method is very useful designing a nonlinear frequency multiplier.

The active device is inserted into a circuit that has the input tuned at the fundamental frequency and the output tuned at the desired harmonic frequency.

The active device is than removed and the matching networks are measured using a Vector Network Analyzer, getting the desired impedances which to be applied to the device.

After that, a conventional linear simulator could be used to synthesize the matching network. Frequency FET Doublers Below is presented a High-Frequency Doubler using a high frequency FET transistor.

High-Frequency FET Doubler

To get good input VSWR and maximum power transfer, the input is conjugate matched using

microstrip distributed and lumped elements. For moderate bandwidth (less than 30% of the center frequency), can resonate the input

capacitance with a series inductor. For uniform conversion gain may need to match the input best at highest frequency of the band.

The output matching network it consists of a filter, to short-circuit the drain at the fundamental frequency and unwanted harmonics, followed by a matching transformer.

A half-wave filter is ideal for the output; it consists of a cascade of alternating high- and low-impedance transmission-line sections, each /4 long at fo; these sections are /2 long at 2*fo and 3/4 long at 3*fo. So, the frequencies of maximum rejection occur at fo and 3*fo, but the filter has no rejection at the output frequency 2*fo.

The imperfect output termination could make the multiplier unstable and cause fundamental frequency leakage.

The Narrow-band Frequency Doubler presented below contains the matching transmission line elements TL1 and TL2, and the bias filter elements TL3 and TL4.

Single Ended Frequency Doubler Narrowband

The drain circuit use the transmission line phase-shifter TL5 to adjust the phase of the

fundamental frequency impedance, and a harmonic band pass filter. The output BPF it is composed of /4 transmission lines TL6, TL7 and TL8, which block the

fundamental frequency and the 3rd harmonic, and present 50 ohms termination at the 2nd harmonic.

The electrical angles (phase) of the gate and drain transmission lines, TL5 and TL6, affect the multiplication gain up to 3dB.

The drain bias filter is composed of elements TL9 and TL10 and their function is to isolate the bias from the generated 2nd harmonic.

The RC circuit in parallel with the power supply is for overall stabilization. The Wide-band Frequency Doubler presented below use a transmission line (TL5) in series with the output BPF to adjust the phase of the impedance at the fundamental frequency.

Single Ended Frequency Doubler - Wideband

The BPF rejects the fundamental and the 3rd harmonic frequencies. There is also a band-stop filter (TL7, TL8, TL9) which blocks the 2nd harmonic, and presents low-loss at fundamental and 3rd harmonic.

Frequency FET Triplers An important difficulty in frequency triplers is the need to short circuit the drain at the unwanted

harmonics. For example a frequency doubler is easy to do using a /4 stub, which effectively shorts the first

and third harmonic, while the fourth and higher harmonics are weak enough to neglect. But is not very simple for terminating the drain in a frequency tripler.

The output network can be difficult to design; the inevitable result is a suboptimum termination, which makes very hard to optimize efficiency and get the risk of instability.

This is an example of a FET frequency tripler:

FET Frequency Tripler

The input stub, grounded at high frequencies by a capacitor, provides a match for the fundamental

input frequency, while in the same time it facilitates bias injection at the gate of the FET device by providing some decoupling.

The bias scheme adopted for the frequency tripler was a self-bias arrangement with resistor between source and ground. Such a self-bias configuration tends to bias a FET device towards pinch-off, with the resistor value determining how close the device is to pinch-off. The larger the value of the closer the bias point is to pinch-off. If the gate bias is connected to an external supply, an option effectively to over-write the self-bias setup is made available.

At the output, a double stub arrangement has been placed. These stubs get multiple functions. First, they form an output match for the desired 3rd harmonic signal. Secondly, they implement some filtering of undesirable fundamental and 2nd harmonic leakage to the output. Using here the real life stubs, it can be difficult to filter the fundamental without rejecting the desired 3rd harmonic at the same time. This happened when considers the simplest stub arrangement to reject the fundamental, which is an open circuit /4 stub. However, such a stub is long 3/4 at the 3rd harmonic and tends to reject this frequency as well. As a consequence, the design of the output stub pair involved a compromise in terms of fundamental and 2nd harmonic rejection, without excessively loading the 3rd harmonic response.

The output stubs is essentially a short circuit stub, the high frequency short being provided by a capacitor to ground. This stub also facilitates drain bias injection.

Balanced Frequency Multipliers Reasons using of Balanced Frequency Multipliers are:

they have improved input match over wide bandwidth, they have good isolation between multiplier stages, they are very stable since the device is terminated in 50 ohms over a wideband frequency.

Balanced Frequency Doubler using Branch Line Hybrids

Branch Line Hybrid and the Distributed and Lumped equivalents

The input hybrid coupler introduces a 90 phase shift and the output hybrid another 90. Therefore, the odd harmonics are 180 out of phase, are cancelled at the output port, and

dissipated at the coupler termination. The even harmonics at the output port are in phase and added in power. A balanced multiplier has 3dB greater output power than an equivalent single-device circuit. The main bandwidth limitation is given by the FETs input and output matching networks not

matched for wideband response. The circuit is self-biased using TL3 and Rg gate to the ground and Rs as source resistor. The bias

is chosen to be near pinch-off point. Balanced to Unbalanced Frequency Doubler Another option is to use only at the input a 180 Rat-Race hybrid to drive each device in anti-phase.

In this way the fundamental drain currents are also in anti-phase and good rejection is obtained by paralleling both drains, and the drain connection point becomes a virtual ground for fundamental and for all odd harmonics.

The even harmonics of the drain currents in the two FETs have no phase difference, however, so the drain-current components at those frequencies combine in phase at the output.

Balanced to Unbalanced Frequency Doubler using Rat-Race Hybrid

Rat-Race Hybrid and the Distributed and Lumped equivalents

To get a constant gain at the output, the gates matching networks are designed for maximum gain

at fundamental high-end and around 3dB less gain at the low-end of the useful band. The disadvantage of this topology is sensitivity to device DC imbalances and input matching

networks, compared to the balanced multiplier using hybrids at both, input and output. Any imbalance is reflected back to the generator requiring an attenuator at the input to minimize

the resulting standing wave. Balanced Frequency Doubler using Active Balun The frequency doubler using an active balun presented below is suitable for small size circuits, replacing the passive balun topologies.

Balanced Frequency Doubler using Active Balun

In this frequency doubler, a simple combination of Common-Gate FET and Common-Source FET provides the required 180 phase difference for the cancellation of the fundamental.

This active balun has the advantage getting small size at low frequencies. The stability has to be controlled, in contrast to a passive balun, and the circuit should be

unconditionally stable for all input impedance attached. To get unconditional stability and to avoid negative resistances at gate and drain of the Common-

Gate FET, a series resistance Rg, is added to gate. This reduces the gain, but it improves stability by decreasing the loop gain at the same time. In addition, two series resistors Rd are added in both drain connectors to decrease the loop gain.

The frequency doubler has a short-circuited stub TL4 and a series transmission line TL3 for an output impedance adjustment at the connection of the two drains. These elements provide a short for the fundamental and additional match for the 2nd harmonic.

The bias point was chosen at Vg=0 to obtain high fundamental suppression and 2nd harmonic.

Balanced Frequency Tripler

Balanced Frequency Tripler

The input match is made with open-circuited stubs TL1, and high-impedance lines TL2. The /4 TL3 connecting both inputs introduces a short at the 2nd harmonic, improving the

performance. The output match contains only a /4 high impedance transmission lines TL4, to parallel tune the

drain output impedance at the fundamental frequency. The device is self-biased and the source resistor Rs is decoupled with Cs.

Higher Order FET Frequency Multipliers

The direct generation of harmonics of higher order can be obtained by biasing the device at different conduction angles.

For even order the device is biased in Class-AB similar for frequency doubler, in order to maintain a rectified sinusoidal drain current which is reach in even harmonics.

For odd order harmonics the optimum bias condition is the one that generates an output waveform with distorted positive and negative peaks. The first option would be to bias the device in Calss-A, about the center of the drain current, and apply a high power at the gate.

The magnitude of higher harmonic components like 5th, 6th, 7th, etc, becomes too small, requiring a high load resistance to compensate the reduction in output power.

BJT Frequency Multipliers The theory of bipolar multipliers is essentially the same as that of FET multipliers. A few notes on the differences, however, are in order.

Unlike FETs, whose channel currents are limited to a little over Idss, bipolar devices do not have such a strict limit.

Silicon BJTs experience high-level injection effects, which tend to limit the peak current and reduce transconductance at high collector current.

Bipolar devices have a large, strongly nonlinear base-to-emitter capacitance. Because of that capacitance, BJT multipliers are susceptible to modes of oscillation that are not unlike those of junction varactor multipliers for example. As with varactors, the best (and simplest) way to avoid such instability is to short-circuit the base and drain at all unwanted harmonics. Have to verify also that active DC bias supplies do not exhibit negative resistance or couple the collector to the base at low frequencies.

Because multiplying devices are turned off under quiescent conditions, BJT multipliers should not be current-biased; they must be biased from a voltage source, ideally with a series resistance.

BJT Frequency Tripler

Balanced Push-Push Harmonic Oscillator Another option generating high frequency signal, using most of the characteristics of the frequency multipliers, is the Harmonic Oscillator. Below is presented an example of a balanced harmonic oscillator.

Balanced Push-Push Harmonic Oscillator

The push-push harmonic oscillator employing two transistors, each oscillating at one half the

desired output frequency. The transistors oscillate out-of-phase with respect to each other, causing the fundamental

frequency to cancel and the second harmonic to add in phase. Push-push designs have several advantages over other topologies. Designing at one half the

frequency increases resonator Q, decreases the parasitics which appeard, and extends the useful frequency range of transistors.

The dielectric resonator is placed between the two gates transmission lines (TL1) Biasing the circuit in Class-AB, guaranties the start-up and stable oscillation, and also the

generation of even harmonics at the output.

Refrences:

1. Design of FET Frequency Multipliers and Harmonic Oscillators E. Camargo 2. Nonlinear Microwave and RF Circuits S. Maas 3. The RF and Microwave Circuit Design Cookbook S. Maas 4. Microwave and Millimeter-Wave Diode Frequency Multipliers M. Faber, J. Chramiec, M.

Adamski 5. Microwave Communications Engineering - Volume 1 I.A. Glover, S.R. Pennock, P.R. Shepherd 6. Millimeter-Wave Integrated Circuits E. Carey, S. Lidholm 7. Varactor Frequency Tripler R. Zingg 8. New Topology Multiplier Generates Odd Harmonics C. Wenzel 9. Choosing a Frequency Multipliers Waveform C. Wenzel 10. A Highly Integrated Ka- band MMIC Quadrupler K. Kamozaki, T. Bos, E. Camargo 11. Low Cost Frequency Multipliers Using Surface Mount PIN Diode Application Note Agilent 12. RF Design Magazine, 1990 2005 13. Microwave Journal Magazine, 1996 2010 14. High Frequency Electronics Magazine, 1996 2010 15. Microwaves & RF Magazine, 2000 2010

Impedance Matching

Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul/

Reactance and LC Resonance Reactance X is a measure of the opposition to the current of Capacitance C and Inductance L.

Reactance is measured in ohms and varies with the frequency of the AC signal. Reactance takes two forms - Inductive (XL), and Capacitive (XC).

XL = *L = 2**f*L XC = 1 / (*C) = 1 / (2**f*C) Where: is angular frequency, f is frequency, L is inductance, and C is capacitance.

When the magnitudes of L reactance and C reactance are equal, the L-C pair resonates. At resonance the net reactance of a series-connected L-C circuit is zero (a short circuit), and the

net reactance of a parallel-connected L-C circuit is infinite (an open circuit). The resonant frequency is getting by equating the magnitudes of the L and C reactances (XL = XC)

Q-Factor The quality factor (Q) serves as a measure of a reactances purity (how close it is to being a pure

reactance, and not a resistance), and is defined as the ratio of the energy stored in a component to the energy dissipated by the component.

Q is a dimensionless unit and is expressed function of reactance X and resistance R as: Q = X / R

It should be stated that Q of the L-C circuit is defined at circuit resonance. If the circuit reactance is plotted as a function of frequency, the slope of the reactance at

resonance is a measure of Q. The quality factor Q of a reactive component (inductor or a capacitor) is the ratio of its reactance

magnitude to its resistance.

Q of an inductor: Q of a capacitor: Unloaded-Q

The loaded quality factor QL is the ratio of the magnitude of the reactance of either L or C at resonance, to the total circuit resistance

In real physical reactive elements there are always some resistive losses. The loss in a component (a capacitor or an inductor) can be described in terms of its Q.

For example, if a lossy inductor is placed in parallel with a lossless capacitor, the Q of the resulting parallel circuit is almost equal to the Q of the inductor.

The unloaded-Q (QU) is the Q associated with the reactive elements only (i.e., without the load).

Loaded-Q

The loaded Q of a resonant circuit is dependent upon three main factors: 1. The source resistance (Rs). 2. The load resistance (RL). 3. The component Q-factor as defined above.

Resonant frequency is given by:

The resonant circuit sees an equivalent RP resistance, RS in parallel with RL, as the load. The RP resistance is smaller in value than either RS or RL RP = (RS *RL) / (RS + RL)

To optimize the loaded-Q there are two options. First, we can select the optimum values for source and load impedances, or second, we can use different ratio values for L and C.

Decreasing the RP will decrease the Q of the resonant circuit, and an increase in RP will increase the Q of the circuit. Can get the same effect if we keep RP constant and varying XP.

Example:

Using a parallel L-C circuit, at the same resonant frequency (178MHz), we get different Q values just changing the L and C values, when keeping RP constant (50 ). - If RP = 50 , C = 8pF, L = 100nH, at 178MHz we get: XP = XC = XL = 111.8 , results Q = 0.45 - If RP = 50 ,